JPH0953985A - Signal processing circuit for charge generation type detection element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a signal processing circuit for charge generation type detection element in which a switched capacitor circuit produces an output signal corresponding to the charges from a detection element by providing a circuit for compensating the offset voltage contained in the output signal from switched capacitor circuit. SOLUTION: An infrared sensor 1 is connected with a switched capacitor circuit 2 and an offset voltage compensation circuit 11 comprising a differential operating circuit 12, a sample and hold circuit 15 and an FET 18 is fed back to the output side of switched capacitor circuit 2. During a preparatory period for measurement, the offset voltage contained in an output signal V0 is held as a compensation signal VH in the sample and hold circuit 15. At the time of measurement, the compensation signal VH is applied to the non-inverting terminal of operational amplifier 3 in the switched capacitor circuit 2 in order to compensate for the offset voltage in output signal thus producing an output corresponding to the charges being outputted from the infrared sensor 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for converting an electric charge generated in a charge generation type detection element into a voltage, and in particular, when a piezoelectric type sensor or a pyroelectric type sensor is used as the detection element, a charge change occurs. The present invention relates to a signal processing circuit of a charge generation type detection element which is preferably used as an amount detection circuit and an infrared detection circuit.

[0002]

2. Description of the Related Art In general, among ceramic dielectrics, some ferroelectric ceramics such as barium titanate (BaTiO ₃ ) and lead zirconate titanate (PZT) have piezoelectric or pyroelectric properties. Are known. A charge generation type detection element (hereinafter referred to as a detection element) utilizing these piezoelectricity and pyroelectricity is used for various purposes as a piezoelectric type sensor and a pyroelectric type sensor.

A switched capacitor circuit is widely known as a charge-voltage conversion circuit for converting the charge output from the charge generation type detection element into a voltage.

Here, FIGS. 3 and 4 show examples in which a switched capacitor circuit is used as a signal processing circuit according to the prior art.

In the figure, reference numeral 1 denotes an infrared sensor as a detection element for converting a minute temperature change due to infrared rays into an electric change. The infrared sensor 1 generates an electric charge by receiving infrared rays emitted from an object to be measured. It has a pyroelectric effect.

Reference numeral 2 denotes a switched capacitor circuit as a charge-voltage conversion circuit. The switched capacitor circuit 2 has an operational amplifier 3 having the infrared sensor 1 connected to an inverting input terminal, and an inverting input terminal of the operational amplifier 3. And an output terminal connected between the capacitor 4 and the output terminal, and an integrating capacitor 4 having a capacitance C1 and a field effect transistor (hereinafter referred to as FET5) which is connected in parallel with the capacitor 4 and serves as a switching element for resetting. It is configured.

Further, the non-inverting input terminal of the operational amplifier 3 is connected to the ground, and the gate of the FET 5 receives an external reset signal VR (see (a) in FIG. 4) to turn it on / off. The OFF operation is repeated.

Then, the switched capacitor circuit 2
In, the charge Q generated in the infrared sensor 1 is accumulated in the integrating capacitor 4, and the output signal V0 shown in the following expression 1 is obtained (see (b) in FIG. 4).

[0009]

[Equation 1] V0 = Q / C1

The FET 5 discharges the electric charge Q accumulated in the capacitor 4 by being turned on during the preparation period in which the electric charge Q is not output from the infrared sensor 1 to the switched capacitor circuit 2.

As described above, by using the switched capacitor circuit 2 in the signal processing circuit, the signal processing circuit can be constructed without using a high resistance resistor, and the operational amplifier 3 and the FET 5 can be used to make the circuit monolithic. There is an advantage that it can be realized.

[0012]

By the way, the switched capacitor circuit 2 according to the prior art described above mainly uses a small capacitor as a circuit parameter, and therefore is mainly M
It is fabricated on an OS (Metal Oxide Semi-condactor) type integrated circuit. On the other hand, the noise of the MOS-FET is larger than that of the bipolar element, and there is a problem that this noise is induced through the parasitic capacitance.

The parasitic capacitance is generated between the resistor and the substrate, between the gate, the source and the drain in the FET 5 and between these and the substrate, between the upper and lower electrodes and the substrate in the capacitor 4, and further between the wirings. It occurs between the wiring and the substrate, and changes in the capacitance of the capacitor 4, power supply noise, clock feedthrough described later, and the like occur.

Next, clock feedthrough by parasitic capacitance will be described.

Here, the parasitic capacitance actually generated in the MOS-IC is generated as a parasitic capacitance C0 between the gate of the FET 5 and the inverting input terminal of the operational amplifier as shown by the dotted line in FIG. Then, in the parasitic capacitance C0, when the reset signal VR of the FET 5 is turned off, the electric charge stored in the parasitic capacitance C0 between the gate and the inverting input terminal flows into the capacitor 4.

At this time, when the gate voltage when the FET 5 is switched to OFF is VG, the charge stored in the parasitic capacitance C0 due to the opening and closing of the FET 5 becomes C0 × VG, and this charge is supplied to the capacitor 4 and output. Signal V0
Changes by ΔV 0.

[0017]

[Equation 2]

Therefore, as shown in the output signal V0 'shown in FIG. 4 (b'), D due to the clock feedthrough component is generated.
The voltage ΔV0 corresponding to C is superimposed on the output signal V0 as an offset voltage, and the ideal output signal V as shown in FIG.
You cannot get 0.

Further, since the electric charge generated from the infrared sensor 1 is as small as several pA, a high gain amplifier must be connected to the circuit at the subsequent stage, and this offset voltage ΔV0 is used for highly accurate detection of infrared rays. On the other hand, it becomes a big obstacle.

The present invention has been made in view of the above-mentioned problems of the prior art, and an object of the present invention is to provide a signal processing circuit of a charge generation type detection element capable of removing an offset voltage due to clock feedthrough. There is.

[0021]

In order to solve the above-mentioned problems, a signal processing circuit of a charge generation type detection element according to the invention of claim 1 outputs an electric charge generated from the charge generation type detection element converted into a voltage. The charge-voltage conversion circuit that outputs as a signal, and the offset-voltage compensation circuit that is feedback-connected to the charge-voltage conversion circuit and that compensates the offset voltage included in the output signal output from the charge-voltage conversion circuit Especially.

According to a second aspect of the present invention, the charge-voltage conversion circuit includes an operational amplifier, an integrating capacitor connected between the inverting input terminal and the output terminal of the operational amplifier, and the parallel capacitor. It is composed of a switched capacitor circuit including a connected switching element for resetting.

According to another aspect of the invention, the offset voltage compensating circuit holds an offset voltage in the output signal output from the charge-voltage converting circuit as a compensation signal, and the offset voltage holding means. And a resetting means for resetting the compensation signal held by.

According to a fourth aspect of the invention, the offset voltage holding means is connected to the output side of the charge-voltage conversion circuit, and the difference between the output signal from the charge-voltage conversion circuit and the zero voltage is used as a compensation signal. A differential operation circuit for outputting, a switching element for energizing a compensation signal, which is connected between the differential operation circuit and the charge-voltage conversion circuit, and controls energization of a compensation signal output from the differential operation circuit, and And a sample-hold circuit including a capacitor that temporarily holds the compensation signal output via the switching element, and the reset means resets the compensation signal held by the sample-hold circuit. It is composed of a switching element.

According to a fifth aspect of the present invention, the reset switching element, the compensation signal energizing switching element, and the compensation signal resetting switching element are turned ON / O.
The FF operation is a first operation in which the switching element for resetting and the switching element for resetting the compensation signal are simultaneously turned on in the preparatory period in which no charge is output from the detection element to the charge-voltage conversion circuit, and a reset operation. Operation of turning on the switching element for resetting the compensation signal and turning on the switching element for turning on the compensation signal while turning on the switching element for turning on the switching element for turning on the switching element for turning on the switching element for turning on the switching element for turning on the compensation signal In this state, the resetting switching element is set to the OFF state in the third operation.

[0026]

According to the first aspect of the invention, the signal processing circuit comprises the charge-voltage conversion circuit and the offset voltage compensation circuit for removing the offset voltage contained in the output signal output from the charge-voltage conversion circuit. Therefore, for example, even when the offset voltage is superimposed on the output signal due to the clock feedthrough by the parasitic capacitance in the charge-voltage conversion circuit,
The offset voltage in the output signal can be removed.

According to the invention of claim 2, since the charge-voltage conversion circuit is composed of the switched capacitor circuit, the signal processing circuit can be composed without using a high resistance resistor, and the operational amplifier and the switching element are used. This enables manufacture on a MOS type integrated circuit.

According to a third aspect of the invention, the offset voltage compensating circuit holds the output signal output from the charge-voltage converting circuit as a compensation signal, and the offset voltage holding means. The offset voltage holding means holds the offset voltage due to the clock feedthrough component as a compensation signal during the preparatory period before measurement, and this signal is output from the charge-voltage conversion circuit. The offset voltage due to the clock feedthrough component contained in the output signal can be removed by adding so as to cancel the output signal. Further, it is possible to reset the compensation signal held in the offset voltage holding means by the reset means and hold the offset voltage due to the clock feedthrough component as the compensation signal for each preparation period.

According to the invention of claim 4, since the offset voltage holding means is composed of the differential operation circuit and the sample hold circuit, and the output means is composed of the switching element for resetting the compensation signal, the compensation signal is supplied during the preparation period. Compensation in which the switching element for energization is turned on and the compensation signal detected by the differential operation circuit is held by the sample hold circuit, and the switching element for energization of the compensation signal is turned off and held by the sample hold circuit during the measurement period. The signal is applied to the virtual ground point of the charge-voltage conversion circuit.
As a result, the offset voltage due to the clock feedthrough component contained in the output signal output from the charge-voltage conversion circuit can be removed.

According to the invention of claim 5, the reset switching element, the compensation signal energizing switching element and the compensation signal resetting switching element are turned on.
Since the / OFF operation is set, an offset voltage due to the charges stored in the parasitic capacitance in the charge-voltage conversion circuit is generated during the preparation period, and this offset voltage is held in the sample hold circuit as a compensation signal.

[0031]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment according to the present invention will be described below with reference to FIG.
A description will be given with reference to FIG. In the embodiments, the same components as those of the above-described conventional technique are designated by the same reference numerals, and the description thereof will be omitted.

In the figure, 11 is a switched capacitor circuit 2
The offset voltage compensating circuit according to the present embodiment is provided in the next stage of FIG. Has been done.

The differential operational circuit 12 comprises an operational amplifier 13 and an input resistor 14 connected to the inverting input terminal of the operational amplifier 13, and the inverting input terminal of the operational amplifier 13 is a switched capacitor circuit. 2 is connected to the output side, and the non-inverting input terminal is connected to the ground.
As a result, during the preparatory period during which no charge is output from the infrared sensor 1 to the switched capacitor circuit 2, the output signal V0 output from the switched capacitor circuit 2 and the ground (zero voltage) are output from the output terminal of the differential operation circuit 12. The difference between
That is, the offset voltage ΔV0 is output as the compensation signal VH.

Reference numeral 15 denotes a sample hold circuit according to the present embodiment connected between the differential operation circuit 12 and the switched capacitor circuit 2, and the sample hold circuit 15 is provided.
Is a compensation capacitor 16 having a capacitance C2 connected between the output terminal of the operational amplifier 13 and the ground,
It comprises a FET 17 as a switching element for energizing a compensation signal, which is connected between the capacitor 16 and the output terminal of the differential operation circuit 12. Further, the energization control signal Vi as shown in FIG. 2B is input to the gate of the FET 17 to perform ON / OFF operation. When the FET 17 is turned on, the compensation signal VH output from the differential operation circuit 12 is transferred to the capacitor 1
6 and the capacitor 16 temporarily stores the electric charge corresponding to the compensation signal VH.

Reference numeral 18 denotes an FET as a switching element for resetting the compensation signal, the FET 18 is connected in parallel to the capacitor 16, and the gate of the FET 18 is shown in FIG.
The reset signal VR2 shown in (c) of FIG.
By performing the FF operation, the electric charge stored in the capacitor 16 during the ON operation is discharged and reset. As a result, the non-inverting input terminal of the operational amplifier 3 forming the switched capacitor circuit 2 is grounded to the ground when the FET 18 is in the ON state, and is a virtual contact point set to the negative offset voltage -ΔV0 by the capacitor 16 in the OFF state. Becomes

The reset signal VR1 as shown in FIG. 2A is input to the gate of the FET 5 of the switched capacitor circuit 2 of this embodiment.

Further, the differential operation circuit 12 and the sample hold circuit 15 constitute the offset voltage holding means according to the present invention, and the compensation signal resetting FET 18 constitutes the resetting means according to the present invention.

The signal processing circuit according to this embodiment is constructed as described above. Next, the circuit operation will be described with reference to the waveforms of FIG.

First, during the preparation period in which no charge is output from the infrared sensor 1 to the switched capacitor circuit 2,
A process for generating an offset voltage ΔV0 by clock feedthrough and holding it in the sample hold circuit 15 is performed.

In the first operation of the region (A), the reset signals VR1 and VR2 are simultaneously turned on, the FET 5 is turned on to discharge the electric charge stored in the capacitor 4 of the switched capacitor circuit 2, and the FET 18 is turned on. As a result, the electric charge stored in the capacitor 16 of the sample hold circuit 15 is discharged.

In the second operation of the region (B), the reset signal VR1 is kept in the ON state, the reset signal VR2 is kept in the OFF state, the energization control signal Vi is kept in the ON state, and the FET is turned ON.
At the same time as turning off 18 and turning on FET 17,
The capacitor 16 of the sample hold circuit 15 is set in the charging standby state.

In the third operation of the region (C), the reset signal VR1 is turned off while the energization control signal Vi is kept on, and the offset voltage ΔV0 is intentionally generated to cause the FE.
When T5 is turned off, the electric charge flowing through the parasitic capacitance C0 is accumulated in the capacitor 4. Then, this charge becomes an offset voltage ΔV0 composed of a clock feedthrough component, and is output from the switched capacitor circuit 2 and also input to the differential operation circuit 12.

At this time, the differential operation circuit 12 uses the FET 17
Since a negative feedback circuit is configured through the operational amplifier 3 and the operational amplifier 3, the operational amplifier 13 operates so that the inverting input terminal and the non-inverting input terminal have the same potential, that is, the output signal V0 becomes zero voltage. To do. However, since the offset voltage ΔV0 exists in the actual output signal V0, the operational amplifier 3 of the switched capacitor circuit 2 tries to make the non-inverting input terminal and the inverting input terminal of the same potential. here,
Since the differential arithmetic circuit 12 is electrically connected to the sample hold circuit 15 via the FET 17, the output terminal of the operational amplifier 13 supplies electric charges for setting the respective input terminals of the operational amplifier 3 to the same potential, and The charge of the compensation signal VH is supplied from the output terminal of 13, and the corresponding charge is stored in the capacitor 16. The compensation voltage VH charged in the capacitor 16 has the same potential as the offset voltage ΔV0.

As described above, by the first to third operations, the capacitors 4 and 16 are discharged, and then the offset voltage ΔV0 is intentionally generated to store the compensation signal VH equal to the offset voltage ΔV0 in the capacitor 16. can do.

Next, during the measurement period in which the charge Q is output from the infrared sensor 1 to the switched capacitor circuit 2, the capacitor 16 is connected to the non-inverting input terminal of the operational amplifier 3 of the switched capacitor circuit 2, so The compensation signal VH stored in 16 is input to the non-inverting input terminal. Then, in the operational amplifier 3, the difference between the charge Q input from the infrared sensor 1 and the charge due to the compensation signal VH is integrated by the capacitance C1 of the capacitor 4,
The switched capacitor circuit 2 outputs the output signal V0.

At this time, the offset voltage ΔV0 due to clock feedthrough in the output signal V0 output from the switched capacitor circuit 2 is canceled by the compensation signal VH from the sample hold circuit 15 applied to the non-inverting input terminal of the operational amplifier 3. Can infrared sensor 1
It is possible to obtain an output signal V0 corresponding to the electric charge output from

As described above, in the signal processing circuit according to the present embodiment, the offset voltage .DELTA.V0 due to the clock feedthrough is charged in the capacitor 16 of the sample hold circuit 15 as the compensation signal VH during the preparation period, and this compensation is performed during the measurement period. By outputting the signal VH to the non-inverting input terminal of the switched capacitor circuit 2, the offset voltage .DELTA.V0 contained in the output signal V0 output from the switched capacitor circuit 2 can be removed.

Therefore, even if any parasitic capacitance is generated around the integrating capacitor 4 of the switched capacitor circuit 2, the offset voltage ΔV 0 induced by the parasitic capacitance is different from that of the differential operation circuit 12 of the offset voltage compensation circuit 11. It can be removed from the output signal V0 by the sample hold circuit 15, and the output signal V0 corresponding to the electric charge detected by the infrared sensor 1 can be obtained.

Further, the signal processing circuit according to the present embodiment is constituted by an operational amplifier and an FET so that M
The OS-type integrated circuit can be monolithically manufactured, and can be downsized and the production efficiency can be improved.

Further, since the output signal V0 output from the signal processing circuit is always zero voltage during the measurement period, the amplifier in the subsequent stage can have a high gain and the detection sensitivity is obtained even when the electric charge output from the infrared sensor 1 is minute. Can be increased.

Although the infrared sensor 1 is used as the detection element in the above embodiment, the present invention is not limited to this, and a charge generation type sensor such as a piezoelectric type sensor may be used as the detection element.
Further, the sample hold circuit 15 is connected to the capacitor 16 and F
Although the ET 17 is used, the operational amplifier may be used.

[0052]

As described above in detail, according to the present invention of claim 1, the signal processing circuit includes a charge-voltage conversion circuit and the charge-voltage conversion circuit.
The offset voltage compensating circuit for compensating the offset voltage included in the output signal output from the voltage converting circuit is included, so that the offset voltage is superimposed on the output signal by the clock feedthrough due to the parasitic capacitance in the charge-voltage converting circuit, for example. Even at this time, the offset voltage can be removed from the output signal by the offset voltage compensating circuit, and the output signal corresponding to the charge output from the sensing element can be accurately obtained, and the detection sensitivity can be improved.

According to the second aspect of the invention, since the charge-voltage conversion circuit is composed of the switched capacitor circuit, the signal processing circuit can be composed without using a high resistance resistor, and the MOS is realized by using the operational amplifier and the switching element. It becomes possible to manufacture on the die integrated circuit, and the production efficiency can be improved.

According to the third aspect of the invention, the offset voltage compensating circuit holds the offset voltage holding means for holding the output signal output from the charge-voltage converting circuit as a compensation signal, and the compensation signal held by the offset voltage holding means. The offset voltage holding means holds the offset voltage due to the clock feedthrough component as a compensation signal in the preparatory period before measurement, and outputs the compensation signal from the charge-voltage conversion circuit. By offsetting the signal, the offset voltage included in the output signal can be removed and the output signal can be accurately detected as the output signal corresponding to the charge output from the sensing element. Further, the compensation signal held in the offset voltage holding means is reset by the resetting means, and the offset voltage due to the clock feedthrough component is held as the compensation signal in each preparation period, whereby accurate compensation can be performed.

According to the invention of claim 4, the offset voltage holding means is constituted by the differential operation circuit and the sample hold circuit, and the output means is constituted by the switching element for resetting the compensation signal. The switching element of is turned on and the compensation signal detected by the differential operation circuit is held by the sample hold circuit,
During the measurement period, the switching element for energizing the compensation signal is turned off.
By adding the compensation signal held in the sample-hold circuit in the F state to the virtual ground point of the charge-voltage conversion circuit, the offset voltage due to the clock feedthrough component contained in the output signal output from the charge-voltage conversion circuit can be obtained. Can be removed.

According to the fifth aspect of the invention, the switching element for resetting, the switching element for energizing the compensation signal, and the switching element for resetting the compensation signal are turned on / off.
Since the operation is set, the offset voltage due to the charges stored in the parasitic capacitance in the charge-voltage conversion circuit during the preparation period can be held as a compensation signal in the sample hold circuit, and the offset voltage in the output signal can be reliably removed. You can

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a signal processing circuit according to an embodiment of the present invention.

FIG. 2 is a control signal output to a reset switching element, a control signal output to a compensation signal energizing switching element, a control signal output to a compensation signal reset switching element, and a signal processing circuit according to an embodiment; It is a waveform diagram which shows the output signal each output from.

FIG. 3 is a circuit configuration diagram showing a signal processing circuit according to a conventional technique.

FIG. 4 is a waveform diagram showing respective waveforms of a control signal output to a reset switching element, an output signal output from a signal processing circuit, and an output signal including an offset voltage according to a conventional technique.

[Explanation of symbols]

1 infrared sensor (detection element) 2 switched capacitor circuit (charge-voltage conversion circuit) 3,13 operational amplifier 4,16 capacitor 5 FET (switching element for reset) 11 offset voltage compensation circuit 12 differential operation circuit 15 sample hold circuit 17 FET (compensation signal energizing switching element) 18 FET (compensation signal resetting switching element)

Claims (5)

[Claims] 1. A charge-voltage conversion circuit for outputting an electric charge generated from a charge generation type detection element as an output signal converted into a voltage, and a feedback connection to the charge-voltage conversion circuit. A signal processing circuit for a charge generation type detection element, comprising an offset voltage compensating circuit for compensating an offset voltage included in an output signal to be outputted. 2. The charge-voltage conversion circuit comprises an operational amplifier, an integrating capacitor connected between the inverting input terminal and the output terminal of the operational amplifier, and a reset capacitor connected in parallel with the capacitor. 2. A switched capacitor circuit composed of the switching element according to claim 1.
A signal processing circuit for the charge-generating detection element described. 3. The offset voltage compensating circuit holds an offset voltage holding means for holding an offset voltage in an output signal output from the charge-voltage converting circuit as a compensation signal, and a compensation held by the offset voltage holding means. The signal processing circuit for a charge-generating type detection element according to claim 1 or 2, comprising a reset means for resetting a signal. 4. The differential operation, wherein the offset voltage holding means is connected to an output side of the charge-voltage conversion circuit and outputs a difference between an output signal from the charge-voltage conversion circuit and a zero voltage as a compensation signal. Circuit and a switching element for compensating signal energization, which is connected between the differential operation circuit and the charge-voltage conversion circuit and controls energization of the compensation signal output from the differential operation circuit, and the switching element. A sample-hold circuit including a capacitor that temporarily holds the output compensation signal, and the reset means includes a switching element for resetting the compensation signal that holds the compensation signal held in the sample-hold circuit. The signal processing circuit of the charge-generating type detection element according to claim 3. 5. The ON / OFF operation of the reset switching element, the compensation signal energizing switching element, and the compensation signal resetting switching element is prepared such that no charge is output from the sensing element to the charge-voltage conversion circuit. During the period, the first operation in which the reset switching element and the compensation signal reset switching element are simultaneously turned on, and the reset switching element is turned on.
In this state, the switching element for resetting the compensation signal is turned off and the switching element for energizing the compensation signal is turned on, and the switching element for energizing the compensation signal is reset to be on. 5. The signal processing circuit for the charge-generating type detection element according to claim 4, wherein the signal processing circuit is set so as to perform a third operation of turning off the switching element for use in the OFF state.