JPH0955394A - Semiconductor chip mounting method - Google Patents

Abstract

(57) [Abstract] [Purpose] To prevent the influence of the C (capacitance) component due to the dielectric constant of the sealing resin on the sensitive area by providing a slight air layer between the sensitive area and the sealing resin. Provided is a semiconductor chip mounting method capable of preventing malfunction of a high-speed semiconductor having a sensitive area and a low-voltage memory. [Structure] After a semiconductor chip 32 is base-bonded to a substrate 31, wire bonding is performed with a wire 33.
Next, a cube-shaped cover 35 having a slightly larger projected area than the sensitive area 34 is mounted on the sensitive area 34. In that state, the sealing resin 36
Coating. After the sealing resin 36 is hardened by heat, the cover 35 is pulled up by 1 to 2 mm to form an air layer in the sensitive area 34. After that, the adhesive 3 is formed so as to fill the gap between the sealing resin 36 and the cover 35.
The cover 35 is fixed at 7.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor chip mounting method.

[0002]

2. Description of the Related Art In recent years, in the field of communication, electronic devices have
High-speed technology typified by exchange technology and high-density technology typified by handheld terminals are becoming important. As a common technology embodying these technologies, bare chip mounting of semiconductors is the mainstream mounting technology. Has become.

Such semiconductor bare chip mounting technology includes wire bonding mounting, flip chip mounting, and T mounting.
AB (TAPE AUTOMATED BONDIN
G) There is mounting, etc., and they are used properly according to various purposes. FIG. 4 is a conventional wire bonding mounting diagram. As shown in this figure, the semiconductor chip 4 is a paste 2
Thus, it is fixed at a predetermined place on the substrate 1 made of glass epoxy, ceramics or the like. This semiconductor chip 4
The upper electrode 5 and the pad 3 on the substrate 1 are electrically connected by a wire 6 made of Au or the like and sealed with a sealing resin 8. Reference numeral 7 is a sensitive area of the semiconductor chip.

FIG. 5 is a conventional flip-chip mounting diagram. As shown in this figure, an electrode 14 is provided on the pattern surface of the semiconductor chip 13, and a pad 12 is formed on the substrate 11 made of glass epoxy, ceramics or the like. The pad 12 and the electrode 14 are connected by a solder bump 16 in order to obtain an electrical connection (including a mechanical connection and a heat conduction path in some cases).

Generally, the solder bumps 16 are melted in a reflow furnace, but after fusion connection, a gap between the semiconductor chip 13 and the substrate 11 is sealed with a sealing resin 17. Reference numeral 15 is a sensitive area of the semiconductor chip 13. The resin is sealed by the coefficient of thermal expansion of the semiconductor chip 13 (for example, Si: around 4 ppm) and the coefficient of thermal expansion of the substrate 11 (alumina ceramics: 8 ppm to glass epoxy:
It is widely known that the stress generated by the difference of about 15 ppm) is absorbed to improve the life of bump connection.

FIG. 6 is a conventional TAB mounting diagram. As shown in this figure, Au bumps 26 for electrical connection are formed on the electrodes 24 on the semiconductor chip 23 by a method using electroplating or a wire bonding apparatus.
The electrodes 24 on the semiconductor chip 23 and the pads 2 on the substrate 21
2 is electrically connected by a lead 27, which is a material obtained by subjecting Cu to Au plating or the like, via an Au bump 26, and is sealed with a sealing resin 28. Reference numeral 25 is a sensitive area of the semiconductor chip.

Generally, the mounting method described above is based on the SOP (SM
ALL OUTLINE PACKAGE), QFP
SMD (SURFACE MOUNT DEVICE) represented by (QUAD FLAT PACKAGE)
The wiring length is shorter, it is suitable for high speed, and the mounting area can be significantly reduced. Here, the sensitive area shown in FIGS. 4 to 6 will be described.

For example, in a high-speed semiconductor, rounding, delay, etc. occur in the signal waveform due to the influence of the capacitance (C) component generated between the patterns on the semiconductor chips 4, 13, 23,
It may cause malfunction. In addition, it is known that in a low voltage memory represented by an IC card or the like, a semiconductor forming a sense amplifier or the like is affected by a C (capacitance) component, which causes a theoretical judgment error. Sensitive area 7,1
Reference numerals 5 and 25 are portions of the semiconductor pattern that are easily affected by these capacitance components and the like, and the portions that need special consideration are areas.

[0009]

However, in the above-mentioned conventional semiconductor chip mounting method, the sealing resin 8, 1 is used.
Capacitance components generated by the dielectric constants (3.0 to 5.0) of 7, 28 are placed on the patterns of the semiconductor chips 4, 13, 23, and particularly, the sensitive areas 7, 1
There is a problem in that the operation of the high speed semiconductor having 5,25, the low voltage memory, etc. cannot be performed normally.

In order to solve the above problems, the present invention provides
By providing a slight air layer between the sensitive area and the sealing resin, it is possible to prevent the influence of the C (capacitance) component on the sensitive area due to the dielectric constant of the sealing resin, and to provide a high-speed semiconductor having the sensitive area. Another object of the present invention is to provide a semiconductor chip mounting method capable of preventing malfunction of a low-voltage memory or the like.

[0011]

In order to achieve the above object, the present invention provides a method of mounting a semiconductor chip, comprising: (1) a cubic shape having a projected area slightly larger than a sensitive area formed on the semiconductor chip. The cover is mounted on the sensitive area, the sealing resin is coated, the sealing resin is cured, and the cover is pulled up in the direction opposite to the sensitive area to fill the gap between the sealing resin and the cover. The cover is fixed with an adhesive.

As described above, a slight air layer is provided between the sensitive area and the sealing resin by merely pulling up the cover, whereby the C (capacitance) component due to the dielectric constant of the sealing resin received by the sensitive area is provided. It is possible to prevent the influence of the above, and thus to prevent the operation failure of the high speed semiconductor and the low voltage memory having the sensitive area.

(2) An opening is formed on the substrate at the center position of the sensitive area formed on the semiconductor chip and at the same center position on the projected coordinates, and the semiconductor chip is connected to the substrate via solder bumps. A sealing resin is filled so as to fill the gap between the semiconductor chip and the substrate while applying air pressure from the opening, and then a lid is attached to the opening of the substrate.

Therefore, a slight air layer can be provided between the sensitive area and the sealing resin in a simple and automated process, and C (capacitance) due to the dielectric constant of the sealing resin received by the sensitive area. The influence of the component can be prevented. (3) An opening is formed in the substrate at the same center position as the projected area and the center position of the sensitive area formed on the semiconductor chip, and the size is one size larger than the sensitive area on the substrate, and this sensitive area is formed. A dam is formed at the same center position on the projected coordinates as the center position of the area, the semiconductor chip is connected to the substrate through a solder bump, and air pressure is applied from the opening,
A sealing resin is filled so as to fill the gap between the semiconductor chip and the substrate, and the opening of the substrate is covered.

Therefore, in addition to the above (2), by forming a dam, the influence of the sealing resin on the sensitive area can be surely prevented.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view of a semiconductor chip mounting process showing a first embodiment of the present invention. (1) First, as shown in FIG. 1A, after the semiconductor chip 32 is base-bonded to the substrate 31, wire bonding is performed with the wire 33. Next, a cube-shaped cover 35 having a slightly larger projected area than the sensitive area 34 is mounted on the sensitive area 34.

(2) In that state, as shown in FIG. 1B, a sealing resin 36 (eg, epoxy) is coated. (3) After the sealing resin 36 is cured by heat, as shown in FIG.
As shown in (c), when the cover 35 is pulled upward by 1 to 2 mm, the sensitive area 34 becomes the sealing resin 36.
However, a slight air layer is formed.

(4) After that, as shown in FIG.
The cover 35 is fixed with an adhesive 37 so as to fill the gap between the sealing resin 36 and the cover 35. The cover will be described below. 2 and 3 are views showing the shape of the cover. FIGS. 2 (a) and 3 (a) are front views of the cover, and FIGS. 2 (b) and 3 (b) are bottom views of the cover. Is.

As shown in these figures, by forming a taper 35a on the side surface of the cover 35, it is possible to easily pull up the cover 35, and at the same time, on the side surface, a release agent (for example, silicone resin). If it is applied, a further effect can be expected. Further, the side surface of the sensitive area 34 needs to be flat so as not to wrap around when the sealing resin 36 is cured. Therefore,
Depending on the case, as shown in FIG. 3, a recess 35b may be formed at the tip of the cover 35.

Further, a highly elastic material (for example, a material such as silicone that can withstand the curing temperature of the sealing resin 36: about 150 ° C.) is applied to the material of the cover 35, and from the time of coating the sealing resin 36 to the completion of curing. It is advisable to apply a certain amount of load. Next, a second embodiment of the present invention will be described. FIG. 7 is a sectional view of a semiconductor chip mounting process showing a second embodiment of the present invention.

(1) First, as shown in FIG. 7A, a through hole 42 is formed at a predetermined position of a substrate 41, while
Solder bumps 4 are provided on the electrodes (not shown) of the semiconductor chip 43.
After forming 4 by electroplating or the like, the sensitive area 45 of the semiconductor chip 43 is positioned so as to correspond to the through hole 42 of the substrate 41, and a pad (not shown) on the substrate 41 is formed.
After applying flux onto the semiconductor chip 43, the semiconductor chip 43 is mounted on the substrate 41 and reflowed to connect the semiconductor chip 43 and the substrate 41. Therefore, the cover 46 is inserted from the back surface of the through hole 42 of the substrate 41.

(2) Next, as shown in FIG. 7B, in this state, a sealing resin 47 is filled so as to fill the gap between the semiconductor chip 43 and the substrate 41. (3) After that, as shown in FIG. 7C, when the cover 46 is pulled down by about 1 to 2 mm, the sensitive area 45 is not sealed with the sealing resin 47, and a slight air layer is formed. It is formed.

(4) Next, as shown in FIG. 7D, the adhesive 4 is formed so as to fill the gap between the sealing resin 47 and the cover 46.
The cover 46 is fixed at 9. Next, a third embodiment of the present invention will be described. FIG. 8 is a sectional view of a semiconductor chip mounting process showing the third embodiment of the present invention. (1) First, as shown in FIG.
Au bumps 52 are formed on the electrodes (not shown) on the substrate 1 for electrical connection with the substrate 57 [see FIG. 8 (d)] by electroplating or wire bonding.
After that, by applying heat, pressure, ultrasonic waves, etc., the lead 55 and the Au bump 52 are connected (ILB: INNER).
Lead Bonding) is performed, and the cover 54 is mounted on the sensitive area 53.

(2) Next, as shown in FIG. 8B, the cover 54 is coated with the sealing resin 56 while applying a slight load. (3) Next, as shown in FIG. 8C, the cover 5 is moved upward.
When 4 is pulled upward by about 1 to 2 mm, the sensitive area 53 is not sealed with the sealing resin 56,
Some air layer is formed.

(4) Next, as shown in FIG. 8D, the cover 54 is fixed with the adhesive 58 so as to fill the gap between the sealing resin 56 and the cover 54. Like the ILB, the lead 55 and the substrate 57 are connected while applying heat, pressure, and ultrasonic waves (OLB: OUTERLEAD BONDIN).
G). Next, a fourth embodiment of the present invention will be described.

FIG. 9 is a sectional view of a semiconductor chip mounting process showing the fourth embodiment of the present invention. (1) First, as shown in FIG.
4 is formed on an electrode (not shown) of the semiconductor chip 63 by electroplating or the like, flux is applied to a pad (not shown) on the substrate 61, the semiconductor chip 63 is mounted on the substrate 61, and then reflow is performed. , Semiconductor chip 63
And the substrate 61 are connected. An opening 62 is formed in the substrate 61 at the same center position as the center position of the sensitive area 65 in projection coordinates.

(2) Next, as shown in FIG. 9B, a sealing resin 66 is filled so as to fill the gap between the semiconductor chip 63 and the substrate 61 while applying air pressure from the opening 62. Let it harden. (3) Thereafter, as shown in FIG. 9C, the opening 62 of the substrate 61 is covered with a lid 67 with an adhesive or the like to complete the sealing. That is, the sensitive area 65 is the sealing resin 6
6 is not sealed, and a slight air layer is formed.

Next, a fifth embodiment of the present invention will be described. FIG. 10 is a sectional view of a semiconductor chip mounting process showing the fifth embodiment of the present invention. This embodiment is different from the fourth embodiment in that the dam on the substrate 71 is one size larger than the sensitive area 76 of the semiconductor chip 74 and is located at the same center position as the center position of the sensitive area 76 in projection coordinates. By forming 73, the sealing resin 77
It is possible to reliably prevent the expansion to the sensitive area 76. That is, (1) first, as shown in FIG. 10A, solder bumps 75 are formed on electrodes (not shown) of the semiconductor chip 74 by electroplating or the like, and then flux is applied to pads (not shown) on the substrate 71. After applying and mounting the semiconductor chip 74 on the substrate 71, the semiconductor chip 74 is reflowed.
And the substrate 71 are connected. The substrate 71-has an opening 72 formed at the same center position as the center position of the sensitive area 76 on the projected coordinates.

(2) Next, as shown in FIG.
While applying air pressure from the opening 72, the sealing resin 77 is filled so as to fill the gap between the semiconductor chip 74 and the substrate 71.
Fill and cure. (3) After that, as shown in FIG. 10C, the opening 72 of the substrate 71 is covered with an adhesive or the like to complete the sealing. That is, the sensitive area 76 is not sealed with the sealing resin 77, and a slight air layer is formed.

It should be noted that the present invention is not limited to the above embodiment, but various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

[0031]

As described in detail above, according to the present invention, the following effects can be achieved. (1) According to the invention as set forth in claim 1, a slight air layer is provided between the sensitive area and the sealing resin only by slightly pulling up the cover, which results from the dielectric constant of the sealing resin received by the sensitive area. It is possible to prevent the influence of the C (capacitance) component that occurs, and thus prevent the malfunction of the high-speed semiconductor having a sensitive area, the low-voltage memory, and the like.

(2) According to the second aspect of the invention, while the air pressure is applied from the opening formed in the substrate, the sealing resin is filled so as to fill the gap between the semiconductor chip and the substrate,
After that, since the lid is attached to the opening of the substrate, a slight air layer can be provided between the sensitive area and the sealing resin in a simple and automated process.
It is possible to prevent the influence of the C (capacitance) component due to the dielectric constant of the sealing resin on the sensitive area.

(3) According to the invention of claim 3, in addition to the effect of (2) above, by forming a dam, the influence of the sealing resin on the sensitive area can be reliably prevented. .

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip mounting process showing a first embodiment of the present invention.

FIG. 2 is a diagram showing a shape of a cover used for mounting a semiconductor chip showing the first embodiment of the present invention.

FIG. 3 is a diagram showing the shape of another cover used for mounting the semiconductor chip according to the first embodiment of the present invention.

FIG. 4 is a conventional wire bonding mounting diagram.

FIG. 5 is a conventional flip chip mounting diagram.

FIG. 6 is a conventional TAB mounting diagram.

FIG. 7 is a sectional view of a semiconductor chip mounting process showing a second embodiment of the present invention.

FIG. 8 is a sectional view of a semiconductor chip mounting process showing a third embodiment of the present invention.

FIG. 9 is a sectional view of a semiconductor chip mounting process showing the fourth embodiment of the present invention.

FIG. 10 is a sectional view of a semiconductor chip mounting process showing a fifth embodiment of the present invention.

[Explanation of symbols]

 31, 41, 57, 61, 71 Substrate 32, 43, 51, 63, 74 Semiconductor chip 33 Wire 34, 45, 53, 65, 76 Sensitive area 35, 46, 54 Cover 35a Taper 35b Recess 36, 47, 56, 66,77 Sealing resin 37,49,58 Adhesive 42 Through hole 44,64,75 Solder bump 52 Au bump 55 Lead 62,72 Opening 67,78 Lid 73 Dam

Claims (3)

[Claims] 1. A cube-shaped cover having a projected area slightly larger than a sensitive area formed on a semiconductor chip is mounted on the sensitive area.
(B) Encapsulating resin is coated to cure the encapsulating resin, (c) the cover is pulled up in the direction opposite to the sensitive area, and (d) adhesive is applied so as to fill the gap between the encapsulating resin and the cover. A method for mounting a semiconductor chip, characterized in that the cover is fixed with an agent. 2. An opening is formed in a substrate at a center position of a sensitive area formed on the semiconductor chip and the same center position as projected coordinates on the substrate, and a semiconductor chip is solder bumped on the substrate. And a sealing resin is filled so as to fill the gap between the semiconductor chip and the substrate while applying air pressure from the opening, and (c) after that, a lid is attached to the opening of the substrate. Semiconductor chip mounting method. 3. An opening is formed in a substrate at the same center position on projected coordinates as a center position of a sensitive area formed on a semiconductor chip, and (b) 1 opening from the sensitive area on the substrate. A dam having a large size and located at the same center position on the projected coordinates as the center position of the sensitive area is formed, and (c) the semiconductor chip is connected to the substrate via a solder bump, and air is introduced from the opening. A method of mounting a semiconductor chip, which comprises filling a sealing resin so as to fill a gap between the semiconductor chip and a substrate while applying pressure, and covering an opening of the substrate.