JPH0955659A - Semiconductor integrated circuit and recorded data reproducing device - Google Patents

Abstract

(57) [PROBLEMS] To automatically cancel an offset voltage input to an A / D converter without using an external calculation means.
Provided is a semiconductor integrated circuit capable of improving the accuracy of A / D conversion. An A / D converter 15 that converts an analog signal into a digital signal and outputs the analog signal, a pre-stage circuit 32 that outputs the analog signal to the A / D converter 15, and an analog signal input from the pre-stage circuit 32 are provided. When stopped, A / D converter 15
An offset voltage cancel circuit 16 for calculating a digital signal for canceling the offset voltage input from the pre-stage circuit 32 to the A / D converter 15 based on the output signal of
And a D / A that converts the digital output signal of the offset voltage cancel circuit 16 into an analog signal and outputs an analog voltage for reducing the offset voltage to the preceding circuit 32.
And a conversion unit 33.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a recorded data reproducing apparatus for reading data written on a recording medium such as a magnetic disk.

Data read from a hard disk such as a magnetic disk through a read head is read as an analog signal. The read data is converted into a digital signal by an A / D converter, the digital signal is subjected to various digital processes, and the recorded data is reproduced. In recent years, in order to speed up the reproduction operation of such recorded data, the recording density on a recording medium and the digital signal processing speed have been improved. Therefore, it is necessary to improve the accuracy of the A / D converter used in the recorded data reproducing device.

[0003]

2. Description of the Related Art In a recorded data reproducing apparatus, analog data read out from a recording medium such as a magnetic disk through a read head is amplified by an amplifier, and an output signal of the amplifier is A / D through an analog equalizer filter. It is output to the converter.

The A / D converter converts the input analog signal into a digital signal and outputs it to the digital processing circuit in the next stage. The digital processing circuit performs digital processing such as decoding processing on the input digital signal to reproduce recorded data.

In the A / D converter as described above, an offset voltage may occur in the input signal input through the analog equalizer filter. This offset voltage is generated due to an increase in ambient temperature, a change in power supply voltage, or a secular change in each circuit in the preceding stage of the magnetic disk or A / D converter.

If an offset voltage occurs in the input signal of the A / D converter, accurate A / D conversion becomes impossible. Therefore, a cancel circuit for canceling the offset voltage is connected to the input terminal of the A / D converter.

The cancel circuit cancels an offset voltage by adjusting an external component such as a resistor, or an output signal of an A / D converter is output to an external MPU.
, And based on the output signal of the A / D converter, M
The feedback control circuit is configured to convert the digital control signal calculated by PU into an analog value by a D / A converter and cancel the offset voltage with the analog value.

[0008]

However, since the cancel circuit using external parts cannot deal with the fluctuation of the offset voltage at any time, the accuracy of A / D conversion cannot be sufficiently improved.

Further, in the cancel circuit for calculating the digital control signal output to the D / A converter by the external MPU based on the output signal of the A / D converter, the data reading speed has been improved in recent years. When the output signal of the A / D converter is speeded up, the amount of calculation of the digital control signal in the MPU increases, which increases the load on the MPU and delays other processing operations. is there.

An object of the present invention is to provide a semiconductor integrated device capable of automatically eliminating an offset voltage input to an A / D converter without using an external arithmetic means and improving the accuracy of A / D conversion. To provide a circuit.

[0011]

FIG. 1 is a diagram illustrating the principle of the present invention. That is, the A / D converter 15 that converts an analog signal into a digital signal and outputs the analog signal, the pre-stage circuit 32 that outputs the analog signal to the A / D converter 15, and the input of the analog signal from the pre-stage circuit 32 are When stopped,
An offset voltage cancel circuit 16 for calculating a digital signal for canceling an offset voltage input from the pre-stage circuit 32 to the A / D converter 15 based on an output signal of the A / D converter 15; The digital output signal of the cancel circuit 16 is converted into an analog signal, and the D / A converter 33 which outputs an analog voltage for reducing the offset voltage to the pre-stage circuit 32 is provided.

(Operation) When the input of the analog signal to the A / D converter 15 is stopped, based on the output signal of the A / D converter 15, the pre-stage circuit 32 inputs the signal to the A / D converter 15. The offset voltage cancel circuit 16 calculates a digital signal for reducing the offset voltage. The output signal of the offset voltage cancel circuit 16 is D /
The A converter 33 converts the analog voltage into an analog voltage, and the pre-stage circuit 33
The offset voltage output from the pre-stage circuit 32 is eliminated.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 2 shows an outline of a recording data reproducing apparatus for reading data written on a magnetic disk.

The read head 1 provided in the magnetic disk drive reads the data written on the magnetic disk and outputs it to the amplifier 2. The amplifier 2 is
The analog data read from the read head 1 is amplified and output to the gain control amplifier 4 in the read channel IC 3.

The gain control amplifier 4 has its gain controlled based on a gain correction signal gc input from the outside, and outputs an output signal of a predetermined level to an analog equalizer filter 5 based on the signal input from the amplifier 2. Output.

The analog equalizer filter 5 adjusts the frequency characteristic of the output signal of the gain control amplifier 4 to a predetermined level and outputs it to the A / D converter 6. The A / D converter 6 converts the analog signal output from the analog equalizer filter 5 into a digital signal and outputs the digital signal to the digital filter 7.

The digital filter 7 removes unnecessary digital components from the digital signal output from the A / D converter 6, and outputs the digital signal to the maximum likelihood decoding circuit 8. Then, the maximum likelihood decoding circuit 8 performs a decoding operation based on the maximum likelihood decoding method, and decodes the decoded read data into the serial-parallel converter 10.
Output to

The serial-parallel converter 10 converts the serial data output from the maximum likelihood decoding circuit 8 into parallel data and outputs the parallel data to the outside of the read channel IC 3.

The output signal of the digital filter 7 is P
The PLL synthesizer circuit 9 is signaled to the LL synthesizer circuit 9, and the PLL synthesizer circuit 9 outputs the signal A based on the output signal of the digital filter 7.
The sampling frequency of the / D converter 6 is generated and output.

The output signal of the gain control amplifier 4 is input to the servo control unit 11. The servo control unit 11
Based on the input signal, the read head recognizes which sector on the magnetic disk is being read, and outputs a control signal CL to a read head driving device (not shown).

Further, as shown in FIG. 4, the servo control section 11 recognizes whether the read head 1 is reading the servo area or the data area in each sector, and reads the servo area, for example. The control signal XSG which sometimes becomes H level is output to the A / D conversion unit 6.

A concrete structure of the A / D converter 6 is shown in FIG. From the analog equalizer filter 5, this A /
The analog input signal Ain input to the D conversion unit 6 is input to the amplifier 14 via the switch circuit 12 and the coupling capacitor 13.

A control signal OFS, which will be described later, is input to the switch circuit 12. For example, when the control signal OFS becomes H level, the switch circuit 12 is turned on and the analog input signal Ain is output to the coupling capacitor 13. It

The input terminal of the amplifier 14 has resistors R1,
It is connected to the ground GND via R2. The amplifier 14 amplifies the analog input signal Ain input via the coupling capacitor 13 and outputs it to the A / D converter 15.

The A / D converter 15 converts the input analog signal into 6-bit binary complement signals OAD0 to OAD5.
And is output to the digital filter 7. That is, if the analog signal input to the A / D converter 15 matches the center voltage, the output signals OAD0 to OAD4 of the A / D converter 15 become "00000", and if the LSB is higher than the center voltage by 1 LSB. , "00001".

Further, if it is lower by 1 LSB than the center voltage, it is "11111", and if it is lower by 2 LSB,
It becomes “11110”. Highest digital signal OAD5
Indicates whether the input voltage of the A / D converter 15 is higher or lower than the center voltage, and is “0” if it is higher than the center voltage and “1” if it is lower than the center voltage.

The digital signals OAD0 to OAD5 are
It is also input to the offset voltage cancel circuit 16. The offset voltage cancel circuit 16 uses the A / D converter 15 based on the digital signals OAD0 to OAD5.
The 8-bit digital signal for canceling the offset voltage of is output to the D / A converter 17.

The D / A converter 17 converts the input digital signal into an analog voltage and outputs the analog voltage between the resistors R1 and R2 via the resistor R3. Therefore, the input voltage of the amplifier 14 is changed and the input voltage of the A / D converter 15 is adjusted based on the change of the analog voltage output from the D / A converter 17.

A specific structure of the offset voltage cancel circuit 16 is shown in FIG. The binary complement signals OAD0 to OAD5 output from the A / D converter 15 are input to the comparator 18. Highest digital signal OAD5
Is also input to the control circuit 19. Then, the control circuit 19
If the digital signal OAD5 is "0", it is determined that the input voltage is higher than the center voltage, and if it is "1", the input voltage is determined to be lower than the center voltage.

A concrete configuration of the comparator 18 is shown in FIG.
Shown in The digital signals OAD1 to OAD4 are NO
It is input to the R circuit 25a and the NAND circuit 26a. The digital signals OAD0 and OAD5 are transferred to the NAND circuit 2
6b, and the digital signal OAD0 is input to the NAND circuit 26c via the inverter circuit.

The output signal of the NOR circuit 25a is N
It is inputted to the AND circuit 26c and the AND circuit 26d.
The output signal of the NAND circuit 26b is input to the AND circuit 26d and the NOR circuit 25b.

The output signal of the NAND circuit 26a is input to the NOR circuit 25b, and the output signal of the dynamic NOR circuit 25b is input to the NOR circuit 25c. The output signal of the AND circuit 26d is the NOR circuit 25.
Input to c.

The output signal C is output from the NAND circuit.
M0 is output, and the output signal C is output from the NOR circuit 25c.
M1 is output. In the comparator configured in this way, all the digital signals OAD0 to OAD4 are "0".
If so, the output signals CM0 and CM1 are both "0". When the digital signal OAD0 is "1", the OAD1
When OAD4 becomes "0", the output signal CM0 becomes "1" and CM1 becomes "0". In addition, the digital signal O
When at least one of AD1 to OAD4 becomes "1", both output signals CM0 and CM1 become "1".

The output signals CM0 and CM1 are input to the control circuit 19. The control circuit 19 outputs the output signal CM
If both 0 and CM1 are “0”, the A / D converter 15
Judge that the analog input voltage of
The control signal LBD is set to L level.

When the output signal CM0 of the comparator becomes "1" and CM1 becomes "0", the control circuit 19 causes A
It is determined that the difference between the analog input voltage of the / D converter 15 and the central voltage is a small value of 2 LSB or less of the A / D converter 15, and the L level output signal LBC is output.

Further, output signals CM0, C of the comparator
When both M1 are "1", the control circuit 19 causes the A / D
It is determined that the difference between the analog input voltage of the converter 15 and the center voltage is a large value of 2 LSB or more of the same A / D converter 15, and the H level output signal LBC is output.

A control signal O input to the control circuit 19
The FT is input from the outside, and the cycle of the offset clock signal OFCLK output from the control circuit 19 is set based on the control signal OFT.

The correction amount setting register 21 is provided in the A / D
1 of the digital output signals OAD0 to OAD4 of the converter 15
It is a register for setting an 8-bit binary code value of the D / A converter 17 corresponding to a change in LSB.

Then, a write control signal WRITE is sent from the external MPU via the serial interface 20,
When the address signal ADR is input, externally input data is written to the address selected by the address signal ADR via the data bus DBUS. The data stored in the correction amount setting register 21 is reset by a reset signal XRESET input from the outside.

The 8-bit stored data I0 to I7 of the correction amount setting register 21 is output to the LSB selection circuit 22. The LSB selection circuit 22 includes the control circuit 1
Control signals LBC and LBD are input from 9 and, based on the control signal LBC, the coarse movement mode in which the input data I0 to I7 are output as they are or the input data I0 to I7 are shifted to the lower side by 2 bits and output. Select the fine movement mode or set all the input data I0 to I7 to "0".

A concrete structure of the LSB selection circuit 22 is shown in FIG. The input data I7 and I6 are input to the AND circuit 27, respectively, and the input data I5 to I0 are input to the input terminal A of the selector 28, respectively.

The input data I7 to I2 are each 2
Bitwise lower input data I5 to I0 are input to the input terminal B of the selector 28. The control signal LBC output from the control circuit 19 is input to the input terminals SL of the AND circuit 27 and the selectors 28. When the control signal LBC input to the input terminal SL becomes H level, the selector outputs the signal input to the input terminal A, and when the control signal LBC becomes L level,
The signal input to the input terminal B is output.

The output signals of the AND circuit 27 and the selector 28 are output to the AND circuit 29, respectively. Further, the control signal LBD output from the control circuit 19 is input to the AND circuit 29, respectively. Then, each AND circuit 29 outputs an 8-bit output signal OT7-
OT0 is output.

The LSB selection circuit 22 thus configured
When the control signals LBC and LBD become the H level, the input data I7 to I0 remain the 8-bit output signal OT7.
It is output as ~ OT0.

When the control signal LBC is maintained at the H level and the control signal LBC is at the L level, the input data I7 to I2 are respectively shifted by 2 bits to the lower side and output as the output signals OT5 to OT0. Then, the output signals OT7 to OT6 become "0".

Therefore, the output signals OT7 to OT0 are digital values of 1/4 of the input data I7 to I0, and the D / A converter 1 corresponding to 1/4 LSB of the A / D converter 15 is provided.
It becomes a binary code value of 7.

When the control signal LBD becomes L level, all the output signals OT0 to OT7 become "0". The output signals OT0 to OT7 of the LSB selection circuit 22 are input to the addition / subtraction circuit 23. In addition, the addition / subtraction circuit 23
Is an 8-bit output signal OF of the output register 24 described later.
C0-OFC7 and the control signal PMD output from the control circuit 19 are input. The control signal PMD becomes L level when the output signal OAD5 of the most significant bit of the A / D converter is "0", and becomes H level when it is "1".

Then, the adder / subtractor circuit 23 controls the control signal PMD.
The input signals OFC0 to OFC7 and the input signals OT0 to OT7 are added or subtracted based on the above. A concrete configuration of the adder / subtractor circuit 23 is shown in FIG. The input signals OFC0 to OFC7 are input to the adder 30, respectively, and the input signals OT0 to OT7 are input to one input terminals of the EOR circuit 31, respectively.

The control signal PMD is input to the other input terminal of the EOR circuit 31. And each EO
The output signals of the R circuit 31 are input to the adder 30, and the output signals S0 to S7 are output from the adder 30.

In the adder / subtractor circuit 33 thus constructed, when the control signal PMD goes high, each EOR circuit 31 outputs a signal in phase with the input signals OT0 to OT7. Then, each adder 30 receives the input signals OFC0 to OF.
Input signals OT0 to OT7 are added to C7 and output as output signals S0 to S7.

On the other hand, when the control signal PMD becomes L level, each EOR circuit 31 outputs a signal obtained by inverting the input signals OT0 to OT7. Then, the adding operation of each adder 30 is substantially an operation of subtracting the same OT0 to OT7 from the input signals OFC0 to OFC7, and outputs the subtraction result as the output signals S0 to S7.

Output signals S0 to S7 of the adder / subtractor circuit 33.
Are input to the output register 24. The offset clock signal OFCLK is input from the control circuit 19 to the output register 24, and the output register 24 updates the stored data to the output signals S0 to S7 of the adder / subtractor circuit 33 at each rising edge of the offset clock signal OFCLK. , Output signals OFC0 to OFC7 to the D / A converter 17.

Data is written to the output register 24 or data stored in the output register 24 is read based on a signal input from the external MPU via the serial interface 20.

That is, the write signal W from the external MPU
When RITE and the address signal ADR are input, the write data is written to the selected address via the data bus DBUS. When the read signal READ and the address signal ADR are input from the external MPU, the storage data of the selected address is read out via the data bus DBUS.

A control signal XSG is input to the control circuit 19 from the servo control section 11. The control circuit 19 then controls the control signal OFS based on the control signal XSG.
Is output to the switch circuit 12.

Control signal A input to the control circuit 19
TCN is input from the outside. The control circuit 19 receives the control signal ATCN and inputs the control signal XSG.
Irrespective of the above, the control signal OFS is output to start the operation of the offset cancel circuit 16.

The control signal WNS input to the control circuit 19 from the outside controls the control signals LBC and LBD output to the LSB selection circuit 22 from the outside to output the output signals OT0 to OT7 of the LSB selection circuit 22 roughly. It is input as a signal for selecting the moving mode or the fine moving mode.

The control signal STB externally input to the control circuit 19 is input as a signal for activating the control circuit 19. The reference clock signal REFCLK input from the outside to the control circuit 19 is input as a reference signal for generating the offset clock signal OFCLK.

Next, the offset voltage canceling operation in the A / D converter 6 in the recording data reproducing apparatus having the above-mentioned structure will be described. When the reading head 1 starts the reading operation of the servo area, the servo controller 11
The control signal XSG is input to the A / D converter 6. The control signal XSG is the offset voltage cancel circuit 16
When input to the control circuit 19 therein, the control signal OFS is input from the control circuit 19 to the switch circuit 12, and the switch circuit 12 is turned off.

In this state, the offset voltage cancel circuit 16 operates so that the input voltage of the A / D converter 15 becomes the center voltage. At this time, if the input voltage of the A / D converter 15 is offset by 2 LSB or more higher than the center voltage, the highest-order digital signal OAD5 output from the A / D converter 15 is "0", Signal OAD
At least one of 1 to OAD4 becomes "1", and the output signals CM0 and CM1 of the comparator 18 become "1".

Then, the control signals LBC and LBD output from the control circuit 19 both become H level, and the control signal PMD becomes L level. H level control signal LBC,
Based on the LBD, the LSB selection circuit 22 receives the input signal I0
.About.I7 are output as output signals OT0 to OT7, and the output signals OT0 to OT7 are in the coarse movement mode.

Further, by the L level control signal PMD,
The addition / subtraction circuit 23 is in the subtraction mode, and the output register 24
Input signals OT0 to OT7 in the coarse motion mode are subtracted from the output signals OFC0 to OFC7 and output to the output register 24 as output signals S0 to S7.

The output register 24 stores the output signals S0 to S7 of the adder / subtractor circuit 23 at every rise of the offset clock signal OFCLK, and outputs the output signals OFC0 to OFC.
It is output to the D / A converter 17 as C7.

Since the D / A converter 17 converts the subtracted input signals S0 to S7 into analog voltages, its output voltage decreases. Then, the input voltage of the amplifier 14 set based on the resistors R1 to R3 decreases, and the analog input voltage of the A / D converter 15 has a smaller offset value and approaches the center voltage.

When the offset value of the analog input voltage of the A / D converter 15 becomes small and only OAD0 of the digital output signals OAD5 to OAD0 of the A / D converter 15 becomes "1", the output signal of the comparator 18 is outputted. CM0
Is "1" and CM1 is "0".

Then, the control signal LBC becomes L level, and the LSB selection circuit 22 shifts the input signals I0 to I7 downward by 2 bits and outputs the output signals OT0 to OT7, and the output signals OT0 to OT7 are changed. The fine movement mode is set.

The control signal PMD is maintained at the L level, the addition / subtraction circuit 23 is maintained in the subtraction mode, the input signals OT0 to OT7 in the fine movement mode are subtracted from the output signals OFC0 to OFC7 of the output register 24, and the output signals are output. S0 ~
It is output to the output register 24 as S7.

Then, in the same manner as described above, the output register 24 stores and outputs the output signals S0 to S7 of the adder / subtractor circuit 23 at each rising edge of the offset clock signal OFCLK, and the D / A converter 17 is in the fine movement mode. Since the output signals OFC0 to OFC7 that have been subtracted by a small amount are converted into analog voltages, the output voltage decreases by a small amount. Then, the input voltage of the amplifier 14 drops slightly, and the analog input voltage of the A / D converter 15 further approaches the center voltage.

By the above operation, the A / D converter 1
When the analog input voltage of 5 becomes the central voltage, all the digital output signals OAD0 to OAD5 of the A / D converter 15 become "0".

Then, the output signal CM of the comparator 18
0 and CM1 become "0", and the control signal LBD becomes "0". Then, the output signals OT0 ...
Since all OT7 are "0", the output signals S0 to S7 of the adder / subtractor circuit 23 and the output signal OF of the output register 24 are OF.
C0-OFC7 is constant.

Therefore, the output voltage of the D / A converter 17 becomes constant, and the analog input voltage of the A / D converter 15 is maintained at the center voltage. Further, when the input voltage of the A / D converter 15 is offset lower than the center voltage, the digital output signal OAD5 becomes "1" and the control signal PMD becomes H level.
Level.

Then, the A / D converter 1 operates in the same manner as described above except that the addition / subtraction circuit 23 is in the addition mode.
The offset of the analog input voltage of 5 is eliminated. In this state, when the reading head 1 finishes reading the servo area and starts reading the data area, the output of the control signal XSG from the servo control unit 11 is stopped,
The output of the control signal OFS is stopped and the control signal LBD becomes L level.

Then, the output signal O of the LSB selection circuit 22
All of T0 to OT7 are maintained at "0", and the output voltage of the D / A converter 17 is maintained constant as in the above. Then, the switch circuit 12 becomes conductive, the analog input signal Ain read from the data area is input through the switch circuit 12, and the A / D converter 15 outputs A / D in a state where the offset voltage is eliminated. The D conversion operation is performed.

When the reading operation of the data area is completed and the reading operation of the servo area is started again, the above-described offset voltage canceling operation is restarted. As described above, in the A / D converter 6, the reading head 1
When the reading operation of the servo area is started by the switch circuit 12, the switch circuit 12 is turned off, the input of the analog input signal Ain is stopped, and the amplifier 14, the A / D converter 15, the offset voltage cancel circuit 16, and the D / A conversion are performed. The device 17 and the resistors R1 to R3 form a closed loop.

Then, the offset voltage cancel circuit 1
By the operation of 6, the offset voltage of the A / D converter 15 can be automatically canceled. The offset voltage cancel circuit 16 is activated based on the control signal XSG input along with the read operation of the servo area,
The magnitude of the offset value is detected by the comparator 18.

Then, the LSB selection circuit 22 selects either the coarse movement mode or the fine movement mode. In the coarse movement mode, the offset voltage canceling operation performed at each rising edge of the offset clock signal OFCLK is A / D.
It is performed for 1 LSB of the converter 15, and in the fine movement mode,
This is performed for each 1/4 LSB of the A / D converter 15.

With such an operation, the A / D converter 15
When the offset voltage is large, the offset voltage can be quickly reduced, and when the offset voltage is reduced, the offset voltage is further reduced to “0”.
Can be finely adjusted to approach.

Therefore, the offset voltage canceling operation can be performed at high speed and with high accuracy. As a result,
The conversion accuracy of the A / D converter 15 can be improved. Further, the output signals OFC0 to OF of the output register 24
Offset clock signal OF for setting the update cycle of C7
CLK can be arbitrarily set based on the control signal OFT input from the outside.

By appropriately selecting the update period, the output signal OF of the output register 24 in accordance with the change of the output signals S0 to S7 of the adder / subtractor circuit 23.
The output voltage of the D / A converter 17 can be stabilized by preventing unnecessary fluctuations of C0-OFC7.

[0080]

As described in detail above, the present invention is
It is possible to provide a semiconductor integrated circuit capable of automatically eliminating the offset voltage input to the D converter without using an external arithmetic means and improving the accuracy of A / D conversion.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a recorded data reproducing device.

FIG. 3 is a circuit diagram showing an A / D conversion unit.

FIG. 4 is a conceptual diagram showing a reading operation of a servo area.

FIG. 5 is a block diagram showing an offset cancel circuit.

FIG. 6 is a circuit diagram showing a comparator.

FIG. 7 is a circuit diagram showing an LSB selection circuit.

FIG. 8 is a circuit diagram showing an adder / subtractor circuit.

[Explanation of symbols]

 15 A / D converter 16 Offset voltage cancel circuit 32 Pre-stage circuit 33 D / A converter

Claims (5)

[Claims] 1. An A / D converter that converts an analog signal into a digital signal and outputs the digital signal, a pre-stage circuit that outputs the analog signal to the A / D converter, and an input of the analog signal from the pre-stage circuit is stopped. Then, based on the output signal of the A / D converter, an offset voltage cancel circuit that calculates a digital signal that reduces the offset voltage input from the preceding circuit to the A / D converter, and the offset voltage cancel circuit. D / A for converting a digital output signal of the circuit into an analog signal and outputting an analog voltage for canceling the offset voltage to the preceding circuit
A semiconductor integrated circuit including a converter. 2. The offset voltage cancel circuit comprises:
A detection unit that detects an offset voltage based on the output signal of the A / D converter, a calculation unit that calculates a digital signal that reduces the offset voltage, and a calculation unit based on the output signal of the detection unit. A control circuit for controlling the operation, and an output signal of the arithmetic unit are stored based on an offset clock signal output from the control circuit, and the D /
2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit comprises an output register for outputting to the A conversion unit. 3. The offset voltage cancel circuit comprises:
A comparator that detects the presence or absence and the magnitude of an offset voltage based on the output signal of the A / D converter; a control circuit that outputs a plurality of control signals based on the output signal of the comparator; An LSB selection circuit that selects a unit change amount of the analog output voltage of the D / A conversion unit and outputs a digital signal, and an output signal of the LSB selection circuit and an output signal of the output register based on the control signal. And an addition / subtraction circuit for performing addition and subtraction with respect to the output register, and an output signal of the addition / subtraction circuit is stored based on an offset clock signal output from the control circuit and output to the D / A conversion unit. 2. The semiconductor integrated circuit according to claim 1, wherein the semiconductor integrated circuit is configured by an output register. 4. The coarse mode in which the LSB selection circuit outputs a binary code value of the D / A converter corresponding to 1 LSB of the A / D converter based on the control signal,
The D / A corresponding to 1/4 LSB of the A / D converter
4. The semiconductor integrated circuit according to claim 3, wherein any one of the fine motion mode for outputting the binary code value of the converter is selected and output. 5. A data reading device for reading data stored in a recording medium composed of a large number of sectors composed of a servo area and a data area as an analog signal, and an A / A for converting the analog signal into a digital signal. A recording data reproducing device comprising a D converting unit and a digital signal processing unit for digitally processing an output signal of the A / D converting unit, wherein the A / D converting unit reads the servo area by the reading device. A switch circuit that stops input of an analog signal based on a control signal output from the reading device during operation, and an A / D that converts the analog signal into a digital signal and outputs the digital signal
A converter, a pre-stage circuit that outputs an analog signal input from the reading device via the switch circuit to the A / D converter, and the A / D converter when the input of the analog signal from the pre-stage circuit is stopped An offset voltage cancel circuit that calculates a digital signal that reduces the offset voltage input from the preceding circuit to the A / D converter based on the output signal of the D converter, and a digital output signal of the offset voltage cancel circuit. D / A for converting into an analog signal and outputting an analog voltage for reducing the offset voltage to the preceding circuit
A recorded data reproducing apparatus comprising: a converter.