JPH0956155A - Fet rectifier circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the increase in a loss of a circuit even with the expansion of a range of the input voltage or with the change in current in a load. SOLUTION: With the input of the rectified and smoothed voltage of a winding 9 of a smoothing coil 8 as a line voltage and the voltage of an auxiliary winding 5 of a transformer 1 as a control voltage, a first control circuit 14 clamps the reverse voltage of the control voltage and inputs it into a complementary-connected transistor and then outputs a first control signal. On the first control signal, an FET for rectification becomes on when a transistor 2 is on and then conducts rectification. On the other hand, a second control circuit 15 receives the rectified and smoothed voltage of a winding 7 of the smoothing coil 8 as a line voltage and the voltage of a winding 6 of the smoothing coil 8 as a control voltage and then outputs a second control signal. On the second control signal, an FET for rectification 11 becomes on when the transistor 2 is on and then conducts commutation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an FET rectifier circuit, and more particularly to an FET rectifier circuit for a switching regulator which uses an insulated gate field effect transistor (hereinafter referred to as FET) for a rectifying element and a commutating element.

[0002]

2. Description of the Related Art Conventionally, this kind of FET rectifier circuit has been used for a switching regulator which is a small, lightweight and highly efficient power source used in a communication device or the like which often uses a DC power source. It is used as a rectifier circuit that switches the input voltage applied to the primary side of the installed transformer and rectifies and commutates in synchronization with this switching.

FIG. 8 is a circuit diagram showing an example of a conventional FET rectifier circuit.

Referring to FIG. 8, a primary winding 51a and a switching transistor 50 connected in series to the primary winding 51a are provided on the primary side of the transformer 51, and a secondary side of the transformer 51 is provided with a secondary winding 51a. Secondary winding 51b and auxiliary windings 51c, 5
1d is provided, the gate of the FET 53 for rectification is connected in series to the one end of the auxiliary winding 51c via the resistor 52, and the one end of the auxiliary winding 51d is connected in series via the resistor 54 for commutation. The gate of the FET 55 is connected. Auxiliary winding 5
The source of FET 53 is connected to the other end of 1c
A connection terminal 57a for a load 57 is connected to the drain of the capacitor 3 via an inductance 56. In addition, FET
A parasitic diode 58 is connected in parallel between the source and drain of 53. At the other end of the auxiliary winding 51d, F
The source of the ET 55 is connected, and the drain of the FET 55 is connected to the connection terminal 57 a for the load 57 via the inductance 56. A parasitic diode 59 is connected in parallel between the source and drain of the FET 55. The source side of the FET 55 is further connected to the connection terminal 57b for the load 57, and the connection terminal 57a and the connection terminal 5 are connected.
A smoothing capacitor 60 is connected in parallel with 7b. The waveform of each part in such a circuit is shown in FIG.
It becomes as shown in. Here, when the drive waveform shown in (a) is output, the rectifying FET 53 has a waveform between the gate and the source as shown in (b), and between the source and the drain (c). The waveform is as shown in. In the commutation FET 55, the waveform shown in (d) is obtained between the gate and the source, and the waveform shown in (e) is obtained between the source and the drain.

Therefore, as shown in FIG. 12A, the above-mentioned conventional FET rectifier circuit is shown in FIG. 12B and FIG. 1 in each period A, B and C of one pattern of the drive waveform.
2 (c) and functions as a circuit configured as shown in FIG. 12 (d). Further, this FET rectifier circuit turns on the rectifying FET 53 by the positive electromotive force generated in the secondary auxiliary winding 51c, and turns the commutation FET 55 by the counter electromotive force generated in the auxiliary winding 51d. Since it is controlled to turn on, no electromotive force is generated in the auxiliary windings 51c and 51d during the zero period (B period when the transistor is off in FIG. 12A) when the switching of the transistor 50 is off. Since the diode 58 or 59 parasitic on the FETs 53 and 55 functions as a rectifying element, there is a problem that the voltage drop during rectification or commutation is large, driving loss is large, and circuit efficiency is poor.

Another conventional F disclosed in Japanese Patent Laid-Open No. 5-199744 is intended to solve this problem.
There is an ET rectifier circuit.

Referring to FIG. 9 which is a circuit diagram showing another conventional FET rectifier circuit, this FET rectifier circuit is obtained by adding FETs, diodes, capacitors, resistors and the like to the conventional FET rectifier circuit shown in FIG. ing. That is,
A diode 61 and a resistor 67 are connected in series between one end of the auxiliary winding 51c and the resistor 52, one end of a capacitor 71 is connected to the contact point between the resistor 67 and the resistor 52, and the other end of the capacitor 71 is connected. Is connected to the other end of the auxiliary winding 51c. The rectifying FET 53 is driven by an FET 63 in which the source is connected to one end of the secondary winding 51b, the gate is connected to the other end via a resistor 69, and the drain is connected to the gate of the FET 53 via a resistor 70. A diode 62 is provided between one end of the winding 51d and the resistor 54.
Connect. The FET 55 for commutation has a source connected to one end of the secondary winding 51b, a gate connected to the other end through a resistor 68, and a drain connected to the gate of the FET 55.
Driven by ET64. The waveform of each part in such a circuit is as shown in FIG. Here, (a)
When the drive waveform shown in is output, FET5 for rectification
In No. 3, the waveform between the gate and the source is as shown in (b), and the waveform between the source and the drain is as shown in (c). In the commutation FET 55, the waveform shown in (d) is obtained between the gate and the source, and the waveform shown in (e) is obtained between the source and the drain.

Therefore, in the other conventional FET rectifying circuit described above, the rectifying FET 53 is the auxiliary winding 51.
The positive state of the secondary winding 51 is maintained by the voltage smoothed and charged in the capacitor 71 by the positive electromotive force generated in c.
The FET 63 is controlled to be turned off by the conduction of the FET 63 controlled by the voltage generated at b. Further, the commutation FET 55 holds the ON state by a voltage obtained by smoothing the counter electromotive force generated in the auxiliary winding 51d, and holds the secondary winding 5
The conduction of the FET 64 controlled by the voltage generated in 1b controls the switching from ON to OFF.

[0009]

The above-mentioned other conventional F
In the ET rectifier circuit, since the FET 55 is turned on even during the zero period shown in the period B of FIG. 12A, the voltage drop during commutation is not large and the drive loss is not deteriorated. However, when the input voltage has a wide range of DC38.4V to 57.6V such as DC48V ± 20%, the voltage of the positive electromotive force of the auxiliary windings 51c and 51d changes greatly. Therefore Pc = C ・ V ・ V ・ F (C: F
FET63 represented by ET gate capacitance, V: FET gate-source voltage, F: switching frequency),
The drive loss of the transistor 64 increases, and the breakdown voltage between the gate and the source of these FETs may be exceeded and the FETs may be destroyed. Further, due to the conduction of the FET 63, the rectifying FE
When controlling T53 from on to off, the FET6
3, the capacitor 71 is short-circuited, which causes a problem that the drive loss of the circuit increases.

Further, the FET 64 is connected to the secondary winding 5
Back electromotive force V (V = K ・ L1 ・ I2 ・ C1 ・
C2, where L1: inductance of the primary winding of the transformer, I2: output current flowing in the secondary winding 1b, C1: capacitance of the primary side of the transformer, C2: capacitance of the secondary side of the transformer, K: The commutation FET 55 is switched from ON to OFF by being turned on (short-circuited) by a proportional constant), but the waveform of the counter electromotive force V is changed by the influence of I2 when the current flowing through the load 57 is changed. Therefore, as shown in FIG. 7, the timing when the FET 55 is turned on is turned off by delaying the time when the rectangular waveform is distorted and becomes a flyback waveform, which is a voltage equal to or higher than a threshold value for turning on the FET 64 from off to t. However, there is also a problem that the drive loss of the circuit increases because of the delay of t time.

The object of the present invention is to eliminate the above-mentioned conventional drawbacks. Therefore, even if the input voltage range is wide and the current flowing through the load changes, the drive loss of the circuit does not occur.
It is to provide an ET rectifier circuit.

[0012]

A FET rectifier circuit according to the present invention includes a transformer having a primary winding on a primary side and a secondary winding and an auxiliary winding on a secondary side, and one of the transformers. A switching element that switches the input voltage applied to the next side,
A rectifying element that is installed on the secondary side of the transformer and uses an insulated gate field effect transistor that is turned on by the positive electromotive force of the transformer; and a first output terminal that outputs the rectifying element and an output voltage. A commutation element using a smoothing coil connected therebetween and an insulated gate field effect transistor which is installed on the secondary side of the transformer and is turned on by a counter electromotive force generated in the smoothing coil when the switching element is off. A first power supply circuit for rectifying and smoothing the voltage across both ends of a first winding wound in parallel with the smoothing coil, and outputting the output voltage of the first power supply circuit as a power supply voltage. A first control circuit which inputs a voltage across the auxiliary winding wound on the secondary side as a control voltage and outputs a first control signal for controlling the rectifying element; A second power supply circuit for rectifying and smoothing the voltage across both ends of a second winding additionally wound in parallel with the smoothing coil, and an output voltage of the second power supply circuit as a power supply voltage A second control circuit for outputting a second control signal for controlling the commutation element by using the voltage across the third winding additionally wound in parallel as the control voltage, and the output voltage. And a smoothing capacitor connected between the first output terminal and the second output terminal for outputting and smoothing the output voltage.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the FET rectifier circuit of the present invention.

The FET rectifier circuit of this embodiment shown in FIG. 1 has a transformer 1 having a primary winding 3 on the primary side and a secondary winding 4 and an auxiliary winding 5 on the secondary side, A transistor 2 which is a switching element that is connected in series with the primary winding 3 and switches the input voltage applied to the transformer 1.
And a FET 10 which is a rectifying element that rectifies the voltage generated on the secondary side of the transformer 1 and has a parasitic diode 12.
And the first winding 9 and the second winding 7 connected between the drain of the FET 10 and the first output terminal 19a on the load side.
And a smoothing coil 8 having a third winding 6, a first power supply circuit 13 for inputting a voltage across the first winding 9, rectifying and smoothing the voltage, and outputting the voltage. And a second control side of the transformer 1 which outputs a first control signal for controlling the FET 10 by inputting a voltage across the auxiliary winding 5 as a control voltage and a voltage across the auxiliary winding 5 as a control voltage. FET 11 which is a commutation element having a parasitic diode 13 and a voltage across both ends of the second winding 7, and a second power supply circuit 17 for rectifying and smoothing the voltage and outputting the voltage. A second control circuit 15 which outputs the second control signal for controlling the FET 11 by inputting the output voltage as a power supply voltage and the voltage across the third winding 6 as a control voltage; The first output terminal 19a and It is constituted by the connected output voltage between the second output terminal 19b and a capacitor 18 for smoothing.

Next, the operation of the FET rectifier circuit of this embodiment will be described in detail with reference to FIGS. 2, 3, 4, 5, and 6.

FIG. 2 is a circuit diagram showing the nth control circuit (n is 1 or 2), which is a PNP transistor 141.
And NPN type transistor 142 are connected in a complementary manner, the collector of the transistor 142 is the terminal dn, the collector of the transistor 141 is the terminal bn and the terminal en.
And the bases of the transistors 141 and 142 are connected to the terminal an via the resistor 143. In order to clamp the reverse voltage applied between the base and collector of the transistor 141, the cathode of the diode 144 is connected to the base of the transistor 141, and the cathode of the Zener diode 145 is connected to the collector of the transistor 141. The anode of 144 and the anode of the Zener diode 145 are connected. This control circuit inputs the power supply voltage of the circuit between the terminals en and dn,
An nth control voltage for controlling the rectification or commutation FET from the terminal cn connected to the emitters of the transistor 141 and the transistor 142 by inputting the control voltage of this circuit between the terminal an and the terminal bn. Is output.

FIG. 3 is a circuit diagram showing the nth power supply circuit (n is 1 or 2). This circuit has a diode 161 having an anode and a cathode for inputting a voltage input between an input terminal An and an input terminal Bn, an anode connected to the input terminal An and a cathode connected to an output terminal Cn, and the output terminal Cn. Is rectified and smoothed by a capacitor 162 having one end connected to the output terminal Dn and the other end connected to the output terminal Dn and the input terminal Bn, and output between the output terminal Cn and the output terminal Dn.

FIG. 5 is a diagram showing the voltage waveform of each part of the FET rectifier circuit of the present invention shown in FIG. 1 (related to rectifying FET), and FIG. 5 (a) shows the transistor 2 when the transistor 2 is switching. Voltage waveform across both ends of 2, (b)
Is the voltage waveform across the auxiliary winding 5, (c) is the collector-base voltage waveform of the transistor 141 in the first control circuit 14, and (d) is the source-drain voltage of the rectifying FET 10. Waveforms are shown respectively.

FIG. 6 is a diagram (commutation FET related) showing the voltage waveform of each part of the FET rectifier circuit of the present invention shown in FIG. 1, and FIG. 6 (a) shows this transistor when the transistor 2 is switching. Voltage waveform across both ends of 2, (b)
Is a voltage waveform across the third winding 6 wound in parallel with the smoothing coil 8, (c) is a voltage waveform between the collector and the base of the transistor 141 in the second control circuit 15, ( d) shows voltage waveforms between the source and drain of the commutation FET 11, respectively.

FIG. 7 is a diagram for explaining that the voltage above the threshold is delayed, and the flyback waveform shows that the voltage above the threshold is delayed by t time.

Referring to FIG. 5, the input voltage applied to the transformer 1 is switched by the transistor 2, and a voltage waveform (a) is generated at both ends of the transistor 2 in synchronization with this switching, and the auxiliary winding Line 5
A voltage waveform (b) is generated at both ends of. On the other hand, the first winding 9 added to the smoothing coil 8 and wound in parallel
4 occurs at both ends of the smoothing coil 8 at both ends of FIG.
A voltage waveform of the same type as in (b) is generated, and the first power supply circuit 16 inputs this voltage between the input terminal A1 and the input terminal B1, rectifies and smoothes this voltage, and outputs the output terminal C1 and the output terminal D1. Output between and. The first control circuit 14 is
The voltage output from the first power supply circuit 16 is input as a power supply voltage between the terminals e1 and d1, and the voltage generated in the auxiliary winding 5 is input as a control voltage between the terminals a1 and b1. Then, the reverse voltage of this control voltage is clamped by the diode 144 and the Zener diode 145 through the resistor 143 shown in FIG. 2 to generate the voltage waveform shown in (c) between the collector and the base of the transistor 141. A voltage of the same type as is output from the terminal c1 as a first control signal. The rectifying FET 10 is controlled by the first control signal, and when the transistor 2 is turned on, the FET is turned on and the FE is turned on.
A voltage waveform (d) is generated between the source and drain of T to perform rectification operation.

Next, referring to FIG. 6, when the input voltage applied to the transformer 1 is switched by the transistor 2, a voltage waveform (a) is generated at both ends of the transistor 2 in synchronization with this switching, A voltage waveform (b) is generated at both ends of the third winding 6 wound in parallel with the smoothing coil 8. On the other hand, the smoothing coil 8
A voltage waveform of the same type as that of FIG. 4 (b) generated at both ends of the smoothing coil 8 is generated at both ends of the second winding wire 7 which is added in parallel and is wound in parallel. This voltage is input between the input terminal A2 and the input terminal B2, rectified and smoothed, and output between the output terminal C2 and the output terminal D2. The second control circuit 15 inputs the voltage output from the second power supply circuit 17 between the terminals e2 and d2 as the power supply voltage, and the third control circuit 15 receives the voltage between the terminals a2 and b2. The voltage generated in the winding 6 is input as a control voltage, and the reverse voltage of this control voltage is input to the resistor 14 shown in FIG.
3 through diode 144 and Zener diode 14
And the transistor 1 is clamped by
A voltage waveform shown in (c) is generated between the collector and base of 41, and a voltage of the same type as this waveform is output from the terminal c2 as a second control signal. The second control signal controls the commutation FET 11 to turn off the transistor 2 when the transistor 2 is on, and a voltage waveform (d) is generated between the source and drain of the FET to perform commutation operation. .

Therefore, the voltage between the source and drain of the rectifying FET 10 generated by the rectifying operation of the rectifying FET 10 and the commutating operation of the commutating FET 11 (see FIG. 5).
(D)) and the source-drain voltage of the commutation FET 11 (FIG. 6 (d)) and the voltage generated at both ends of the secondary winding 4 (same shape as FIG. 5 (b)). Is output from the first output terminal 19a and the second output terminal 19b as a constant output voltage Vout which is smoothed by the smoothing coil 8 and the capacitor 18.

[0025]

As described above, according to the FET rectifying circuit of the present invention, the rectifying FET 10 and the commutating FET are provided.
Since the transistors 141 and 142 connected in a complementary manner are used in the control circuit for controlling 11 instead of the FETs 13 and 14, there is no driving loss of the circuit even if a wide range of voltage is input, and the FET 11 for commutation is controlled. Since the control voltage of the control circuit is taken not from the winding on the secondary side of the transformer 1 but from the third winding 6 of the smoothing coil 8, the commutating FET 11 changes from off to on even if the current flowing through the load changes. Since there is no delay in the time, the drive loss of the circuit does not occur. Further, the rectification FET 10 and the commutation F
The first of the smoothing coil 8 is used as the power supply voltage to be supplied to the ET 11.
Since a voltage generated in the winding 9 and the second winding 7 is rectified and smoothed, a constant power supply voltage is applied to the FET 10 and the FET 11 even if the input voltage input to the transformer 1 changes. Therefore, the voltage between the gate and source of the FET 10 and FET 11 is
The withstand voltage between the gate and source of T is not exceeded.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of an FET rectifier circuit of the present invention.

FIG. 2 is a circuit diagram showing an nth control circuit (n is 1 or 2).

FIG. 3 is a circuit diagram showing an nth power supply circuit (n is 1 or 2).

FIG. 4 is a diagram showing a voltage waveform generated in a smoothing coil.

FIG. 5 is a diagram showing voltage waveforms (related to a rectifying FET) of each part of the FET rectifying circuit of the present invention.

FIG. 6 is a diagram showing voltage waveforms (related to commutation FET) of each part of the FET rectifier circuit of the present invention.

FIG. 7 is a diagram illustrating that a voltage that becomes equal to or higher than a threshold value is delayed.

FIG. 8 is a circuit diagram showing an example of a conventional FET rectifier circuit.

FIG. 9 is a circuit diagram showing another conventional FET rectifier circuit.

FIG. 10 is a diagram showing voltage waveforms at various parts of a conventional FET rectifier circuit.

FIG. 11 is a diagram showing voltage waveforms of respective parts of another conventional FET rectifier circuit.

FIG. 12 is an operation explanatory view showing a state of a conventional FET rectifier circuit.

[Explanation of symbols]

 1 transformer 2 transistor 3 primary winding 4 secondary winding 5 auxiliary winding 6 third winding 7 second winding 8 smoothing coil 9 first winding 10 FET (for rectification) 11 FET (for commutation) ) 12, 13 Parasitic diode 14 First control circuit 15 Second control circuit 16 First power supply circuit 17 Second power supply circuit 18 Capacitor 19a First output terminal 19b Second output terminal 50 Transistor 51 Transformer 51a 1 Secondary winding 51b Secondary winding 51c, 51d Auxiliary winding 52 Resistance 53 FET (for rectification) 54 Resistance 55 FET (for commutation) 56 Inductance 57 Load 57a, 57b Connection terminal 58, 59 Parasitic diode 60 Capacitor 61, 62 Diode 63,64 FET 65,66 Parasitic diode 67,68,69,70 Resistor 71 Capacitor 14 1 PNP type transistor 142 PN type transistor 143 resistance 144 diode 145 zener diode 161 diode 162 capacitor

Claims (2)

[Claims] 1. A transformer having a primary winding on a primary side and a secondary winding and an auxiliary winding on a secondary side, and a switching element for switching an input voltage applied to the primary side of the transformer. A rectifying element that is installed on the secondary side of the transformer and uses an insulated gate field effect transistor that is turned on by the positive electromotive force of the transformer; and a first output terminal that outputs the rectifying element and an output voltage. A smoothing coil connected between the smoothing coil and an insulating gate field effect transistor which is installed on the secondary side of the transformer and is turned on by a back electromotive force generated in the smoothing coil when the switching element is off. A diversion element; a first power supply circuit for rectifying and smoothing the voltage across both ends of a first winding wound in parallel with the smoothing coil; and outputting the output voltage of the first power supply circuit as a power supply. A first control circuit that outputs a first control signal for controlling the rectifying element by inputting a voltage across the auxiliary winding wound on the secondary side of the transformer as a control voltage. A second power supply circuit that rectifies and smoothes the voltage across both ends of a second winding additionally wound in parallel with the smoothing coil, and outputs the output voltage of the second power supply circuit as the power supply voltage; A second control circuit for outputting a second control signal for controlling the commutation element, using a voltage across a third winding additionally wound in parallel with the coil as a control voltage; and the output voltage And a smoothing capacitor that is connected between the first output terminal and the second output terminal for outputting the output voltage to smooth the output voltage. 2. The first control circuit and the second control circuit each include a complementary connected transistor and a reverse voltage preventing diode connected to the input side of the transistor. FE described in 1
T rectifier circuit.