JPH0962391A - Reference voltage generation circuit - Google Patents

Abstract

Provided is a reference voltage generation circuit which is configured by using a MOS field effect transistor and which can easily set a temperature coefficient of a reference voltage to a predetermined value. SOLUTION: An operational amplifier 10 in which resistors 12 (resistance value R1) and 14 (resistance value R2) are connected between an output terminal and non-inverting and inverting input terminals, and a transistor Tr1 connected to the non-inverting input terminal. And a transistor Tr2 connected to the inverting input terminal via a resistor 16 (resistance value R3). The gate width W and the gate length L of each of the transistors Tr1 and Tr2 are formed to be equal to each other, and further, R1 = R
3, (W / L) × R3 = 0.7 × 10 ⁶ Ω, R2 / R3
= 4.6, the resistance values R1 to R3, the gate width W, and the gate ratio L, that is, the transistor characteristics are associated with each other. As a result, the temperature coefficient of the reference voltage Vo output by the reference voltage generation circuit 2 becomes substantially equal to the minimum value of the temperature coefficient that can be realized by the circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reference voltage generating circuit for generating a reference voltage having excellent temperature characteristics in a CMOS integrated circuit or the like.

[0002]

2. Description of the Related Art Conventionally, as a reference voltage generating circuit for generating a reference voltage having a small temperature coefficient for use as a reference for circuit operation in an electronic circuit, for example, the IEEE Journal of
As disclosed in Solidstate circuits.Volsc-8.PP222 (1973), the bandgap voltage based on the PN junction of the semiconductor element has a stable temperature characteristic with little variation, and this bandgap voltage is It is known to generate a reference voltage based on this.

That is, the reference voltage generating circuit 8 is shown in FIG.
As shown in (a), an operational amplifier 10 that outputs a predetermined reference voltage Vo, a resistor 12 (resistance value R1) connected between the output terminal of the operational amplifier 10 and the non-inverting input terminal,
The resistor 14 (resistance value R2) connected between the output terminal and the inverting input terminal of the operational amplifier 10, the base and the collector are connected to each other and the non-inverting input of the operational amplifier 10, and the emitter is A first semiconductor circuit including a grounded bipolar transistor B1 and a resistor 16 (resistance value R3) having one end connected to the inverting input of an operational amplifier.
And a second semiconductor circuit including a bipolar transistor B2 having a base and a collector connected to each other and the other end of the resistor 16 and an emitter grounded.

The bipolar transistors B1 and B2
Have different current driving capabilities. That is, in order to operate the operational amplifier 10 so that the predetermined reference voltage Vo is output from the output terminal,
The current of each current path is such that the characteristics of the voltage applied to each input terminal based on the current flowing in each current path to which the bipolar transistors B1 and B2 are connected intersect at one point when the output terminal is at the reference voltage Vo. This is to make the characteristics different from each other.

The reference voltage generating circuit 8 configured as described above
, The potential of the inverting input terminal to which one end of the resistor 16 is connected is equal to the base-emitter voltage Vbe1 of the bipolar transistor B1 applied to the non-inverting input, due to the imaginary short circuit of the input terminal of the operational amplifier 10.
On the other hand, the other end of the resistor 16 has a bipolar transistor B
A base-emitter voltage Vbe2 of 2 is applied. Therefore, the bipolar transistor B is connected to both ends of the resistor 16.
1, B2 base-emitter voltage difference (Vbe1-Vbe
2) is applied, and a constant current I2 flows according to the voltage across this and the resistance value R3. As a result, the added value of the predetermined voltage I2 · R2 induced in the resistor 14 by the current I2 and the base-emitter voltage Vbe1 of the bipolar transistor B1 is output from the operational amplifier 10 as the reference voltage Vo.

The reference voltage Vo generated by the reference voltage generating circuit 8 is expressed by the following equation (1).

[0007]

[Equation 1]

K is the Boltzmann constant, t is the absolute temperature, and q is the elementary charge. The reference voltage generation circuit 9 shown in FIG. 5B is configured by using diodes D1 and D2 instead of the diode-connected bipolar transistors B1 and B2 of the reference voltage generation circuit 8 of FIG. ,base·
A forward voltage Vr is used instead of the emitter-to-emitter voltages Vbe1 and Vbe2.
The reference voltage Vo is generated based on 1 and Vr2, and the reference voltage Vo in this case is expressed by the following equation (2).

[0009]

[Equation 2]

Then, the base-emitter voltage Vbe1
The (forward voltage Vr1) has a negative temperature coefficient (about −2 mV / ° C.), but as can be seen from the equations (1) and (2), the resistance values R1 to R3 and the characteristics of the transistor are appropriately set. By setting the first term of the equations (1) and (2) to have a positive temperature coefficient of the same magnitude as that of the first term, the temperature coefficient of the reference voltage Vo can be made substantially zero.

However, such a reference voltage generating circuit 8,
9 is to be realized on a CMOS integrated circuit, the reference voltage generating circuit 8 using the bipolar transistors B1 and B2 requires a BiCMOS process in which a CMOS process and a bipolar process are combined in the manufacturing thereof. There was a problem that became complicated.

Further, in the case of the reference voltage generating circuit 9 using the diodes D1 and D2, it is possible to use various PN junctions in the CMOS process, but it is designed so that a parasitic transistor that deteriorates the circuit characteristics is not formed. There was a problem that it was difficult to do.

Therefore, in order to solve these problems,
As the first and second semiconductor circuits, instead of the bipolar transistors B1 and B2 (diodes D1 and D2),
Attempts have been made to construct using N-channel MOS field effect transistors.

[0014]

However, when the MOS field effect transistor is used, the voltage applied to the non-inverting input is not based on the PN junction, so that the theoretical formula for determining the reference voltage is as described above ( It becomes much more complicated than the equations (1) and (2). As a result, it is extremely troublesome to design parameters such as resistance values R1 to R3 and transistor characteristics so that the temperature coefficient of the reference voltage becomes a predetermined value. There was a problem of cost.

Further, when the MOS field effect transistor is used, in order to simplify the parameter design, it is necessary to make the threshold voltage of the MOS field effect transistor equal in order to simplify the theoretical formula as much as possible. However, for example, when the reference voltage generating circuit is formed on a CMOS integrated circuit, if the current driving capacities of the respective transistors are made different from each other as in the conventional device, variations in characteristics caused by manufacturing in each transistor. Since it is different, it is difficult to match the threshold voltage of each transistor, and as a result, the temperature coefficient as designed can not be realized when actually manufactured, and the accuracy is degraded. was there.

In order to solve the above problems, the present invention provides
An object of the present invention is to provide a reference voltage generation circuit which is configured by using a MOS type field effect transistor and which can easily set the temperature coefficient of the reference voltage to a predetermined value.

[0017]

The invention according to claim 1 made in order to achieve the above object, is an operational amplifier for outputting a predetermined reference voltage to an external device, and an output of the operational amplifier. A first resistor connected between the terminal and the non-inverting input terminal, a second resistor connected between the output terminal of the operational amplifier and the inverting input terminal, and one end of which is connected to the non-inverting input terminal. The other end is connected and grounded.
A first semiconductor circuit that causes a current to flow from the output terminal side to the non-inverting input terminal side, a third resistor having one end connected to the inverting input terminal, and one end having the third resistor A second semiconductor circuit connected to the opposite side of the inverting input terminal and the other end of which is grounded, and a current flows through the second resistor from the output terminal side toward the inverting input terminal side. The operational amplifier is induced by a current flowing through the second and third resistors based on a difference between voltages across the first and second semiconductor circuits and a resistance value of the third resistor. In the reference voltage generating circuit, which outputs the added value of the voltage across the second resistor and the voltage applied to the non-inverting input terminal by the first semiconductor circuit as the reference voltage, the first semiconductor Circuit, gate and drain are the above calculation It is composed of a first N-channel MOS field effect transistor connected to the non-inverting input terminal of the width device and having a source grounded, and the second semiconductor circuit has a gate and a drain connected to the third resistor. And a second N-channel MOS type field effect transistor whose source is grounded. Further, the gate width and the gate length of the first and second N-channel MOS type field effect transistors are formed to have the same size. The resistance values of the first to third resistors are set so that the temperature coefficient of the reference voltage becomes a predetermined value.

In the reference voltage generating circuit thus constructed, the potential of the inverting input terminal becomes equal to the potential of the non-inverting input terminal due to the imaginary short circuit of the input terminal of the operational amplifier circuit, so that one end of the inverting input terminal, The difference between the voltages across the first and second semiconductor circuits is applied across the third resistor, the other end of which is connected to the second semiconductor circuit. As a result, a predetermined current corresponding to the voltage applied across the third resistor and the resistance value of the third resistor flows through the second and third resistors, and the predetermined current causes the second resistor to pass through the second resistor. The added value of the induced both-end voltage and the voltage applied to the non-inverting input terminal by the first semiconductor circuit is output from the output terminal as a reference voltage. Also, the resistance values of the first to third resistors,
By appropriately setting the characteristics of the first and second N-channel MOS field effect transistors, the temperature coefficient of the reference voltage can be set arbitrarily.

In the present invention, the first and second
The gate width and the gate length of the N channel MOS type field effect transistor are formed to have the same size, and the transistors have the same current characteristics. Therefore, according to the present invention, the reference voltage generating circuit is provided in the CMOS.
When forming on an integrated circuit, since the conditions at the time of forming each transistor are exactly the same, the threshold voltage of each transistor can be made exactly the same, and the reference voltage generating circuit can be exactly as designed. A reference voltage can be generated.

Further, since the characteristics of the respective transistors are made equal, the theoretical formula expressing this reference voltage, and by extension, the theoretical formula of the temperature coefficient obtained by differentiating the theoretical formula of this reference voltage with respect to temperature, are simplified. When the temperature coefficient is set to a predetermined value, the design of parameters such as the resistance values of the first to third resistors can be facilitated.

Next, the invention described in claim 2 is the same as claim 1.
In the reference voltage generating circuit described in the paragraph 1,
The respective resistance values of the resistors are set to the same value, and the ratio W / L of the gate width W and the gate length L of the N-channel MOS field effect transistors forming the first and second semiconductor circuits is set.
And the resistance value of the third resistor is 0.7 × 1
It is characterized by being set to 0 ⁶ Ω or more.

According to the reference voltage generating circuit configured as described above, the reference voltage generating circuit can be generated by appropriately setting the ratio R2 / R3 of the resistance value R2 of the second resistor and the resistance value R3 of the third resistor. The temperature coefficient can be arbitrarily set with the minimum absolute value of the temperature coefficient that can be realized by the circuit as the lower limit.

That is, based on the theoretical expression of the temperature coefficient, the ratio R2 / of the resistance value R2 of the second resistor and the resistance value R3 of the third resistor is R2 /
When the characteristic of the absolute value of the temperature coefficient when R3 is changed as a parameter is obtained, the characteristic has a minimum value. The ratio of the gate width W and the gate length L of the transistor W /
The multiplication value of L and the resistance value of the third resistor is 0.7 × 1.
When set to 0 ⁶ Ω or more, the minimum value becomes substantially equal to the minimum temperature coefficient that can be realized by the reference voltage generating circuit. Therefore, the ratio R2 of the resistance values of the second and third resistors is
By arbitrarily setting / R3, it is possible to arbitrarily set the temperature coefficient with the minimum absolute value of the temperature coefficient that can be realized by the reference voltage generation circuit as the lower limit.

Next, the invention according to claim 3 is the reference voltage generating circuit according to claim 2, further comprising a resistance value R2 of the second resistor and a resistance value R3 of the third resistor. The ratio R2 / R3 is set to about 4.6.

In the reference voltage generating circuit thus constructed, the absolute value of the temperature coefficient of the reference voltage can be made substantially equal to the minimum value that can be realized by the reference voltage generating circuit. That is, when the absolute value of the temperature coefficient is calculated based on the theoretical expression of the temperature coefficient, the product of the ratio W / L of the gate width W and the gate length L of the transistor and the resistance value of the third resistor is obtained. When it is 0.7 × 10 ⁶ Ω or more, the ratio R2 / R3 of the resistance values of the second and third resistors becomes the minimum value when the ratio R2 / R3 is about 4.6. Therefore, the first to third resistance values and the gate width W of the first and second N-channel MOS transistors
The temperature coefficient of the reference voltage of the reference voltage generating circuit, in which the ratio W / L of the gate length L is related as described above, is substantially equal to the minimum value of the temperature coefficient that can be realized by the reference voltage generating circuit. It will be.

Further, according to the reference voltage generating circuit of the present invention, the resistance value of the first resistor, the resistance value of the second resistor, and the gate widths of the first and second N-channel MOS type field effect transistors. The ratio W / L of W to the gate length L is all related to the resistance value of the third resistor, and therefore, setting the resistance value of any of the first to third resistors will set these values. Since the resistance value and the characteristics of the first and second N-channel MOS type field effect transistors can all be determined, the design can be performed very easily.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing the overall configuration of the reference voltage generating circuit of this embodiment. In addition, as shown in FIG.
In the reference voltage generating circuit 2 of this embodiment, in the reference voltage generating circuits 8 and 9 of the conventional device shown in FIG. 5, the first semiconductor circuit is the bipolar transistor B1 (diode D).
Instead of 1), the source is grounded and the gate and drain are composed of a first transistor Tr1 composed of an N-channel MOS type field effect transistor connected to the non-inverting input terminal of the operational amplifier 10. The circuit
Instead of the bipolar transistor B2 (diode D2), the source is grounded and the gate and drain are resistors 1
The second transistor Tr2, which is an N-channel MOS field effect transistor connected to the transistor 6, is the same as that of the second transistor Tr2.
And the resistors 12, 14, 16 have resistance values R1, R2, R3.
Is the same as the conventional device except for the difference.

The first and second transistors Tr
As shown in FIG. 2, an N-channel MOS type field effect transistor (hereinafter, referred to as an NMOS transistor) forming the transistors 1 and Tr2 is formed by a P type silicon substrate 20 and impurity diffusion on the silicon substrate 20. The N-type drain region 22 and the source region 24, the electrically insulating oxide film 26 formed on the substrate surface between the drain region 22 and the source region 24, and the substrate 2 with the oxide film 26 interposed therebetween.
The gate electrode 28 is made of metal and is formed so as to face 0.

Then, when a positive voltage is applied to the gate electrode 28, electrons are induced at the interface between the oxide film 26 and the substrate 20 directly under the gate electrode 28, and an N-type is formed between the drain region 22 and the source region 24. The conductive layer (channel) 30 is formed. The size of the channel 30, that is, the gate electrode 2
The magnitude of 8 determines the magnitude of the drain current, and the shorter the length (gate length) L and the wider the width (gate width) W, the larger the current value. That is, the current characteristics of the first and second transistors Tr1 and Tr2 are determined by the gate width W and the gate length L. Note that in FIG. 2, the gate width W extends in the depth direction of the drawing.

The reference voltage generating circuit 2 thus constructed
, The first transistor Tr1 has a resistance value R of the resistor 12 based on its gate voltage / drain current characteristic.
A predetermined current I1 determined by 1 and the reference voltage Vo is passed through the resistor 12, and a predetermined voltage is applied to the non-inverting input terminal of the operational amplifier 10. On the other hand, the second transistor Tr2
Supplies a predetermined current I2, which is determined by the resistance value R3 of the resistor 16 and the potential of the inverting input terminal of the operational amplifier 10, to the resistors 14 and 16 based on the gate voltage / drain current characteristics. Then, the operational amplifier 10 outputs the added value of the potential of the non-inverting input terminal and the voltage across the resistor 14 due to the current I2 as the reference voltage Vo.

In this embodiment, the resistance value R1
~ R3 and the first and second transistors Tr1, T
Gate widths W1 and W2 and gate lengths L1 and L2, which are parameters that determine the gate voltage / drain current characteristics of r2
Are set to satisfy the following relational expressions (A) to (C).

(A) W1 = W2 = W, L1 = L2 = L (B) R1 = R3 (C) K = (W / L) × R3 = 0.7 × 10 ⁶ Ω That is, the relational expression (A) Thus, the first and second transistors Tr1 and Tr2 have the same gate voltage / gate current characteristics, the resistance values R1 and R3 are associated with each other by the relational expression (B), and According to the relational expression (C), the first and second transistors Tr1,
The characteristic of Tr2 and the resistance values R1 and R3 are associated with each other. In the following, the ratio of the gate width W to the gate length L W / L
And a resistance value R3 multiplied by a parameter K (= (W /
It is called L) x R3).

FIG. 3 is a theoretical formula for obtaining the temperature coefficient, where the ratio of the resistance value R2 of the resistor 14 to the resistance value R3 of the resistor 16 is used as a parameter M (= R2 / R3) in the circuit thus set. 9 is a graph in which the absolute value | Verr | of the temperature coefficient is obtained using (see the equation (10) described later). The parameter M is changed by setting R1 = R3 = 18 kΩ and W / L = 40 and changing R2.

As shown in FIG. 3, the absolute value of the temperature coefficient | V
err | has a minimum value when the parameter M is 4.6, and the value at that time is 0.039 mV / ° C. The characteristic is that the value of the parameter K is 0.7 × 10 ⁶ Ω.
When it is made larger, it becomes a characteristic having a minimum value in the vicinity of M = 4.6, and the minimum value becomes substantially the same as the characteristic shown in FIG. On the other hand, when the value of the parameter K is smaller than 0.7 × 10 ⁶ Ω, the smaller the value of the parameter K is, the more the characteristic shown in FIG. 3 is shifted to the upper left in the figure. Becomes

That is, this minimum value is the minimum value of the temperature coefficient | Verr | that can be realized in the reference voltage generating circuit 2. Therefore, in the reference voltage generating circuit 2 of the present embodiment set to satisfy the relational expressions (A) to (C), the temperature coefficient of the reference voltage Vo is set by appropriately selecting and setting the value of the parameter M. Verr can be arbitrarily set with the minimum value of the temperature coefficient | Verr | that can be realized in the circuit as the lower limit.

In this embodiment, the temperature coefficient | Verr |
The reference voltage generating circuit 2 designed to have a predetermined value
When implemented on an integrated circuit, the gate widths W1 and W2 and the gate lengths L1 and L2 of the first and second transistors Tr1 and Tr2 are made equal, so that the transistors Tr1 and Tr2 are set under exactly the same conditions. And the threshold value Vth of these transistors Tr1 and Tr2.
Can be exactly equal. Therefore, it is possible to accurately realize the temperature coefficient | Verr | obtained by the design.

As described above, a substantially similar minimum value can be obtained even if the value of the parameter K is larger than 0.7 × 10 ⁶ Ω, so only when the relational expression (C) is satisfied. Not limited to the above, as long as the following relational expression (C ′) is satisfied, the same effect as this embodiment can be obtained.

(C ′) K = (W / L) × R3 ≧ 0.7 × 10 ⁶ Ω Next, a second embodiment will be described. In the present embodiment, the reference voltage generating circuit 2 of the first embodiment set to satisfy the relational expressions (A) to (C) is further set to satisfy the following relational expression (D). .

(D) M = R2 / R3 = 4.6 Specifically, R1 = R3 = 18 kΩ, R2 = 82.8 k
Ω, W / L = 40 is set. That is, in the reference voltage generating circuit 2 of the present embodiment set to satisfy the relational expressions (A) to (D), the absolute value | Verr | of the temperature coefficient of the reference voltage Vo is always the reference voltage. It becomes possible to generate the reference voltage Vo having an excellent temperature characteristic, which is substantially equal to the minimum value that can be realized in the generation circuit 2.

In this embodiment, the relational expression (A)
From (D), the resistance value R1, the resistance value R2, and the ratio W / L of the gate width W and the gate length L of the first and second transistors Tr1 and Tr2 are all related to the resistance value R3. Therefore, if any of the resistance values R1 to R3 is determined, the resistance values R1 to R3 and the transistors Tr1 and T3 are set.
All the characteristics of r2 can be determined, and it is possible to design extremely easily.

Here, FIG. 4 is a graph in which the absolute value | Verr | of the temperature coefficient is obtained by changing the parameter K based on the theoretical expression for obtaining the temperature coefficient Verr (see the equation (10) described later). . The resistance values R1 to R3 are R1 = R3
= 18 kΩ, R2 = 82.8 kΩ, gate width W
The parameter K is changed by changing the ratio W / L of the gate length L to the gate length L.

As shown in FIG. 4, as the parameter K becomes larger, the absolute value of the temperature coefficient │Verr│ sharply decreases, and the minimum value 0.039 mV at K = 0.7 × 10 ⁶ Ω.
/ ° C., and with the parameter K> 0.7 × 10 ⁶ Ω, the absolute value of the temperature coefficient | Verr | becomes a substantially constant value.

This characteristic shifts to the upper right in the figure when the value of the parameter M is larger than 4.6, and conversely shifts to the upper left when the value of the parameter M is smaller than 4.6. To do. That is, not only when the value of the parameter K is 0.7 × 10 ⁶ Ω, but when the value is more than this value, the absolute value | Verr | of the temperature coefficient becomes substantially equal to the minimum value. Therefore, also in this embodiment. Similar to the first embodiment, the same effect as in the present embodiment can be obtained not only in the case of the relational expression (C) but also in the range of the relational expression (C ′).

Next, the theoretical formula used for obtaining the temperature coefficient Verr of the reference voltage Vo will be described. First, the theoretical formula representing the reference voltage Vo of the reference voltage generating circuit 2 is represented by the following formula.

[0045]

(Equation 3)

K: Boltzmann constant, q: electron charge amount,
t: absolute temperature, e: base of natural logarithm I1 (t), I2 (t): respective transistors Tr1, Tr
2 drain current Vth (t): threshold voltage of transistors Tr1 and Tr2 G (t): a function based on the physical properties of the substrate 20. Note that equation (3) is based on the assumption that the threshold voltages of the transistors Tr1 and Tr2 are equal. It is a thing.

In the equation (3), the first and second terms are
The potential of the non-inverting input terminal (the same applies to the inverting input terminal) of the operational amplifier 10 and the third term represent the voltage across the resistor 14. Then, the drain currents Ii (t), {i = 1,
2}, threshold voltage Vth (t), function G (t)
Is expressed by the following equations (4) to (6).

[0048]

(Equation 4)

[0049]

(Equation 5)

[0050]

(Equation 6)

However,

[0052]

(Equation 7)

[0053]

(Equation 8)

Εsi: Dielectric constant of silicon forming the substrate 20 Cox: Capacity of the oxide film 26 μ: Mobility of carriers on the surface of the substrate 20 Ns: Impurity concentration of the substrate 20 Ni: Intrinsic carrier concentration of the substrate 20 Vds: Drain -Source voltage Vsb: source-substrate voltage Vde: drain-source voltage or drain saturation voltage, whichever is smaller fb, fs: drain region 22 and source region 24 formed on the substrate by impurity diffusion, A correction value for correcting the influence of an error due to the diffusion to just below the gate electrode 28 and the shortening of the length of the channel 30. In the equation (4), the transistors Tr1 and Tr2 are
Sub-threshold region, that is, a voltage near the threshold voltage Vth is applied between the gate and the source,
It is the one when it is operated so that the channel is not completely formed between the sources.

In the equations (3) to (8), the Boltzmann constant k, the electron charge q, and the base e of the natural logarithm are constants, and the dielectric constant εsi of silicon, the mobility μ of carriers, and the oxidation. The film capacitance Cox, the impurity concentration Ns, the intrinsic carrier concentration Ni, and the correction values fb and fs are determined to be predetermined values according to the manufacturing process conditions, and the drain-source voltage Vds, the source-substrate voltage Vsb, and the voltage Vde are produced. It is a value that is dependently determined according to the circuit operation based on the characteristics of the formed transistor.

That is, the temperature coefficient V obtained by the differential equation of the reference voltage Vo and the theoretical equation of the reference voltage Vo.
err is a resistance value R1 to R3 and a current value I1 (t), I
It is adjusted by setting 2 (t) appropriately. Among them, the current values I1 (t) and I2 (t) are the first and second transistors Tr1 and Tr, as can be seen from the equation (4).
It is adjusted by the gate width Wi of 2 and the gate length Li.

Here, based on the relational expressions (A) to (D),
When the theoretical formula of the reference voltage Vo shown in the formula (3) is arranged,
It becomes like the following formula. For the relational expressions (C) and (D), the numerical values are not determined and the parameters M and K are used.

[0058]

[Equation 9]

In particular, the relational expression (A), that is, the first and second
Gate widths W1 and W2 of the transistors Tr1 and Tr2 of
By making the gate lengths L1 and L2 equal to each other, I1
(T) = I2 (t), and in the formula (3), the terms that cancel each other out and depend on the temperature are reduced, so that the theoretical formula of the reference voltage Vo is simplified.

The temperature coefficient Verr of the reference voltage Vo obtained by differentiating the equation (9) with respect to the absolute temperature t is represented by the following equation.

[0061]

(Equation 10)

In this equation, when each value is appropriately set and the parameter M is changed, as shown in FIG. 3, the characteristic that the absolute value | Verr | of the temperature coefficient has a minimum value, and the second value is obtained. When the parameter K is changed, as shown in FIG. 4, it is possible to obtain the characteristic that the value becomes substantially constant above a predetermined value.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a configuration of a reference voltage generation circuit according to an embodiment.

FIG. 2 is an explanatory diagram showing a structure of an N-channel MOS type field effect transistor.

FIG. 3 is a graph showing a simulation result in which the characteristic of the temperature coefficient of the reference voltage Vo is obtained using M = R2 / R3 as a parameter.

FIG. 4 is a graph showing a simulation result in which the characteristic of the temperature coefficient of the reference voltage Vo is obtained using K = (W / L) × R3 as a parameter.

FIG. 5 is an electric circuit diagram showing a configuration of a conventional reference voltage generating circuit.

[Explanation of symbols]

2 ... Reference voltage generating circuit 10 ... Operational amplifier 12,
14, 16 ... Resistor 20 ... Silicon substrate 22 ... Drain region 24 ...
Source region 26 ... Oxide film 28 ... Gate electrode 30 ... Channel Tr1 ... First transistor Tr2 ... Second transistor

Claims (3)

[Claims] 1. An operational amplifier for outputting a predetermined reference voltage to an external device, a first resistor connected between an output terminal and a non-inverting input terminal of the operational amplifier, and the operational amplifier. A second resistor connected between the output terminal and the inverting input terminal, one end connected to the non-inverting input terminal and the other end grounded, and the first resistor from the output terminal side to the above A first semiconductor circuit that allows a current to flow toward the non-inverting input terminal side, a third resistor having one end connected to the inverting input terminal, and one end opposite to the inverting input terminal of the third resistor. A second semiconductor circuit that is connected to the second resistor and has the other end grounded, and supplies a current to the second resistor from the output terminal side toward the inverting input terminal side. The difference between the voltages across the first and second semiconductor circuits and the third resistance Of the voltage across the second resistor induced by the current flowing through the second and third resistors based on the resistance value of the resistance and the voltage applied to the non-inverting input terminal by the first semiconductor circuit. In the reference voltage generating circuit for outputting the added value from the output terminal as the reference voltage, the first semiconductor circuit is configured such that the gate and the drain are connected to the non-inverting input terminal of the operational amplifier and the source is grounded. And a second semiconductor circuit having a gate and a drain connected to the third resistor and a source grounded. In addition, the first and second N-channel MOS field effect transistors are formed to have the same gate width and gate length, respectively. So that the temperature coefficient of the voltage reaches a predetermined value, the reference voltage generating circuit, characterized by comprising setting the resistance value of the resistance of the first to third. 2. The reference voltage generating circuit according to claim 1, wherein the resistance values of the first and third resistors are set to the same value, and each of the first and second semiconductor circuits is configured. The multiplication value of the ratio W / L of the gate width W and the gate length L of the N-channel MOS field effect transistor and the resistance value of the third resistor is set to 0.7 × 10 ⁶ Ω or more. A reference voltage generation circuit characterized by the above. 3. The reference voltage generating circuit according to claim 2, wherein the ratio R2 / R3 of the resistance value R2 of the second resistor and the resistance value R3 of the third resistor is approximately 4.6. A reference voltage generating circuit characterized by being set to.