JPH096302A - Error diffusion processing circuit - Google Patents

Abstract

(57) [Summary] [Purpose] To obtain high-definition images on the display panel with improved calculation accuracy. [Configuration] A reproduction error is added to an input video signal by vertical and horizontal direction addition circuits 14 and 16 to obtain a diffused output signal,
The signal is converted into a signal with a small number of bits and is output from the output terminal 20 to the display panel. The difference between the diffused output signal and the threshold value of the threshold value selection circuit 24 is calculated by the error calculation circuit 22, weighted by the weight circuit 28, and delayed by the delay circuit 30. , 32 to delay and output as reproduction error to addition circuits 16 and 14
At the rounding error detection circuit 44 and the rounding error delay circuit 5,
0 is provided, the detection circuit 44 detects when the operation result of the error operation circuit 22 is an odd number and is positive, and the data “1” is added to the addition circuit 16 via the delay circuit 50. Therefore, when the input data is "01", the data "1" is output from the detection circuit 44 and added to the input data by the adder circuit 16. Therefore, the input data "01" and "00" are displayed on the display panel. Can be seen.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel (PDP) and a liquid crystal display panel (LCD).
The present invention relates to an error diffusion processing circuit for displaying a halftone image in a display device using a display panel such as P).

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention is paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system, and is a direct drive system by a digitized video input signal. Therefore, the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are divided into two types, AC type and DC type, which have different basic characteristics. Among these, AC type PDPs have sufficient characteristics in brightness and life, but in gradation display, they are prototype level. However, there was only a report of displaying up to 64 gradations.
Recently, a future 256-gradation method based on the address / display separation type driving method (ADS subfield method) has been proposed.

This is because one frame has a relative luminance ratio of 1,
It consists of eight subfields of 2, 4, 8, 16, 32, 64, and 128, and 25 combinations of luminance of eight screens
6-gradation display is performed. Each subfield is composed of an address period for writing refreshed data for one screen and a sustain period for determining the brightness level of the subfield. In the address period, wall charges are initially formed in each pixel at the same time on the entire screen, and then sustain pulses are applied to the entire screen for display.
The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the above-described AC driving method, as the number of gradations increases, the number of bits in an address period as a preparation period for lighting and emitting a panel within one frame period increases. The period becomes relatively short, and the maximum luminance decreases. In this way, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is lowered. Conversely, if the number of bits of the signal to be handled is reduced, the light emission luminance is increased, but gradation display is reduced. This causes deterioration of image quality.

Therefore, the applicant of the present invention, as shown in FIG.
An error diffusion processing circuit 10 for displaying a halftone image on a PDP or LCDP display device has been proposed. In the error diffusion processing circuit 10 shown in FIG. 4, a video signal output terminal 20 is connected to a video signal input terminal 12 via a vertical direction addition circuit 14, a horizontal direction addition circuit 16 and a bit conversion circuit 18, and a horizontal direction addition circuit is provided. The error calculation circuit 22 and the threshold selection circuit 24 are connected to the output side of 16 and the output side of the threshold selection circuit 24 is connected to the input side of the error calculation circuit 22 via the coefficient circuit 26 having a coefficient value of −1. A weighting circuit 28 having a weighting amount of 1/2 is connected to the output side of the error calculating circuit 22.

On the output side of the weighting circuit 28, the original pixel A
Reproduction error E that occurred 1 dot earlier than (i, j)
A 1-dot delay circuit 30 that outputs (i-1, j) to the horizontal direction addition circuit 16 is coupled, and the 1-dot delay circuit 3
The output side of 0 is further coupled to a 1-line delay circuit 32 that outputs a reproduction error E (i-1, j-1) generated by one line in the past to the vertical direction addition circuit 14.

Then, the diffusion output signal in which the error is incorporated and diffused by the vertical direction addition circuit 14 and the horizontal direction addition circuit 16 is sent to the bit conversion circuit 18, and the diffusion output quantized by n bits by the bit conversion circuit 18. Signal to m
It is converted into (≦ n−1) bits and output from the video signal output terminal 20 to the PDP as a drive signal. In this way,
An original image input signal is diffused by incorporating an error, and a signal having a bit number smaller than that of the original image input signal allows a smooth response to be obtained without lowering the emission brightness.

[0008]

However, in the error diffusion processing circuit 10 shown in FIG. 4, the weighting circuit 28 shifts by 1 bit so that the error calculation result of the error calculation circuit 22 becomes 1/2. Since weighting is performed, when the error calculation result is an odd number, the "1" at the LSB (least significant digit) is truncated. Therefore, when shading is input, for example, "00" and "01" are displayed in the same pattern (for example, PD
There was a problem that it would be output to P).

The present invention has been made in view of the above problems, and an object of the present invention is to improve the calculation accuracy so that a high-definition image can be obtained on a display panel (for example, PDP). . For example, it is intended to make the difference between “00” and “01” of input data visible on the display panel when shading is input.

[0010]

According to the present invention, a reproduction error is added to a digitized input video signal by an adder circuit to obtain a diffused output signal, and the diffused output signal is converted into a signal having less bits than input bits. While converting and outputting to the display panel, the difference between the diffused output signal and the threshold value selected for the display panel is calculated by the error calculation circuit, weighted by the weight circuit, and delayed by the delay circuit as a reproduction error. In the error diffusion processing circuit for outputting to the adder circuit, a rounding error detection circuit that detects when the operation result of the error operation circuit is odd and positive and outputs data "1", and the rounding error detection circuit And a rounding error delay circuit for delaying the output data by the same amount as the delay amount of the delay circuit and outputting it as added data to the adder circuit. It is intended to.

[0011]

When the weighting amount of the weighting circuit is 1/2, the weighting circuit shifts by 1 bit as in the conventional example, so that the calculation result of the error calculation circuit becomes 1
/ 2 is weighted. The error weight output signal output from the weight circuit is added to the adder circuit via the delay circuit. At this time, the rounding error detection circuit detects that the operation result of the error operation circuit is odd and positive, and detects the data "1".
Is added to the adder circuit via the rounding error delay circuit.
The delay amount of this rounding error delay circuit is set to be the same as the delay amount of the delay circuit.

Therefore, when the shading is input and the input data is "01", the rounding error detection circuit outputs data "1" and the addition circuit adds the data to the input data, but the input data is "00". Sometimes, the rounding error detection circuit does not output the data "1".
Therefore, "01" and "00" of the input data can be visually recognized on the display panel (display panel).
This is because the bits other than the LSB are the same, and the LSB is "1".
The difference between the input data “0” and “0” means that the data can be visually recognized on the display panel.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In FIG. 1, the same parts as those in FIG. 4 are designated by the same reference numerals. Reference numeral 40 represents an error diffusion processing circuit showing an embodiment of the present invention. The error diffusion processing circuit 40 is constructed as follows. That is, 12 is a video signal input terminal of an original pixel A (i, j) of n bits (for example, 8 bits). The video signal input terminal 12 includes a vertical direction addition circuit 14, a horizontal direction addition circuit 16, and an overflow processing circuit. It is connected to the video signal output terminal 20 via the bit conversion circuit 18 that performs a process of reducing the number of bits. An m-bit input (for example, 5-bit input) display panel (for example, PDP) is coupled to the video signal output terminal 20.

An error calculation circuit 22 and a threshold selection circuit 24 are coupled to the output side of the horizontal direction addition circuit 16, and the error calculation is performed on the output side of the threshold value selection circuit 24 via a coefficient circuit 26 having a coefficient of -1. It is coupled to the input side of circuit 22.
On the output side of the error calculation circuit 22, the weighting amount is 1/2.
After passing through the weighting circuit 28 of FIG.
= 1) via the 1-dot delay circuit 30 and the horizontal direction adder circuit 16 and also connected to the input side of the 1-line delay circuit 32 as an example of the h-line delay circuit (h = 1), The output side of the one-line delay circuit 32 is connected to the vertical direction addition circuit 14.

The one-dot delay circuit 30 outputs the error weight output signal output from the weight circuit 28 for one dot (1
The reproduction error E (i-1, j) of the pixel one dot before the original pixel A (i, j) is output. The 1-line delay circuit 32 delays the error-weighted output signal output from the 1-dot delay circuit 30 by 1 line, and for a pixel (1 line + 1 dot) before the original pixel A (i, j). Reproduction error E (i-
1, j-1) is output.

On the output side of the error calculation circuit 22, a rounding error detection circuit 44 which detects when the calculation result of the error calculation circuit 22 is odd and positive and outputs data "1".
Are combined. The output side of the rounding error detection circuit 44 is coupled to the input side of the horizontal direction addition circuit 16 via a rounding error delay circuit 50 whose delay amount is set to be the same as the delay amount of the 1-dot delay circuit 30. It is connected to the other input side of the overflow processing circuit 42.

Next, the operation of the above embodiment will be described with reference to FIGS.
Will be described together. For convenience of explanation, the original pixel signal is set to 8 bits (n = 8, 256 gradations), the display capability of the PDP is set to 5 bits (m = 5, 32 gradations), and the upper 5 bits are obtained by 8-bit processing.
Bits shall be output. Further, in FIG. 1, data of respective main parts other than "input" to the video signal input terminal 12 and "spread output K" from the overflow processing circuit 42 are shown in FIG. (I is excluded), and the error weight output signals separated by one line are the same (A = C). If the "input" data to the video signal input terminal 12 is always "01" (the numerical value represents an 8-bit hexadecimal number, the same applies hereinafter),
A to J and “spread output K” corresponding to the number of clocks are
As shown in FIG. The details will be described below.

(A) When the number of clocks is "1", since the data A, C and D input to the vertical direction addition circuit 14 and the horizontal direction addition circuit 16 are all "00", the vertical direction addition circuit 14 and the horizontal direction The data B and E output from the adder circuit 16 are both “01”. The threshold selection circuit 24 is configured to output “00” when the input data is “00” to “07” and output “08” when the input data is “08”. When it is "01", the output data F is "00".

The coefficient circuit 26 includes a threshold selection circuit 24.
Since the data F output from is multiplied by "-1" and output to the error calculation circuit 22, the error calculation circuit 22 outputs (E-
F) is calculated, and the output data G which is the calculation result is "01". Therefore, the output data H of the weighting circuit 28 becomes "00", and the data C obtained by delaying this data H by 1 dot by the 1-dot delay circuit 30 is input to the horizontal addition circuit 16 as the data of the clock frequency "2". To do. Since A = C, A of clock frequency “2” is also “00”
Becomes

The rounding error detection circuit 44 includes an error calculation circuit 2
The output data J is "01" when G is "01" because it is configured to detect when the operation result G of 2 is odd and positive and to output the data "1". Data D obtained by delaying this data J by one dot in the rounding error delay circuit 50 is input to the horizontal direction addition circuit 16 as data of the number of clocks “2”.

(B) As described above, when the number of clocks is "2", the data H when the number of clocks is "1" is the data A and C, and the data J when the number of clocks is "1" is the data D. . Therefore, when the number of clocks is "2", the data of the number of clocks "1" changes as follows. The data D changes from "00" to "01", and with this,
The data E, G, and K change from "01" to "02", and the data H changes from "00" to "01". Further, since the data G has changed from "01" to an even number "02", the output data J of the rounding error detection circuit 44 changes from "01" to "00". Other data remains unchanged.
Further, in the same manner as in the case of (a), the data H and J are delayed by one dot by the delay circuits 30 and 50, and the data C and
D is input to the horizontal direction addition circuit 16 as data of the number of clocks "3". Also, from the precondition, A = C.

(C) Therefore, when the number of clocks is "3", the data of the number of clocks "2" changes as follows.
While the data D changes from "01" to "00",
The data A and C change from “00” to “01”, the data B changes from “01” to “02”, and the data E, G, and K change from “02” to “03”. To do. Further, since the data G changes from "02" to an odd number "03", the output data J of the rounding error detection circuit 44 is "0".
It changes from "0" to "01". Other data remains unchanged.

(D) The same operation is performed thereafter, and when the number of clocks is "7", the data of the number of clocks "6" changes as follows. The data D changes from “01” to “00”, the data A and C change from “02” to “03”, and the data B changes from “03” to “04” accordingly. E, G, and K change from "06" to "07". Also, the data G is from "06" to an odd number "07".
Therefore, the output data J of the rounding error detection circuit 44 changes from "00" to "01". Other data remains unchanged.

(E) Next, when the number of clocks is "8", the data of the number of clocks "7" changes as follows.
The data D changes from "00" to "01", and accordingly, the data E and K change from "07" to "08".
Since the bit conversion circuit 18 bit-converts the data K from 8 bits to 5 bits, when the data K becomes "08" and is bit-converted by the bit conversion circuit 18 and supplied to the video signal output terminal 20, The PDP coupled to the video signal output terminal 20 lights dots corresponding to LSB to display pseudo halftone.

When the data E changes from "07" to "08", the output data F of the threshold selection circuit 24 changes from "00" up to then "08", and the output data G accordingly. Changes from "07" to "00", the output data H,
J is "03", "01" to "00", "0"
Changes to 0 ". The output data H and J of "00" are delayed by 1 dot by the delay circuits 30 and 50, and the data "0" is output.
The output data A, C, and D when "0" is the next clock frequency "9".

(F) Therefore, when the number of clocks is "9", the data of the number of clocks "8" changes as follows.
While the data D changes from "01" to "00",
The data A and C change from "03" to "00", the data B changes from "04" to "01", and the data E, G and K change to "08", "00", "08"
To "01", "01", "01". Also,
Since the data E has changed from "08" to "01",
The output data F of the threshold selection circuit 24 changes from "08" to "0".
Changes to 0 ". Further, since the data G changes from "00" to an odd number "01", the output data J of the rounding error detection circuit 44 changes from "00" to "01". Other data remains unchanged.

As described above, the data A to K when the number of clocks is "9" is the data A when the number of clocks is "1".
~ Same as K. Similarly, the number of clocks "1"
The data AK in the case of 0 "," 11 ", ... Becomes the same as the data AK in the case of the number of clocks" 2 "," 3 ",. Therefore, the PDP coupled to the video signal output terminal 20 has the LSB at a rate of once every eight clocks.
The dot corresponding to is turned on to display the pseudo halftone.

On the other hand, in the circuit 10 of the conventional example shown in FIG. 4 which does not include the rounding error detection circuit 44 and the rounding error delay circuit 50, if the input data is always "01", the output data from the error calculation circuit 22 is output. "01" is the load circuit 2
The data A and C input to the vertical direction adder circuit 14 and the horizontal direction adder circuit 16 are always "00" by weighting 1/2 by the 1-bit shift of 8. Therefore, even if the number of clocks increases (even when the number of clocks reaches 8), the data E which is the spread output signal is always "01", and the bit conversion circuit 18
Pseudo-halftone is not displayed on the 5-bit input PDP coupled via the video signal output terminal 20.

Further, the luminance characteristic of the embodiment of FIG. 1 is as shown by the solid line R of FIG. 3, and a finer image can be obtained as compared with the dotted line S showing the luminance characteristic of the conventional example of FIG. That is, the luminance characteristic line R of the embodiment of the present invention has the luminance level linearly changing in proportion to the input signal level, whereas the luminance characteristic line S of the conventional example has the input signal levels “00” and “00”. "01" has the same brightness level and the input signal level is "0".
Even after 2 ”, the brightness level is lower than the brightness characteristic line R. FIG.
, The input signal level is the video signal input terminal 1 of FIG.
2 represents the signal level input to the video signal 2, and the brightness level represents the brightness level of the PDP connected to the video signal output terminal 20 of FIG.

In the above embodiment, the weight circuits for the horizontal direction and the vertical direction are shared by the weight circuits whose weighting amount is 1/2, but the present invention is not limited to this. For example, the weight circuits for the horizontal direction and the vertical direction may be separately formed by the weight circuits having the weighting amount of 1/2, and the weighting amount of each weighting circuit may be the weighting amount other than 1/2. (For example, one may be 1/4 and the other may be 3/4).

In the above-described embodiment, the adder circuit is formed by the vertical adder circuit and the horizontal adder circuit, and the delay circuits corresponding to the adder circuit are the 1 line delay circuit as an example of the h line delay circuit and the d dot delay circuit. However, the present invention is not limited to this. For example, the adder circuit is formed by a vertical adder circuit and a horizontal adder circuit, and the delay circuit is formed by an h line delay circuit in which h is not 1 and a d dot delay circuit in which d is not 1, and this h line delay circuit is used. H from the original pixel A (i, j)
The reproduction error E (i, j−h) generated in the past only for the line is supplied to the vertical direction addition circuit, and the original pixel A is supplied by the d dot delay circuit.
Reproduction error E that occurred in the past by d dots from (i, j)
(Id, j) may be supplied to the horizontal addition circuit.

Alternatively, the addition circuit is a diagonal addition circuit,
Any one of the vertical direction adder circuit and the horizontal direction adder circuit, any two adder circuits, or all adder circuits are formed, and the delay circuit is formed by one corresponding delay circuit (for example, an oblique direction adder circuit). Corresponding to (p line +
q dot) delay circuit), and two corresponding delay circuits (for example, a diagonal addition circuit and a horizontal addition circuit (p
(Line + q dot) delay circuit and d dot delay circuit) or three corresponding delay circuits ((p line + q dot) delay circuit, h line delay circuit and d dot delay circuit) and one corresponding weight circuit It may be formed by two or three load circuits. This (p line + q dot) delay circuit uses p lines, q lines from the original pixel A (i, j).
Reproduction error E (i-q, j-p) that occurred in the past by dots
Represents a circuit for supplying the signal to the diagonal direction addition circuit.

In the above embodiment, the case where the display panel is a PDP has been described. However, the present invention is not limited to this, and the present invention can be applied to the case of a display panel other than PDP (for example, LCDP (liquid crystal display panel)). .

[0034]

According to the present invention, a rounding error detection circuit and a rounding error delay circuit are provided in the error diffusion processing circuit, and when the rounding error detection circuit detects that the operation result of the error operation circuit is odd and positive, the data "1" is detected. Is added to the addition circuit via the rounding error delay circuit, so when the input data is "01", the rounding error detection circuit outputs data "1" and the addition circuit adds it to the input data. Is "00", data "1" is not output from the rounding error detection circuit. Therefore, "01" and "00" of the input data can be visually recognized on the display panel, the calculation accuracy is improved, and the display panel (for example, PD
In P), a high definition image can be displayed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an error diffusion processing circuit according to the present invention.

FIG. 2 is an explanatory diagram showing data of each part at each clock frequency when the data input to the video signal input terminal of FIG. 1 is always “01”.

FIG. 3 is a luminance characteristic diagram comparing the present invention with a conventional example.

FIG. 4 is a block diagram of a conventional error diffusion processing circuit.

[Explanation of symbols]

10, 40 ... Error diffusion processing circuit, 12 ... Video signal input terminal, 14 ... Vertical addition circuit, 16 ... Horizontal addition circuit, 18 ... Bit conversion circuit, 20 ... Video signal output terminal, 22 ... Error calculation circuit, 24 ... Threshold selection circuit, 2
6 ... Coefficient circuit, 28 ... Weighting circuit, 30 ... 1 dot delay circuit, 32 ... 1 line delay circuit, 42 ... Overflow processing circuit, 44 ... Rounding error detection circuit, 50 ... Rounding error delay circuit.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical location H04N 5/66 H04N 5/66 A (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Within Fujitsu General Co., Ltd. (72) Inventor Masayuki Kobayashi 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Inside General Fujitsu Limited (72) Inventor Hayato Denda 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Within Fujitsu General Co., Ltd.

Claims (5)

[Claims] 1. A reproduction error is added to a digitized input video signal by an adder circuit to obtain a diffused output signal, and the diffused output signal is converted into a signal having less bits than the input bits and output to a display panel. At the same time, the difference between the diffused output signal and the threshold value selected for the display panel is calculated by an error calculation circuit, weighted by a weighting circuit, delayed by a delay circuit, and output as a reproduction error to the addition circuit. In the error diffusion processing circuit described above, a rounding error detection circuit that detects when the operation result of the error operation circuit is odd and positive and outputs data “1”, and output data of this rounding error detection circuit is delayed by the delay circuit. An error diffusion processing circuit, comprising: a rounding error delay circuit that delays the same amount as the amount and outputs the added data to the adding circuit. 2. An adder circuit includes a vertical direction adder circuit for adding a reproduction error in a vertical direction and a horizontal direction adder circuit for adding a reproduction error in a horizontal direction, and a delay circuit calculates an operation value of an error operation circuit. From an h line delay circuit that delays the h line and outputs it as a reproduction error to the vertical direction addition circuit, and a d dot delay circuit that delays the calculation value of the error calculation circuit by d dots and outputs it as a reproduction error to the horizontal direction addition circuit. The rounding error delay circuit delays the output data of the rounding error detection circuit by the same amount as the delay amount of one of the h line delay circuit and the d dot delay circuit, and the vertical direction addition circuit and the horizontal direction. The error diffusion processing circuit according to claim 1, wherein the error diffusion processing circuit outputs the output data to an adding circuit corresponding to the one delay circuit of the adding circuits. 3. The error diffusion processing according to claim 2, wherein the delay amount of the h line delay circuit is one line, the delay amount of the d dot delay circuit is one dot, and the weighting amount of the weight circuit is ½. circuit. 4. The error diffusion processing circuit according to claim 3, wherein the weight circuit is used for both vertical and horizontal directions. 5. The addition circuit includes an oblique direction addition circuit for adding reproduction errors in an oblique direction, a vertical direction addition circuit for adding reproduction errors in a vertical direction, and a horizontal direction addition circuit for adding reproduction errors in a horizontal direction. The delay circuit delays the operation value of the error operation circuit (p line + q dots) and outputs it as a reproduction error to the diagonal direction addition circuit (p line + q dots), and the operation value of the error operation circuit. And a h-line delay circuit for delaying the output value to the vertical addition circuit as a reproduction error, and a d-dot delay circuit for delaying the calculated value of the error calculation circuit by d dots and outputting it as a reproduction error to the horizontal addition circuit. The rounding error delay circuit outputs the output data of the rounding error detection circuit from the (p line + q dot) delay circuit, the h line delay circuit, and the d dot delay circuit. The delay amount is delayed by the same amount as the delay amount of any one delay circuit and output as output data to the adder circuit corresponding to the one delay circuit of the diagonal direction adder circuit, the vertical direction adder circuit, and the horizontal direction adder circuit. The error diffusion processing circuit according to claim 1, wherein