JPH0990902A - Pseudo halftone processing circuit - Google Patents

Abstract

(57) Abstract: A circuit scale is reduced by eliminating the need for a line memory for error diffusion. SOLUTION: Lower-order (nm) -bit (for example, 3-bit) data A of an n-bit (for example, 8-bit) video signal
Error diffusion calculation circuit 56 for performing horizontal error diffusion calculation based on the above, and the output value of this error diffusion calculation circuit 56 is added to the upper m bits (eg, 5 bits) of data B of the video signal and output to the display panel. The first addition circuit 52 is configured to calculate δ = DS by the calculation control circuit 64 of the error diffusion calculation circuit 56, and when the calculation value δ becomes positive (≧ 0), the first addition circuit A carry signal for adding "1" to the least significant bit of the data B is supplied to 52 to perform error diffusion only in the horizontal direction. Then, the calculation initial value setting circuit 70 sets the calculation initial value of the error diffusion calculation circuit 56 by changing it for each line, thereby eliminating the directionality of the diffusion pattern and eliminating the need for a memory element (line memory) in the line direction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pseudo halftone processing circuit for displaying a pseudo halftone image on a display panel such as a PDP (plasma display panel) or LCDP (liquid crystal display panel). More specifically, a pseudo halftone level is generated by signal processing, and the number of gradations (for example, 5 bits, 32 gradations) that is smaller than the number of gradations (for example, 8 bits, 256 gradations) of the input video signal is displayed. The present invention relates to a pseudo-halftone processing circuit for displaying a pseudo-halftone image on a display device such as a PDP or an LCDP which can only be obtained.

[0002]

2. Description of the Related Art Recently, as a thin and lightweight display device, P
Attention is paid to DP display devices. The drive system of this PDP display device is completely different from the conventional CRT drive system and is a direct drive system using a digitized input video signal. Therefore, the brightness gradation emitted from the panel surface is determined by the number of bits of the signal to be handled. PDPs are divided into two types, AC type and DC type, which have different basic characteristics. Among these, AC type PDPs have sufficient characteristics in brightness and life, but in gradation display, they are prototype level. However, there was only a report of displaying up to 64 gradations.
Recently, a future 256-gradation method based on the address / display separation type driving method (ADS subfield method) has been proposed.

This is because one frame has a relative luminance ratio of 1,
It is composed of 8 sub-fields of 2, 4, 8, 16, 32, 64, and 128, and the combination of the brightness of 8 screens is 25.
6-gradation display is performed. Each subfield is composed of an address period for writing refreshed data for one screen and a sustain period for determining the brightness level of the subfield. In the address period, wall charges are initially formed in each pixel at the same time on the entire screen, and then sustain pulses are applied to the entire screen for display.
The brightness of the subfield is proportional to the number of sustain pulses and is set to a predetermined brightness. In this way, 256 gradation display is realized.

In the AC driving method as described above, as the number of gradations is increased, the number of bits in the address period as a preparation period for lighting and emitting the panel is increased within one frame period. The period is relatively short and the maximum brightness is low. In this way, if the number of bits of the signal to be handled is increased, the image quality is improved, but the light emission luminance is lowered. Conversely, if the number of bits of the signal to be handled is reduced, the light emission luminance is increased, but gradation display is reduced. This causes deterioration of image quality.

Therefore, a PDP (an example of a display panel) having a display level of m bits (m≤n-1) is obtained by performing pseudo halftone processing on an input video signal of n bits.
Has proposed a display device for displaying a pseudo halftone image. The circuit for performing this pseudo halftone process reproduces a grayscale image by error diffusion, and has been conventionally configured as shown in FIG.

The pseudo halftone processing circuit shown in FIG. 7 includes a first error diffusion circuit 10 for performing error diffusion within a frame on sequentially input n-bit video signals, and a circuit added as necessary. Therefore, the second error diffusion circuit 12 includes a second error diffusion circuit 12 that performs diffusion in the frame direction on the pseudo halftone output output from the first error diffusion circuit.
The m-bit pseudo-halftone output signal output from the PDP is output to the PDP to display a pseudo-halftone image.

The first error diffusion circuit 10 includes a diagonal addition circuit 14, a vertical addition circuit 16 and a horizontal addition circuit 18 which are inserted in series between the input and the output and add a reproduction error to the input video signal to diffuse it. A bit conversion circuit 20 for converting the diffused output signal of the horizontal direction addition circuit 18 into an m-bit signal and outputting the m-bit signal, an error detection circuit 22 coupled to the output side of the horizontal direction addition circuit 18, and this error detection circuit. The error load signal of 22 is delayed by a predetermined amount, and the corresponding adder circuit 1
It is composed of an oblique delay circuit 24, a vertical delay circuit 26, and a horizontal delay circuit 28, which are output to 4, 16, and 18 as reproduction errors.

The error detection circuit 22 has a ROM 30 in which data of corrected luminance levels for luminance gradation correction is set and stored in advance.
And a subtraction circuit 32 that outputs the error detection signal by calculating the difference between the corrected luminance level set in the ROM 30 and the diffusion output signal output from the horizontal direction addition circuit 18, and the error detection output from the subtraction circuit 32. Delay circuits 24, 26, 2 corresponding to error weighted signals obtained by weighting signals with a predetermined weight
It is composed of load circuits 34, 36, 38 for outputting to 8.

The second error diffusion circuit 12 outputs the inter-frame error data to generate an inter-frame error data generation circuit 40.
And a frame addition circuit 42 that is inserted between the input and output and that adds the inter-frame error data output from the inter-frame error data generation circuit 40 to the pseudo halftone output signal output from the first error diffusion circuit 10. There is.

[0010]

However, in the pseudo halftone processing circuit shown in FIG. 7, the first error diffusion circuit 10 has an oblique delay circuit 24 for performing error diffusion in the oblique direction and the vertical direction. Since the vertical delay 26 circuit is provided, a line memory for delaying the predetermined number of lines is required, which causes a problem that the circuit scale becomes large. Further, the pseudo halftone processing circuit shown in FIG. 7 requires the addition of the second error diffusion circuit 12 for performing the diffusion in the frame direction, which causes a problem that the circuit scale becomes larger. Further, the pseudo halftone processing circuit shown in FIG. 7 has a problem that a unique pattern is displayed due to error diffusion.

The present invention has been made in view of the above problems, and an object of the present invention is to reduce the circuit scale by eliminating the need for a line memory for error diffusion. It is an object of the present invention to reduce the circuit scale by performing diffusion in the frame direction with a simple configuration as needed.
Furthermore, if necessary, just add a simple circuit,
The purpose is to prevent a unique pattern due to error diffusion from being displayed.

[0012]

According to the present invention, the lower (n) of n-bit (n is a positive integer) video signal sequentially input is selected.
-M) An error diffusion calculation circuit for performing an error diffusion calculation in the horizontal direction based on bit (m≤n-1) data A, and an output value of the error diffusion calculation circuit is the upper m of the n-bit video signal. The error diffusion arithmetic circuit includes a second adder circuit that receives the data A as one input, and an output data C of the second adder circuit. 1-dot delay circuit for delaying 1-dot, a switching circuit for supplying output data D of the 1-dot delay circuit to the other input side of the second addition circuit via one switching side, and an output of the 1-dot delay circuit The difference δ (= DS) between the data D and the preset threshold S is calculated, and when the calculated value δ becomes positive (≧ 0), the least significant bit of the data B is stored in the first addition circuit. And to supply a carry signal to add "1" to And an arithmetic control circuit for switching the switching circuit to the other switching side to supply the arithmetic value δ to the other input side of the second adding circuit. The arithmetic initial value of the error diffusion arithmetic circuit is displayed on the display panel. A calculation initial value setting circuit is provided that is set differently for each line.

One switching side of the second addition circuit, the one-dot delay circuit and the switching circuit of the error diffusion calculation circuit constitutes an integration loop circuit, and the second addition circuit in the integration loop circuit sequentially inputs n bits ( For example, the data A of the lower (n−m) bits (for example, 3 bits when m = 5) of the video signal of n = 8 is integrated. When this integrated value increases and the output data D of the 1-dot delay circuit of the integration loop circuit becomes equal to or greater than a preset threshold value S (for example, 8), the control circuit switches the switching side of the switching circuit from one to the other. The calculated value δ (= D−S) is supplied to the other input side of the second addition circuit via the other switching side, and the integrated value in the integration loop circuit decreases by the threshold value S. The threshold value S is, for example, 2 3 8 when the data A is the lower 3 bits, or 2 4 16 when the data A is the lower 4 bits.
Is set to

When the output data D exceeds the preset threshold S as described above, the carry signal (carry signal) is supplied to the first adder circuit, and the data of the upper m bits of the n-bit video signal is supplied. A pseudo halftone level "1" is added to the least significant bit of B. Further, since the calculation initial value setting circuit changes the calculation initial value of the error diffusion calculation circuit for each line, the pseudo halftone level "1" is displayed on the display panel.
The position from the starting point on the line to which is added changes from line to line, and vertical lines do not appear on the screen.

When a calculation initial value setting circuit for setting the calculation initial value of the error diffusion calculation circuit by changing it for each line and frame of the display panel is provided, the calculation initial value setting circuit causes the calculation of the initial value of the error diffusion calculation circuit. Since the value is changed not only for each line but also for each frame, the position on the display panel from the start point on the line to which the pseudo halftone level "1" is added changes for each line and also for each frame. , Vertical lines do not appear on the screen, and interframe diffusion is performed.

A pattern removal control signal generation circuit for outputting a pattern removal control signal and a pattern removal control signal addition circuit for injecting the pattern removal control signal output from the pattern removal control signal generation circuit into the error diffusion calculation circuit are provided. In this case, the pattern by the error diffusion process is removed.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An example of an embodiment of the present invention will be described below with reference to FIGS. In FIG. 1, reference numeral 50 denotes an input terminal for inputting an n-bit (for example, 8-bit) video signal, which is coupled to the input terminal 50 to transmit upper m bits (for example, 5 bits) of data B of the video signal. The signal line passes through the 1-dot delay circuit 51 and is coupled to the output terminal 54 which outputs the m-bit pseudo-halftone output signal via the first adding circuit 52. The signal line coupled to the input terminal 50 and transmitting the data (A) of the lower (n−m) bits (for example, 3 bits) of the video signal is one input side of the second addition circuit 58 in the error diffusion calculation circuit 56. Is bound to.

The error diffusion calculation circuit 56 is constructed as follows. On the output side of the second adding circuit 58,
1-dot delay circuit 6 composed of a flip-flop circuit
0 is coupled, and the output side of the 1-dot delay circuit 60 is coupled to the other input side of the second adder circuit 58 via one switching side of the switching circuit 62 to form an integration loop. On the output side of the 1-dot delay circuit 60,
One input side of the subtraction circuit 66 in the arithmetic control circuit 64 is coupled, and a threshold value S (for example, 8) of lower (nm) bits (for example, 3 bits) is set on the other input side of the subtraction circuit 66. The threshold setting circuit 68 for outputting the
The other switching side of the switching circuit 62 is coupled to the output side of the subtraction circuit 66.

The arithmetic and control circuit 64 includes the subtraction circuit 6
When the calculated value δ (= DS) of 6 becomes positive (≧ 0), the switching circuit 62 is switched to the other switching side and the calculated value δ is input to the other input side of the second adding circuit 58. And a carry signal for adding "1" to the least significant bit of the data B to the first adder circuit 52.

Reference numeral 70 denotes a calculation initial value setting circuit. The calculation initial value setting circuit 70 has an initial value setting ROM 72, a line counter 74 formed of an octal counter for counting horizontal synchronizing signals, and a vertical synchronizing signal. A frame counter 76 formed of a binary counter for counting, and by outputting a predetermined calculation initial value to the 1-dot delay circuit 60 in the error diffusion calculation circuit 56, the calculation initialization of the error diffusion calculation circuit 56 is started. The value is set to be changed for each line and frame of the display panel.

The setting of the calculation initial value by the calculation initial value setting circuit 70 is as shown in FIG. 2, for example. That is, when the number of pseudo gradations is 8 (when the bit difference (nm) is 3 bits) and the threshold value S is 8, the line number of the odd-numbered frame of the display panel. For the first 8 lines of 0, 1, 2, ..., 7, the calculation initial value is set to 7, 1, 2, ..., 0, and for the second and subsequent 8 lines, the calculation initial value is set every 8 lines. From the setting circuit 70, the first calculation initial value (7, 1,
2, ..., 0) are repeatedly output. Line number of even frame of display panel. 0, 1, 2, ..., 7 first 8
For the lines, the calculation initial values are set to 3, 5, 6, ... 4, For the second and subsequent 8 lines, the calculation calculation initial value setting circuit 70 sets the calculation calculation initial values (3, 5) every 8 lines. , 6, ..., 4) are repeatedly output.

These calculation initial values are R for the initial value setting.
It is stored in advance in the OM 72. To select these calculation initial values, for example, various combinations of values from 0 to 7 are given as the calculation initial values, an experiment for displaying a screen of a standard video signal on a display panel is carried out, and the calculation in the diffusion direction is performed. A value corresponding to the best screen with few patterns based on the deviation or the like is selected. Then, these selected calculation initial values are stored in the initial value setting ROM 72 in advance.

Next, the operation of the above embodiment will be described with reference to FIG. For convenience of description, assuming that the video signal input to the input terminal 50 is 8 bits (n = 8, 256 gradations) and the display capability of the display panel (for example, PDP) is 5 bits (m = 5, 32 gradations), it is pseudo. The number of gradations is 8 (n-
m = 3 bits). The threshold value S of the threshold value setting circuit 68 is not limited to this, but is set to 8 which is the same as the pseudo gradation number of 8. Then, in order to make the explanation of the error diffusion easy to understand, the case where the level of the video signals sequentially input is “1” will be described. This corresponds to the case where all pixels are not lit when the pseudo halftone display is not performed.

When a digital video signal of level "1" is input to the input terminal 50, the 3-bit data A sequentially input to the error diffusion calculation circuit 56 is "001" and the first addition circuit via the 1-dot delay circuit 51. The 5-bit data B sequentially input to 52 is “00000”. The calculation initial value set by the calculation initial value setting circuit 70 is a value as shown in FIG. 2, and is supplied to the 1-dot delay circuit 60 of the integration loop.

(A) First, the line No. of the first frame.
The 0th pixel of the 0 horizontal line in the horizontal direction will be described. This first frame, line No. Initial calculation value of 0 D
s is 7 (= “0111”) as shown in FIG.

(A) The data B of the 0th pixel in the horizontal direction is 1
When input to the dot delay circuit 51, the data D output from the 1-dot delay circuit 60 is the calculation initial value Ds.
Therefore, the calculation by the calculation control circuit 64 is as follows: δ = DS−Ds−S = “0111” − “1000” <0.

(B) When the calculated value δ is negative, the switching signal is not output from the arithmetic control circuit 64 to the switching circuit 62, so that the movable piece of the switching circuit 62 is at the upper side as shown by the solid line in FIG. It is connected to the switching side of. Therefore, the addition by the second addition circuit 58 becomes C = A + Ds = “001” + “111” = “1000” (decimal 8), and after this data C is delayed by 1 dot by the 1-dot delay circuit 60. , Data D is supplied to the arithmetic control circuit 64.

(C) The data B of the 0th pixel in the horizontal direction is 1
The dot delay circuit 51 delays one dot for the first addition circuit 5
When inputting to 2, the data D output from the 1-dot delay circuit 60 is “1000” due to (b) above, so the operation by the operation control circuit 64 is as follows: δ = DS− “ 1000 "-" 1000 "= 0.

(D) When the calculated value δ is positive (≧ 0),
A switching signal is output from the arithmetic control circuit 64 to the switching circuit 62, and the movable piece of the switching circuit 62 is switched to the lower switching side as shown by the chain line in FIG. Therefore, the calculation by the second addition circuit 58 is C = A + δ = “001” + “000” = “001”, and after this data C is delayed by 1 dot by the 1-dot delay circuit 60, calculation control is performed as data D. It is supplied to the circuit 64. At this time, the data B of the next horizontal 1st pixel
Is also being input to the first adder circuit 52.

(E) Furthermore, when the calculated value δ is positive,
A carry signal is output from the arithmetic control circuit 64 to the first adder circuit 52, and the first adder circuit 52 adds "1" to the least significant bit of the input data B. That is, the addition by the first adding circuit 52 is B + “00001” = “00000” + “00001” = “00001”, and this data is supplied to the display panel from the output terminal 54 as a pseudo-halftone output signal. As shown in FIG. 3, the 0th pixel in the horizontal direction of the display panel is turned on by error diffusion.

(B) Next, the line N of the first frame
o. The first pixel in the horizontal direction of the 0 horizontal line will be described. (A) The data B of the first pixel in the horizontal direction is the first addition circuit 5
When it is input to 2, the data D output from the 1-dot delay circuit 60 is "00" according to (d) of (a) above.
1 ”, the calculation by the calculation control circuit 64 is δ = D−S = DS−“ 0001 ”−“ 1000 ”<0.

(B) When the calculated value δ is negative, the switching signal output from the arithmetic control circuit 64 to the switching circuit 62 disappears, so that the movable piece of the switching circuit 62 is as shown by the solid line in FIG. Return to the upper switching side. Therefore, the addition of the second addition circuit 58 becomes C = A + D = “001” + “001” = “010”, and this data C is delayed by 1 dot in the 1-dot delay circuit 60, and the second horizontal direction is next. Data B of the pixel is
When input to the adder circuit 52, the data D is supplied to the arithmetic control circuit 64.

(C) Further, when the operation value δ is negative, the carry signal is not output from the operation control circuit 64 to the first adding circuit 52, so that the first adding circuit 52 keeps the input data B as it is. The output data is output and supplied as a pseudo-halftone output signal from the output terminal 54 to the display panel. For this reason, as shown in FIG. 0
No. 1 pixel in the horizontal direction does not light up.

(C) Line No. of the first frame As for the pixels from the second to the seventh in the horizontal direction of the horizontal line of 0, the calculation value δ remains negative as in the case of (b), and therefore the switching signal output from the calculation control circuit 64 to the switching circuit 62. , The movable piece of the switching circuit 62 is on the upper switching side shown by the solid line in FIG.
There is also no carry signal output to the adder circuit 52. For this reason,
As shown in FIG. 3, pixels 2 to 7 in the horizontal direction of the display panel do not light up. However, the output data C of the second adding circuit 58 and the output data D of the 1-dot delay circuit 60 are sequentially "00" each time the horizontal pixel number increases by one.
1 ”increase.

(D) Line No. 1 of the first frame. For the 8th pixel in the horizontal direction of the 0 horizontal line, the output data D of the 1-dot delay circuit 60 becomes “1000” (8 in decimal notation), and δ = DS−S = 0. When the calculated value δ becomes positive (≧ 0) in this way, a switching signal is output from the arithmetic control circuit 64 to the switching circuit 62 in the same manner as in the case of (a), and the movable piece of the switching circuit 62 is moved to the position shown in FIG. Is switched to the lower switching side indicated by the chain line, C = A + δ = “001” + “000” = “001”, and this data C is passed through the 1-dot delay circuit 60 to the next horizontal 9th pixel. Is data D related to.

When the operation value δ becomes positive, a carry signal is output from the operation control circuit 64 to the first adding circuit 52, and the first adding circuit 52 outputs "1" to the least significant bit of the input data B.
Add. Therefore, as in the case of (a) above, the first
The added data "00001" by the adder circuit 52 is supplied to the display panel from the output terminal 54 as a pseudo-halftone output signal, and as shown in FIG. 3, the 8th pixel in the horizontal direction of the display panel is turned on by error diffusion.

(E) As described in the above (A) to (D), the line No. of the first frame. In the horizontal line of 0, the calculation initial value Ds is 7, and as shown in FIG. 3, with 8 dots (8 pixels) as the period T, horizontal directions 0, 8, 1
No. 6, ... Pixels are lit, and other pixels are not lit.

(F) Similarly, the line No. of the first frame is set. In the horizontal line of 1, the calculation initial value Ds is 1
Then, as shown in FIG. 3, at the period T of 8 dots (8 pixels), the pixels of the horizontal direction 6, 14, 22, ...
Diffusion display is performed in which other pixels are not lit.

(G) Similarly, the line No. of the first frame. In the horizontal lines of 2, 3, ..., 7, the calculation initial value Ds is 2, 4, ..., 0, and as shown in FIG. Ds
One dot corresponding to is turned on and the other pixels are not turned on, and diffusion display is performed.

(H) Line No. 1 of the first frame. 8 to line No. In the horizontal lines up to 15, line No. 15 shown in FIG. 0 to line No. Diffusion display similar to the diffusion patterns up to 7 is made (not shown), and this is repeated thereafter.

(I) Line No. of the second frame 0 to line No. In the horizontal lines up to 7, the cycle T corresponds to the calculation initial values Ds 3, 5, ..., 4 shown in FIG.
The line No. of the first frame shown in FIG. 3 is different except that the position of one dot that lights up among (8 dots) is different. 0
To line no. Diffusion display similar to the diffusion patterns up to 7 is performed (not shown). Line N of the second frame
o. Similar diffusion display is performed on the horizontal lines after 8 (not shown).

(D) The diffused display of the horizontal lines of the odd frames below the third frame is the same as the diffused display of the first frame, and the diffuse display of the horizontal lines of the even frames below the fourth frame is the diffused display of the second frame. It is similar to the diffuse display.

In the above embodiment, the case where the number n of bits of the input video signal is 8 and the displayable bit m of the PDP is 5 has been described, but the present invention is not limited to this, and m,
It can be used as long as both n are positive integers and satisfy the condition of m ≦ n−1.

In the above embodiment, the calculation initial value setting circuit sets the calculation initial value of the error diffusion calculation circuit to eight lines of the display panel, and the calculation initial value is switched line by line in this set. The directionality of the diffusion pattern in the vertical direction is erased, and the odd-numbered frame and the even-numbered frame are set as one set, and the operation initial value is switched for each frame in this set to eliminate the directionality between the frames of the diffusion pattern. The present invention is not limited to this, and the calculation initial value of the error diffusion calculation circuit may be switched line by line and frame by frame to eliminate the vertical directionality of the diffusion pattern and the interframe directionality. Alternatively, the calculation initial value of the error diffusion calculation circuit may be switched line by line to eliminate the vertical directivity of the diffusion pattern.

In the above embodiment, the case where the positive circuit for removing the pseudo pattern due to the error diffusion is not provided is described, but the present invention is not limited to this, and the pseudo pattern due to the error diffusion is removed. It is also possible to use a circuit to which a circuit for adding is added. 4 to 6 show an example thereof.

FIG. 4 shows an 8-bit video signal signal line coupled to the input terminal 50, which is inserted into a signal line before being divided into a 5-bit signal line and a 3-bit signal line. When a pattern removal control signal addition circuit 80 and a pattern removal control signal generation circuit 82 for outputting a pattern removal control signal are added to the addition circuit 80, the pattern removal control signal generation circuit 82 is, for example, at level "1". And a noise generation circuit that randomly outputs a signal of level "0".

In FIG. 5, the pattern removal control signal adding circuit 80a is inserted between the second adding circuit 58 and the switching circuit 62 in the error diffusion calculating circuit 56 of FIG. 1 and the pattern is added to the adding circuit 80a. This is a case where the pattern removal control signal generation circuit 82a for outputting the removal control signal is provided and the error diffusion calculation circuit 56a is formed to which the function of pattern removal by error diffusion is added.

FIG. 6 shows a calculation initial value setting circuit 7
A pattern removal control signal addition circuit 80b inserted in a line for supplying an operation initial value from 0 to the error diffusion calculation circuit, and a pattern removal control signal generation circuit 82b outputting a pattern removal control signal to this addition circuit 80b are added. This is the case.

In the above embodiment, the display panel is the PDP.
Although the case has been described, the present invention is not limited to this and can be applied to the case of a display panel (for example, LCDP) other than the PDP.

[0050]

The pseudo halftone processing circuit of the present invention according to claim 1 is the data of the lower (nm) bits (for example, 5 bits) of the sequentially input n-bit (for example, 8 bits) video signal. An error diffusion calculation circuit for performing an error diffusion calculation in the horizontal direction based on A, and an output value of this error diffusion calculation circuit is used as data B of upper m bits of an n-bit video signal.
And a first addition circuit for outputting to the display panel. The error diffusion calculation circuit is composed of a second addition circuit, a 1-dot delay circuit, a switching circuit and a calculation control circuit to perform error diffusion only in the horizontal direction. , A calculation initial value setting circuit that sets the calculation initial value of the error diffusion calculation circuit for each line of the display panel is provided, and the calculation initial value is changed for each line to erase the directionality of the diffusion pattern and produce a smooth reproduced image. It is characterized in that it is obtained.

As described above, since the error diffusion in the horizontal, vertical and diagonal directions can be performed without using the line memory, the error diffusion in the diagonal and vertical directions can be performed like the pseudo halftone processing circuit of the conventional example. It is not necessary to provide a diagonal delay circuit or a vertical delay circuit for performing the operation, a storage element (line memory) in the line direction can be eliminated, and the circuit scale can be reduced.

According to a second aspect of the pseudo-halftone processing circuit of the present invention, in the pseudo-halftone processing circuit according to the first aspect, the calculation initial value of the error diffusion calculation circuit is set not only for each line of the display panel but also for each frame. Since the calculation initial value setting circuit for changing the setting is also provided, a special circuit such as the conventional example (second error diffusion circuit 1 in FIG. 7) is used for inter-frame processing.
It is not necessary to provide 2), and the circuit scale can be further reduced.

A pseudo halftone processing circuit according to a third aspect of the present invention is generated by error diffusion by simply adding an adding circuit and a pattern removal control signal generating circuit (for example, a noise generating circuit) in the first or second aspect of the invention. The pattern can be removed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an embodiment of a pseudo halftone processing circuit according to the present invention.

FIG. 2 is an explanatory diagram showing an example of setting a calculation initial value in a calculation initial value setting circuit of FIG.

FIG. 3 is an explanatory view showing the operation of FIG.

FIG. 4 is a block diagram showing a first example in which a circuit for removing a pattern due to error diffusion is added to FIG.

FIG. 5 is a block diagram showing a second example in which a circuit for removing a pattern due to error diffusion is added to FIG.

FIG. 6 is a block diagram showing a third example in which a circuit for removing a pattern due to error diffusion is added to FIG.

FIG. 7 is a block diagram showing an example of a conventional pseudo halftone processing circuit.

[Explanation of symbols]

50 ... Video signal input terminal, 51 ... 1-dot delay circuit, 52 ... First addition circuit, 54 ... Output terminal, 56, 5
6a ... Error diffusion calculation circuit, 58 ... Second addition circuit, 60
... 1-dot delay circuit, 62 ... switching circuit, 64 ... arithmetic control circuit, 66 ... subtraction circuit, 68 ... threshold value setting circuit, 7
0 ... Calculation initial value setting circuit, 72 ... ROM for initial value setting,
74 ... Line counter, 76 ... Frame counter, 8
0, 80a, 80b ... Pattern removal control signal adding circuit, 8
2, 82a, 82b ... Pattern removal control signal generation circuit, A,
B, C, D ... Data, Ds ... Initial value of calculation, S ... Threshold set, delta ... Calculation value (= DS).

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Junichi Onodera 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture, Japan Inside Fujitsu General Co., Ltd. (72) Inventor Masayuki Kobayashi 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture, Japan 72) Inventor Hayato Denda 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Inside Fujitsu General Limited (72) Inventor Toru Aida 1116 Suenaga, Takatsu-ku, Kawasaki City, Kanagawa Prefecture Fujitsu General Limited

Claims (3)

[Claims] 1. A lower (n−m) bit (m ≦ n−1) of a sequentially input n-bit (n is a positive integer) video signal.
Error diffusion calculation circuit for performing error diffusion calculation in the horizontal direction based on the data A, and the output value of the error diffusion calculation circuit is the data B of the upper m bits of the n-bit video signal.
To the display panel, and the error diffusion calculation circuit outputs a second addition circuit that receives the data A as one input and output data C of the second addition circuit to 1 1 dot delay circuit for dot delay and this 1
A switching circuit that supplies the output data D of the dot delay circuit to the other input side of the second addition circuit via one switching side, the output data D of the one-dot delay circuit, and a preset threshold value S. A digit for calculating the difference δ (= DS) and adding "1" to the least significant bit of the data B in the first adder circuit when the calculated value δ becomes positive (≧ 0). And a calculation control circuit for supplying the raising signal and switching the switching circuit to the other switching side to supply the calculated value δ to the other input side of the second adding circuit. A pseudo halftone processing circuit comprising a calculation initial value setting circuit for setting the calculation initial value of the circuit by changing it for each line of the display panel. 2. A lower (n−m) bit (m ≦ n−1) of a sequentially input n-bit (n is a positive integer) video signal.
Error diffusion calculation circuit for performing error diffusion calculation in the horizontal direction based on the data A, and the output value of the error diffusion calculation circuit is the data B of the upper m bits of the n-bit video signal.
And an output data C output from the second addition circuit. The first addition circuit outputs the data to the display panel. 1 dot delay circuit for dot delay and this 1
A switching circuit that supplies the output data D of the dot delay circuit to the other input side of the second addition circuit via one switching side, the output data D of the one-dot delay circuit, and a preset threshold value S. A digit for calculating the difference δ (= DS) and adding "1" to the least significant bit of the data B in the first adder circuit when the calculated value δ becomes positive (≧ 0). And a calculation control circuit for supplying the raising signal and switching the switching circuit to the other switching side to supply the calculated value δ to the other input side of the second adding circuit. A pseudo halftone processing circuit, comprising a calculation initial value setting circuit for changing and setting a calculation initial value of the circuit for each line and frame of the display panel. 3. A pattern removal control signal generation circuit for outputting a pattern removal control signal, and a pattern removal control signal addition circuit for injecting the pattern removal control signal output from this pattern removal control signal generation circuit into an error diffusion calculation circuit. The pseudo halftone processing circuit according to claim 1, which is provided.