JPH0964183A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) An object of the present invention is to reduce the number of steps in an air bridge forming process, prevent yield deterioration in response to abnormal patterning of a resist, and configure a wiring electrode having good flatness. SOLUTION: A step of forming a metal film 31 in a planned pier formation area 62 on the main surface of a semiconductor substrate 11, a step of forming a surface protective film 13 on the metal film, and a desired area of the surface protective film. The method includes forming an opening 63 penetrating the metal film, forming a wiring electrode 23 on the surface protection film, and removing the metal film 31 from the surface protection film opening 63 by etching. It is characterized by forming a bridge. The metal film 31 is formed simultaneously with the gate electrode 22 of the field effect transistor. The metal film 31 is characterized by containing at least aluminum.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method of manufacturing a semiconductor device having a bridge pier structure (hereinafter referred to as an air bridge structure) in a wiring electrode.

[0002]

2. Description of the Related Art In recent years, with the digitalization of mobile communications such as cordless telephones and mobile telephones, there has been a demand for a power amplifier which is small in size, low in price, low in distortion, high in efficiency and low in power consumption.
In order to achieve low distortion, high efficiency, and low power consumption, a gallium arsenide / field effect transistor (GaAs / FET) capable of highly efficient linear operation is used as an amplification element. In order to reduce the size and cost, a field effect transistor (hereinafter abbreviated as FET) that is an amplification element,
A monolithic microwave integrated circuit (hereinafter abbreviated as MMIC) in which a matching circuit, a resistance element that is a bias circuit, a capacitor element, and an inductor element are formed on one semiconductor chip is desired.

The inductor element is formed by patterning a metal film which is a wiring electrode directly on the semiconductor substrate or on an insulating film formed on the surface of the semiconductor substrate. This inductor element has frequency characteristics and generally causes self-resonance at a certain frequency or higher, and does not operate as an inductor element.

As a method of increasing the frequency at which self-resonance occurs (hereinafter referred to as the self-resonant frequency), there is a method in which the wiring electrode has an air bridge structure. When the wiring electrode has an air bridge structure, the capacitance of the wiring electrode with respect to the ground is reduced and the self-resonance frequency can be increased, so that a good inductor element can be realized even at high frequencies. In order to reduce the capacitance to ground of the inductor element, it is desirable to form the entire wiring electrode away from the semiconductor substrate, but due to problems in the formation process and structural strength, the so-called air bridge structure in which a bridge pier is partially adopted is widely adopted. Has been done.

As a conventional example according to the present invention, a forming process for forming an air bridge structure in an MMIC using an FET as an active element will be described.

FIGS. 5 to 8 are sectional views showing a process of forming an FET and an air bridge structure inductor element in the order of steps.

First, the insulating film 12 is formed on the main surface of the semiconductor substrate 11.
Are formed (FIG. 5A). This insulating film 12 is a spacer film for lifting off the metal when forming the ohmic electrode and the gate electrode of the FET. As the insulating film 12, SiO ₂ is formed to a thickness of about 500 nm.

Next, an ohmic electrode 21 serving as a source electrode and a drain electrode of the FET is formed (FIG. 5B). The ohmic electrode 21 is formed, for example, by depositing AuGe and Pt to a thickness of about 200 nm and 30 nm, respectively.

Next, the gate electrode 22 of the FET is formed (FIG. 5C). The gate electrode 22 is made of, for example, 50 Al.
It is formed by vapor deposition with a thickness of about 0 nm.

Next, the surface protection film 13 is formed on the entire surface of the semiconductor substrate (FIG. 6A). The surface protection film 13 is formed to protect the semiconductor surface and the electrode surface. Normal,
The surface protection film 13 is formed of SiN with a thickness of about 200 nm.

Next, an opening is provided in a predetermined area of the surface protective film 13 to form a contact hole 64 (FIG. 6 (b)).
The contact hole 64 is formed to connect the ohmic electrode 21 and the wiring electrode.

Next, the wiring electrode 24 is formed. The wiring electrode 24 is made of Ti, Pt, and Au and has a thickness of 300 nm,
It is formed by vapor deposition with a thickness of about 100 nm and 1500 nm. At this time, the wiring electrode 24 is not formed in the air bridge formation planned area 65 (FIG. 6C).

Next, a resist 43 is applied to the entire surface (FIG. 6 (d)).

Next, the resist 43 on the wiring electrode 24 is removed to expose the wiring electrode 24 (FIG. 7A).

Next, a metal film 32 for electrolytic plating is formed on the entire surface (FIG. 7B). The metal film 32 for electrolytic plating is Au
Is formed by vapor deposition to a thickness of about 100 nm.

Next, a resist 44 is applied (see FIG. 7).
(C)).

Next, the resist 44 on the planned area for forming the wiring electrode is removed. Next, the wiring electrode 25 is formed. For this formation, an electrolytic plating method using the metal film 32 for electrolytic plating as an electrode is used to form Au to a thickness of about 2 μm (FIG. 7).
(D)).

Next, the resist 44 is removed, and the metal film 32 for electrolytic plating other than the wiring electrode portion is removed by etching. Next, the resist 43 is removed (FIG. 8). The portion from which the resist 43 has been removed by the above process is the air layer 51.
Next, an air bridge structure is formed.

[0019]

Since the conventional process for forming the air bridge structure uses the three-layer structure of the resist 43, the electrolytic plating metal film 32, and the resist 44, the number of steps increases.

Further, when an abnormal patterning of the resist occurs, it is difficult to remove the resist and perform the patterning again, which causes a decrease in yield.

Further, the formed air bridge portion is likely to have irregularities, resulting in poor flatness. Therefore, when the semiconductor substrate is attached to the supporting substrate in the back surface processing step of polishing and thinning the semiconductor substrate, stress is applied to the convex portion of the air bridge structure, the air bridge structure is deformed, and it approaches or contacts the surface protective film. , The ground capacity becomes large. Therefore, the high frequency characteristics of the inductance element are deteriorated, which causes the yield to be reduced.

[0022]

In a method of manufacturing a semiconductor device in which at least a field effect transistor and a wiring electrode having an air bridge structure are formed on a main surface of a semiconductor substrate, an air bridge is formed on the main surface of the semiconductor substrate. Forming a metal film in a predetermined area, forming a surface protection film on the metal film, forming an opening penetrating the metal film in a desired region of the surface protection film, and the surface protection The method is characterized by including a step of forming a wiring electrode on the film and a step of etching and removing the metal film from the opening of the surface protective film.

Further, it is characterized in that the metal film is formed at the same time as the gate electrode of the field effect transistor.

Further, the metal film contains at least aluminum.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION In the method for manufacturing a semiconductor device according to the present invention, after forming the wiring electrode, the metal layer immediately below the wiring electrode is removed by etching to form an air bridge structure, so that the wiring with good flatness is formed. Electrodes can be formed. Further, the steps other than the etching of the metal layer can be performed at the same time as the normal gate step of the FET, so the steps can be simplified. Further, since the resist is not used as a base for forming the air bridge, it is possible to prevent the yield reduction that occurs when the resist patterning is abnormal.

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

1 (a) to 1 (d), 2 (b) and 2 (c), 3 (b) and 3 (c), and FIG. a), FIG. 3 (a) and FIG. 4 are plan views for further supplementing and explaining the cross-sectional view.

First, the insulating film 12 is formed on the main surface of the semiconductor substrate 11.
Is formed (FIG. 1A). This insulating film 12 is a spacer film for lifting off the metal when forming the ohmic electrode and the gate electrode of the FET. As the insulating film 12, SiO ₂ is formed to a thickness of about 500 nm.

Next, the ohmic electrodes 21 which will be the source and drain electrodes of the FET are formed (FIG. 1B). The ohmic electrode 21 is formed, for example, by depositing AuGe and Pt to a thickness of about 200 nm and 30 nm, respectively.

Next, a resist 41 is applied on the entire surface (see FIG. 1).
(C)).

Next, the air bridge formation planned region and FET
41 and insulating film 1 in the gate electrode formation planned region of
2 is removed (FIG. 1 (d)). The width of the portion to be removed, that is, the insulating film opening portion 61 is made wider than the width of the wiring electrode formation planned area 62 as shown in the plan view of FIG.

Next, in the insulating film opening portion 61, the metal film 31,
31a and 31b are formed, and the surface protection film 13 is further formed on the entire surface (FIG. 2B). This metal film 31, 31a,
31b is formed by vapor-depositing Al with a thickness of about 500 nm, for example. The metal film 31 simultaneously forms the metal film 31a in the area where the air bridge is to be formed and the metal film 31b in the gate electrode portion of the FET. The surface protection film 13 is formed of SiN with a thickness of about 200 nm.

Next, a resist 42 is applied on the surface protective film 13 (FIG. 2 (c)).

Next, on the metal films 31, 31a and 31b, a portion other than the wiring electrode formation planned region 62, that is, a predetermined region of the surface protective film 13 as shown in the plan view of FIG. The part 63 is formed. The surface protective film opening 63 is also formed on the ohmic electrode 21 and the gate electrode lead portion,
A contact hole with the wiring electrode. The surface protection film opening 63 is formed of SiN by, for example, a dry etching method.
It is formed by etching the film.

Next, a wiring electrode 23 is formed on the surface protective film 13.
Is formed (FIG. 3B). The wiring electrode 23 is made of Ti, P
t and Au have thicknesses of 300 nm, 100 nm and 15 respectively.
It is formed by vapor deposition to a thickness of about 00 nm.

Next, the metal film 31a is selectively removed by etching through the surface protective film opening 63 (FIG. 3).
(C)). Since the metal film 31 is Al, etching can be performed by using a chemical that dissolves Al but does not dissolve Ti / Pt / Au, for example, an aqueous sodium hydroxide solution. If the etching time is made sufficiently long, the metal film 31a immediately below the wiring electrode 23 is also removed by side etching.

The portion from which the metal film 31 has been removed by the steps described above becomes the air layer 51, and the air bridge structure is formed (FIG. 4).

[0038]

According to the method for manufacturing a semiconductor device of the present invention, since the air bridge structure is formed by etching and removing the metal layer immediately below the wiring electrode after forming the wiring electrode, the wiring electrode having good flatness. Can be formed. Further, the steps other than the etching of the metal layer can be performed at the same time as the normal FET gate step, so that the steps can be simplified. Further, since the resist is not used as a base for forming the air bridge, it is possible to prevent the yield from being reduced due to the re-patterning of the resist.

[Brief description of drawings]

1A to 1D are cross-sectional views each showing a part of a method of manufacturing a semiconductor device according to one embodiment of the present invention in the order of steps,

2A is a plan view of FIG. 1D, FIG. 2B and FIG. 2C are sectional views showing a part of a method of manufacturing a semiconductor device according to one embodiment of the present invention in the order of steps.

3A is a plan view of FIG. 2C, and FIGS. 3B and 3C are cross-sectional views showing a part of a method of manufacturing a semiconductor device according to one embodiment of the present invention in the order of steps.

FIG. 4 is a sectional view showing a part of a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps,

5A to 5C are cross-sectional views each showing a part of a method of manufacturing a semiconductor device of a conventional example in the order of steps,

6A to 6D are cross-sectional views each showing a part of a method of manufacturing a semiconductor device of a conventional example in the order of steps.

7 (a) to 7 (d) are cross-sectional views each showing a part of a method of manufacturing a semiconductor device of a conventional example in the order of steps.

FIG. 8 is a cross-sectional view showing a part of a method for manufacturing a semiconductor device of a conventional example.

[Explanation of symbols]

 11 ... Semiconductor substrate 12 ... Insulating film 13 ... Surface protective film 21 ... Ohmic electrode 22 ... Gate electrode 23, 24, 25 ... Wiring electrode 31 ... Metal film 32 ... Electroplating metal film 41, 42, 43, 44 ... Resist 51 ... Air layer 61 ... Insulating film opening 62 ... Wiring electrode formation planned area 63 ... Surface protective film opening 64 ... Contact hole 65 ... Air bridge formation planned area

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor device comprising at least a field effect transistor and a wiring electrode having a bridge pier structure formed on a main surface of a semiconductor substrate, wherein a metal film is provided in a pier formation planned area on the main surface of the semiconductor substrate. A step of forming, a step of forming a surface protective film on the metal film, a step of forming an opening penetrating the metal film in a desired region of the surface protective film, and a wiring electrode on the surface protective film. A method of manufacturing a semiconductor device, comprising: a step of forming the metal film; and a step of etching and removing the metal film from the opening of the surface protective film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the metal film is formed simultaneously with the gate electrode of the field effect transistor. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the metal film contains at least aluminum.