JPH0964303A - Method for manufacturing semiconductor integrated circuit device - Google Patents

Abstract

(57) [Abstract] [Purpose] Capacitor over bit line (CO
B) The number of manufacturing steps of a DRAM having a memory cell having a structure is reduced. Further, the difference in aspect ratio between the connection hole formed in the memory cell region and the connection hole formed in the peripheral circuit region is reduced. The wirings 20 and 21 of the first layer of the peripheral circuit and the upper electrode 19 of the capacitive element for storing information of the memory cell are simultaneously formed by using the wiring material of the same layer, and the second layer of the peripheral circuit is formed. The wiring 27 and the wiring 25 on the upper electrode 19 are simultaneously formed by using the wiring material in the same layer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device manufacturing technique, and more particularly to a DRAM (Dynamic Random Acce
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having an ss memory).

[0002]

2. Description of the Related Art In recent large-capacity DRAMs, in order to compensate for the decrease in the stored charge amount (Cs) of the information storage capacitive element (capacitor) accompanying the miniaturization of the memory cell, the information storage capacitive element is selected as a memory cell. Adopts a stack capacitor structure that is placed on top of the MISFET for use.

There are various types of stacked capacitor structures. Among them, a capacitor over bit line (Cap) in which an information storage capacitive element is arranged above a bit line is known.
The acitor over bitline (COB) structure is characterized in that the underlying step of the storage electrode (storage node) is flattened by the bit line, so that the load on the process for forming the information storage capacitive element is reduced. In addition, since the bit line is shielded by the information storage capacitor, a high signal-to-noise (S / N) ratio can be obtained.
A DRAM having a memory cell having a COB structure is described in Japanese Patent Application Laid-Open No. 7-122654.

[0004]

The manufacturing process of the memory cell having the COB structure described above is roughly as follows.

First, the first conductive film (polycrystalline silicon film or polycide film) deposited on the semiconductor substrate is used to form the gate electrode and word line of the memory cell selecting MISFET. Subsequently, a bit line is formed by the second conductive film (polycrystalline silicon film or polycide film) deposited on the upper layer of the gate electrode (word line) via the insulating film, and further on the upper layer of the bit line via the insulating film. The lower electrode (storage electrode) of the information storage capacitive element is formed by the third conductive film (polycrystalline silicon film) deposited by deposition.

Next, an upper electrode (plate electrode) of the information storage capacitive element is formed by a fourth conductive film (polycrystalline silicon film) deposited on the upper layer of the lower electrode via a capacitive insulating film, and then the upper electrode is formed. Fifth deposited on the upper layer of the electrode through an interlayer insulating film
Conductive film (aluminum alloy film or tungsten film)
Then, a first layer wiring connected to the upper electrode of the information storage capacitive element and a first layer wiring connected to the MISFET of the peripheral circuit are formed. Then, the second layer is formed on the upper layer of the first layer wiring.
The sixth conductive film (aluminum alloy film) deposited via the interlayer insulating film of the second layer is used to connect the second layer wiring such as the main word line, the common source line, and the wiring connected to the first layer wiring of the peripheral circuit. Form. Thereafter, the deposition of the interlayer insulating film and the deposition / etching of the conductive film are repeated to form the third and subsequent wirings. The interlayer insulating film that insulates the upper and lower wiring layers is formed of BP
An SG (Boro Phospho Silicate Glass) film or the like is used, and a flattening process such as reflow is performed in order to prevent disconnection of the upper and lower wiring layers inside the connection hole formed in the interlayer insulating film.

According to the study by the present inventor, the above-mentioned COB
The structured memory cell has a problem that its manufacturing process is very long. For example, patterning of the fourth conductive film (formation of the upper electrode), etching of the interlayer insulating film (connection hole) only during the step of forming the upper electrode of the information storage capacitive element to the step of forming the second layer wiring. Formation), patterning of the fifth conductive film (formation of the first layer wiring), etching of the second layer interlayer insulating film (formation of connection holes), patterning of the sixth conductive film (formation of the second layer wiring) Therefore, only the photoresist process requires 5 processes. Therefore, DRAM
In order to improve the manufacturing yield of, it is essential to devise a process that reduces the number of steps as much as possible.

Further, in the memory cell having the COB structure, the information storage capacitive element is arranged above the bit line. Therefore, when the connection hole is formed by etching the interlayer insulating film in the upper layer of the information storage capacitive element, the memory cell is formed. There is a large difference in aspect ratio between the connection hole formed in the cell region and the connection hole formed in the peripheral circuit region. That is, the connection hole that connects the first-layer wiring and the upper electrode of the information storage capacitor is
While it is formed only by etching the interlayer insulating film covering the upper electrode, the first layer wiring and the substrate of the peripheral circuit (MI
Since the connection holes for connecting to the source and drain regions of the SFET) are formed by etching not only the above-mentioned interlayer insulating film but all insulating films under the same, the aspect ratio is higher than that of the connecting holes on the upper electrode. Grows very large. Therefore, if these connection holes are formed at the same time in the same etching step, the amount of overetching of the shallow connection holes formed on the upper electrode increases, and the bottom of the connection hole penetrates to the conductive layer below the upper electrode. As a result, the upper and lower conductive layers may be short-circuited. In addition, since the connection holes formed in the peripheral circuit have a very large aspect ratio, the processing accuracy is likely to be lowered, or the conductive film is not sufficiently embedded, so that the connection reliability between the substrate and the wiring is lowered. May cause wire breakage.

An object of the present invention is to provide a capacitor over
DR having memory cell of bit line (COB) structure
It is to provide a technique capable of reducing the number of AM manufacturing processes.

Another object of the present invention is to reduce the difference in aspect ratio between the connection hole formed in the memory cell region and the connection hole formed in the peripheral circuit region in the DRAM having the COB structure memory cell. It is to provide the technology that can.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

(1) The present invention provides a memory cell having a COB structure in which a bit line is arranged above a memory cell selecting MISFET formed on a semiconductor substrate, and an information storage capacitive element is arranged above the bit line. A method of manufacturing a semiconductor integrated circuit device having a DRAM, comprising: (a) patterning a first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a gate electrode of a MISFET of a peripheral circuit. (B) M of the memory cell selecting MISFET and the peripheral circuit
Opening a first insulating film deposited on the upper layer of the ISFET to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the inside of the first connection hole Patterning the second conductive film deposited on the upper layer of the first insulating film including the above to form a bit line connected to one of the source and drain regions of the memory cell selecting MISFET through the first connection hole. (D) Opening the second insulating film and the first insulating film deposited on the upper layer of the bit line to form a second connecting hole reaching the other of the source and drain regions of the memory cell selecting MISFET. And (e) patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the second connection hole, and through the second connection hole, the memory cell selection MISFE. Forming a lower electrode of the information storage capacitive element connected to the other of the source and drain regions of (5), (f) depositing a capacitive insulating film of the information storage capacitive element on the upper layer of the lower electrode, and then performing the capacitive insulation. Opening a film, the second insulating film and the first insulating film to form a third connection hole reaching the MISFET of the peripheral circuit;
(G) The fourth conductive film deposited on the capacitive insulating film including the inside of the third connection hole is patterned, and the upper electrode of the information storage capacitive element and the MISFET of the peripheral circuit through the third connection hole. Forming a first wiring connected to the upper electrode, and (h) a fourth connection hole reaching the upper electrode by opening a hole in the third insulating film deposited on the upper electrode and the upper layer of the first wiring, Forming a fifth connection hole reaching the first wiring, and (i) patterning a fifth conductive film deposited on the third insulating film including the insides of the fourth connection hole and the fifth connection hole. Forming a second wiring connected to the upper electrode through the fourth connection hole and a third wiring connected to the first wiring through the fifth connection hole.

(2) The present invention provides a memory cell having a COB structure in which a bit line is arranged above a memory cell selecting MISFET formed on a semiconductor substrate, and an information storage capacitive element is arranged above the bit line. A method of manufacturing a semiconductor integrated circuit device having a DRAM, comprising: (a) patterning a first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a gate electrode of a MISFET of a peripheral circuit. (B) M of the memory cell selecting MISFET and the peripheral circuit
Opening a first insulating film deposited on the upper layer of the ISFET to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the inside of the first connection hole Patterning the second conductive film deposited on the upper layer of the first insulating film including the above to form a bit line connected to one of the source and drain regions of the memory cell selecting MISFET through the first connection hole. (D) Opening the second insulating film and the first insulating film deposited on the upper layer of the bit line to form a second connecting hole reaching the other of the source and drain regions of the memory cell selecting MISFET. And (e) patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the second connection hole, and through the second connection hole, the memory cell selection MISFE. Forming a lower electrode of the information storage capacitive element connected to the other of the source and drain regions of (5), (f) depositing a capacitive insulating film of the information storage capacitive element on the upper layer of the lower electrode, and then performing the capacitive insulation. Opening a film, the second insulating film and the first insulating film to form a third connection hole reaching the MISFET of the peripheral circuit;
(G) Embedding a fourth conductive film inside the third connection hole; (h) Patterning the fifth conductive film deposited on the capacitive insulating film including the inside of the third connection hole to accumulate information. Forming an upper electrode of the capacitor element and a first wiring connected to the MISFET of the peripheral circuit through the third connection hole, (i) a third layer deposited on the upper electrode and the first wiring Opening an insulating film to form a fourth connection hole reaching the upper electrode and a fifth connection hole reaching the first wiring; (j) the inside of the fourth connection hole and the fifth connection hole Patterning a sixth conductive film deposited on the third insulating film including a second wiring connected to the upper electrode through the fourth connection hole and connected to the first wiring through the fifth connection hole. Forming a third wiring to be formed,
Is included.

[0015]

According to the above means (1), the MI of the peripheral circuit is
By simultaneously forming the first wiring connected to the SFET and the upper electrode of the information storage capacitive element of the memory cell using the wiring material of the same layer, the first wiring is formed above the upper electrode via the interlayer insulating film. Compared with the method of forming the above-mentioned method, the number of steps for forming the interlayer insulating film, the step for forming the connection hole, and the step for depositing / patterning the wiring material is reduced by one step, respectively, and accordingly, the number of DRAM manufacturing steps can be reduced accordingly.

Further, the MISF of the first wiring and the peripheral circuit
Since the third connection hole connecting to ET is formed by etching the insulating film below the lower electrode of the information storage capacitor, the first wiring is formed above the upper electrode of the information storage capacitor. Compared with the case, the aspect ratio of the third connection hole can be made smaller, which improves the processed shape of the third connection hole and the burying property of the wiring material in the third connection hole, so that the connection of the first wiring The reliability and the yield of the step of forming the first wiring are improved.

Also, a fifth connecting hole for connecting the third wiring and the first wiring of the peripheral circuit, and a fourth connecting hole for connecting the second wiring on the upper electrode of the information storage capacitor and the upper electrode, respectively. Since the third insulating film is formed by etching, the aspect ratio can be reduced. Moreover, since the upper electrode and the third wiring are formed on the same wiring layer, the fourth connection hole and the fifth wiring are formed.
The aspect ratios of the connection holes are almost the same. This allows
It is possible to prevent problems such as penetration of the fourth connection hole and the fifth connection hole due to overetching, and also the processed shapes of the fourth connection hole and the fifth connection hole and the fourth connection hole and the fifth connection hole.
Since the filling property of the wiring material in the connection hole is improved, the connection reliability of the second wiring and the third wiring and the yield of the step of forming the second wiring and the third wiring are improved.

According to the above means (2), by embedding the conductive film in the third connection hole, the connection reliability of the first wiring connected to the MISFET of the peripheral circuit through the third connection hole is further improved. .

[0019]

Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, those having the same function are designated by the same reference numeral, and the repeated description thereof will be omitted.

(Embodiment 1) A method of manufacturing a DRAM having a COB structure memory cell according to this embodiment will be described with reference to FIGS.

First, as shown in FIG. 1, a field oxide film 2 and a gate oxide film 3 are formed on the main surface of a semiconductor substrate 1 by a known method, and then a MISFET for memory cell selection (memory array) is formed in a memory cell region (memory array). Qt) is formed, and an n-channel type MISFET (Qs) is formed in the peripheral circuit region. The gate electrode 4 of each of the memory cell selecting MISFET and the n-channel type MISFET is a polycrystalline silicon film (or a polycide film in which a polycrystalline silicon film and a refractory metal silicide film are laminated) on the semiconductor substrate 1 by the CVD method. A silicon oxide film 5 is deposited, and these films are patterned by etching using a photoresist as a mask. The gate electrode 4 of the memory cell selecting MISFET also serves as the word line WL and is configured integrally with the word line WL. The n-type semiconductor region 6 (source region, drain region) of each of the memory cell selection MISFET and the n-channel type MISFET is formed by implanting an n-type impurity (for example, phosphorus) in the semiconductor substrate 1 using the gate electrode 4 as a mask. .

Next, as shown in FIG. 2, after depositing the silicon oxide film 7 and the BPSG film 8 on the semiconductor substrate 1 by the CVD method, the BPSG film 8 is reflowed to planarize its surface. Subsequently, after forming a contact hole 9 in the BPSG film 8 on one of the source and drain regions (n-type semiconductor region 6) of the memory cell selection MISFET, polycrystalline silicon deposited on the BPSG film 8 by the CVD method. MISF for memory cell selection by patterning the film (or polycide film)
A bit line BL is formed on the upper layer of ETQt.

Next, as shown in FIG. 3, the lower electrode (storage electrode) 11 of the information storage capacitor is formed on the upper layer of the bit line BL via the BPSG film 10. To form the lower electrode 11, BPSG is formed on the upper layer of the bit line BL by the CVD method.
After depositing the film 10, the BPSG film 10 is reflowed to planarize its surface. Then, MISF for memory cell selection
Source and drain regions of ETQt (n-type semiconductor region 6)
BPSG films 10 and 8 and silicon oxide film 7 on the other side of
After the gate oxide film 3 is etched to form the contact hole 12, the polycrystalline silicon film (or polycide film) deposited on the BPSG film 10 by the CVD method is patterned.

Next, as shown in FIG. 4, after forming the capacitance insulating film 13 of the information storage capacitance element on the lower electrode 11, the capacitance insulating film 13, the BPSG films 10 and 8, the silicon oxide film 7, By etching 5 and the gate oxide film 3, a connection hole 13 reaching one of the source and drain regions (n-type semiconductor region 6) of the n-channel type MISFET of the peripheral circuit and a connection hole 14 reaching the gate electrode 4 are formed. .

Next, as shown in FIG.
A Ti (titanium) film 16, a TiN (titanium nitride) film 17 and a W (tungsten) film 18 are deposited on the capacitive insulating film 13 including the insides of 3 and 14. The Ti film 16 is deposited by the sputtering method, the TiN film 17 is deposited by the reactive sputtering method, and the W film 18 is deposited by the CVD method.

Next, as shown in FIG. 6, the Ti film 1 is formed.
6, the TiN film 17 and the W film 18 are patterned to form the upper electrode 19 of the information storage capacitive element and the first layer wirings 20 and 21 of the peripheral circuit. Peripheral circuit wiring 2
0 is an n-channel MISFE through the connection hole 13.
The wiring 21 is connected to the n-type semiconductor region 6 of T and is connected to the gate electrode 4 through the connection hole 14.

Next, as shown in FIG. 7, second-layer wirings 23 to 27 are formed on the upper electrode 19 and the wirings 20 and 21 via the interlayer insulating film 21. Of the wirings 23 to 25 formed in the upper layer of the information storage capacitive element, the wiring 25
Are connected to the upper electrode 19 through connection holes 28 formed in the interlayer insulating film 22. In addition, the wiring 26 of the peripheral circuit,
Among the wirings 27, the wiring 27 is connected to the wiring 21 of the first layer through the connection hole 29 formed in the interlayer insulating film 22, and further connected to the gate electrode 4 through this wiring 21.
The wiring 26 is connected to the wiring 20 of the first layer through a connection hole (not shown) formed in the interlayer insulating film 22, and is further connected to one of the n-type semiconductor regions 6 of the n-channel MISFET through the wiring 20.

The interlayer insulating film 22 is formed of, for example, plasma C
It is composed of three layers: a silicon oxide film deposited by the VD method, a spin-on-glass film deposited by the spin coating method, and a silicon oxide film deposited by the plasma CVD method. Also, wiring 2
3 to 27 are composed of, for example, three layers of a Ti film deposited by the sputtering method, an aluminum (Al) alloy film deposited by the sputtering method, and a TiN film deposited by the reactive sputtering method.

Next, as shown in FIG. 8, a second layer interlayer insulating film 30 is deposited on the second layer wirings 23 to 27, and a third layer insulating film 30 is deposited on the interlayer insulating film 30. Wiring 31-33
Is formed, the DRAM of this embodiment is substantially completed. The interlayer insulating film 30 is composed of, for example, three layers of a silicon oxide film deposited by a plasma CVD method, a spin-on-glass film deposited by a spin coating method, and a silicon oxide film deposited by a plasma CVD method, and the wirings 31 to 33 are, for example, Ti film deposited by sputtering method, Al deposited by sputtering method
3 of alloy film and TiN film deposited by reactive sputtering
Composed of layers.

In this way, the wiring 2 of the first layer of the peripheral circuit is
According to the manufacturing method of the present embodiment in which 0 and 21 and the upper electrode 19 of the information storage capacitive element of the memory cell are formed in the same step using the wiring material of the same layer, an interlayer insulating film is formed on the upper layer of the upper electrode. Compared to the case of forming the wiring of the first layer via
Since the number of steps for forming the interlayer insulating film, the step for forming the connection hole, and the step for depositing / patterning the wiring material are reduced by one, the number of DRAM manufacturing steps can be reduced accordingly.

Further, according to the manufacturing method of this embodiment, the wirings 20 and 21 of the first layer of the peripheral circuit and the n-channel type MIS are formed.
The connection holes 13 and 14 for connecting the n-type semiconductor region 6 of the FET and the gate electrode 4 are formed in the lower electrode 1 of the information storage capacitor.
Since the insulating film below 1 is formed by etching,
The aspect ratio of the connection holes 13 and 14 becomes smaller than that in the case where the wiring of the first layer is formed in the upper layer of the upper electrode of the information storage capacitor. As a result, the processed shapes of the connection holes 13 and 14 and the filling characteristics of the wiring material in the connection holes 13 and 14 are improved, so that the connection reliability of the wirings 20 and 21 and the yield of the step of forming the wirings 20 and 21 are improved. improves.
Further, the throughput of the process of forming the connection holes 13 and 14 is also improved.

Further, according to the manufacturing method of this embodiment, the connection hole 29 for connecting the second layer wiring 27 and the first layer wiring 21 of the peripheral circuit, and the upper electrode 19 of the information storage capacitive element.
Since each of the connection holes 28 connecting the upper wiring 25 and the upper electrode 19 is formed by etching only the interlayer insulating film 22, the aspect ratio becomes small. Moreover, since the upper electrode 19 and the wiring 21 are formed in the same wiring layer, the aspect ratios of the connection holes 28 and 29 are substantially the same. As a result, it is possible to prevent defects such as penetration of the connection holes 28 and 29 due to overetching, and to improve the processed shape of the connection holes 28 and 29 and the filling characteristics of the wiring material in the connection holes 28 and 29. Therefore, the wiring 23, 26
The connection reliability and the yield of the step of forming the wirings 20 and 21 are improved.

(Embodiment 2) In Embodiment 1, after the capacitance insulating film 13 is deposited on the lower electrode 11 of the information storage capacitive element, the capacitance insulating film 13, the BPSG films 10 and 8, the silicon oxide film 7, 5 and the gate oxide film 3 were etched to form a connection hole 13 reaching one of the source and drain regions (n-type semiconductor region 6) of the n-channel type MISFET of the peripheral circuit and a connection hole 14 reaching the gate electrode 4.

On the other hand, in this embodiment, as shown in FIG. 9, after the capacitance insulating film 13 is deposited on the lower electrode 11 of the information storage capacitive element, the Ti film 16 is deposited on the capacitive insulating film 13. , Then the Ti film 16, the capacitive insulating film 13, the BPSG
By etching the films 10 and 8, the silicon oxide films 7 and 5, and the gate oxide film 3, the connection hole 13 and the gate that reach one of the source and drain regions (n-type semiconductor region 6) of the n-channel type MISFET of the peripheral circuit. A connection hole 14 reaching the electrode 4 is formed.

Next, as shown in FIG.
After depositing the TiN film 17 and the W film 18 on the Ti film 16 including the insides of 3 and 14, the Ti film 16, the TiN film 17 and the W film 18 are patterned, and the upper electrode 19 of the information storage capacitive element, And the wiring 2 of the first layer of the peripheral circuit
0 and 21 are formed. The subsequent steps are the same as in the first embodiment.

According to this embodiment, the same effect as that of the first embodiment can be obtained.

(Embodiment 3) In the manufacturing method of this embodiment, as shown in FIG. 11, first, as shown in FIG. 11, a capacitance insulating film 13 is deposited on the upper layer of the lower electrode (storage electrode) 11 of the information storage capacitive element, and then the capacitance is increased. The insulating film 13, the BPSG films 10 and 8, the silicon oxide films 7 and 5, and the gate oxide film 3 are etched to reach one of the source and drain regions (n-type semiconductor region 6) of the n-channel type MISFET of the peripheral circuit. A connection hole 13 and a connection hole 14 reaching the gate electrode 4 are formed. The steps up to this point are the same as in the first embodiment.

Next, in this embodiment, as shown in FIG.
A W film 35 is embedded inside the connection holes 13 and 14. W
The film 35 is embedded by depositing the W film 35 on the capacitive insulating film 13 including the insides of the connection holes 13 and 14 by the CVD method and then removing the W film 35 on the capacitive insulating film 13 by the etch back method. .

Next, as shown in FIG. 13, the capacitor insulating film 1
By depositing, for example, a TiN film and an Al alloy film on 3 and patterning these films, the upper electrode 19 of the information storage capacitive element and the first layer wiring 2 of the peripheral circuit are formed.
0 and 21 are formed. The subsequent steps are the same as in the first embodiment.

According to the third embodiment, by embedding the W film 35 inside the connection holes 13 and 14, the wirings 20 and 21 are formed.
Connection reliability can be further improved.

(Embodiment 4) In the manufacturing method of this embodiment, as shown in FIG. 14, first, as shown in FIG. 14, a capacitive insulating film 13 and a Ti film 16 are formed on the lower electrode (storage electrode) 11 of the information storage capacitive element.
After depositing and, the Ti film 16, the capacitor insulating film 13, the BPS
By etching the G films 10 and 8, the silicon oxide films 7 and 5, and the gate oxide film 3, a connection hole 13 reaching one of the source and drain regions (n-type semiconductor region 6) of the n-channel type MISFET of the peripheral circuit and Gate electrode 4
To form the connection hole 14 reaching to. The steps up to this point are the same as in the second embodiment.

Next, in this embodiment, as shown in FIG.
A W film 35 is embedded inside the connection holes 13 and 14. W
The film 35 is embedded by depositing the W film 35 on the capacitive insulating film 13 including the insides of the connection holes 13 and 14 by the CVD method and then removing the W film 35 on the capacitive insulating film 13 by the etch back method. .

Next, as shown in FIG. 16, for example, a TiN film and an Al alloy film are deposited on the Ti film 16, and these films are patterned to form the upper electrode 19 of the information storage capacitive element, and First layer wiring 20 of the peripheral circuit,
21 are formed. The subsequent steps are the same as in the first embodiment.

According to this embodiment, it is possible to obtain the same effect as that of the third embodiment.

(Embodiment 5) In the manufacturing method of this embodiment, as shown in FIG. 17, first, a capacitor insulating film 13 is deposited on the upper layer of the lower electrode (storage electrode) 11 of the information storage capacitor, and then the capacitor is formed. The insulating film 13, the BPSG films 10 and 8, the silicon oxide films 7 and 5, and the gate oxide film 3 are etched to reach one of the source and drain regions (n-type semiconductor region 6) of the n-channel type MISFET of the peripheral circuit. A connection hole 13 and a connection hole 14 reaching the gate electrode 4 are formed. Subsequently, a TiN film 17 and a Ti film 16 are deposited on the capacitive insulating film 13 including the insides of the connection holes 13 and 14.

Next, in this embodiment, as shown in FIG.
After depositing the Al alloy film 36 on the Ti film 16, the Al alloy film 36 is reflowed to be embedded in the connection holes 13 and 14. The Al alloy film 36 is embedded by depositing the Al alloy film 36 with a film thickness of about 1.5 to 3 times the diameter of the connection holes 13 and 14, and subsequently under a high pressure of about 100 atm of about 350 to 500 ° C. This is performed by heating the Al alloy film 36 at a high temperature. After that, FIG.
, The Al alloy film 36, the Ti film 16 and the Ti film
By patterning the N film 17, the upper electrode 19 of the information storage capacitor and the wirings 20 and 2 of the first layer of the peripheral circuit are formed.
Form one. The subsequent steps are the same as in the first embodiment.

According to this embodiment, the same effect as that of the third embodiment can be obtained by embedding the Al alloy film 36 inside the connection holes 13 and 14.

(Embodiment 6) In the manufacturing method of this embodiment, as shown in FIG. 20, first, as shown in FIG. 20, a BPSG film 10 is deposited on the upper layer of the bit line BL by the CVD method, and the surface thereof is flattened by reflowing. By etching the BPSG film 10 in the memory cell region using the photoresist as a mask, the film thickness of the BPSG film 10 in the memory cell region is made thinner than that in the peripheral circuit region.

Next, as shown in FIG. 21, the BPSG films 10 and 8, the silicon oxide film 7 and the gate oxide film 3 above the source and drain regions (n-type semiconductor region 6) of the memory cell selecting MISFET Qt are etched. Then connection hole 1
After forming 2, the polycrystalline silicon film (or polycide film) deposited by the CVD method on the BPSG film 10 is patterned to form the lower electrode 11 of the information storage capacitor. At this time, since the film thickness of the BPSG film 10 in the memory cell region is made thinner than that in the peripheral circuit region in advance, the elevation of the lower electrode 11 of the information storage capacitor and the BPSG film 10 in the peripheral circuit region. Altitude is almost equal.

Next, as shown in FIG. 22, the lower electrode 11
After forming the capacitive insulating film 13 and the TiN film 17 on the upper layer, the capacitive insulating film 13, the TiN film 17, the BPSG film 10,
8, the silicon oxide films 7 and 5 and the gate oxide film 3 are etched to obtain an n-channel MIS of the peripheral circuit
A connection hole 13 reaching the source / drain region (n-type semiconductor region 6) of the FET and a connection hole 1 reaching the gate electrode 4.
4 is formed.

Next, as shown in FIG. 23, the connection hole 1
After depositing the Ti film 16 on the TiN film 17 including the insides of 3 and 14, the W film 35 is embedded inside the connection holes 13 and 14. The W film 35 is embedded by depositing the W film 35 on the Ti film 16 including the insides of the connection holes 13 and 14, and then using the chemical mechanical polishing (CMP) method to form the W film on the Ti film 16. The film 35 is removed. At this time, BP
The W film 35 is also embedded in the low step portion of the SG film 10 and the gaps between the lower electrodes 11, 11.

Next, as shown in FIG. 24, an Al alloy film 36 is deposited on the Ti film 16, and then the Al alloy film 36 and T are deposited.
By patterning the i film 16 and the TiN film 17, the upper electrode 19 of the information storage capacitor and the first layer wirings 20 and 21 of the peripheral circuit are formed. The subsequent steps are the same as in the first embodiment.

According to this embodiment, the difference in elevation between the upper electrode 19 of the information storage capacitor and the wirings 20 and 21 of the first layer of the peripheral circuit can be reduced, so that the upper electrode 19 and the wiring 20, 21 can be formed with high dimensional accuracy. This also improves the dimensional accuracy of the second and subsequent wiring layers.

As described above, the invention made by the inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, the upper electrode of the information storage capacitor and the first-layer wiring of the peripheral circuit are the same as those used in the above embodiment.
In addition to the i film, the TiN film, the W film, the Al alloy film, a polycrystalline silicon film, a tungsten silicide (WSi ₂ ) film, a titanium silicide (TiSi ₂ ) film and the like can be used.

[0056]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

According to the present invention, the number of manufacturing steps of a DRAM having a COB structure memory cell can be reduced, so that the manufacturing yield of the DRAM can be improved.

According to the present invention, in the DRAM having the memory cell having the COB structure, it is possible to reduce the difference in aspect ratio between the connection hole formed in the memory cell region and the connection hole formed in the peripheral circuit region. Therefore, the connection reliability of the wiring in the connection hole and the yield of the wiring forming process are improved.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of essential parts of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 1 of the present invention.

FIG. 3 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 1 of the present invention.

FIG. 4 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 5 is a cross-sectional view of essential parts of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 1 of the present invention.

FIG. 6 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 7 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 8 is a fragmentary cross-sectional view of the semiconductor substrate showing the method of manufacturing the DRAM according to the first embodiment of the present invention.

FIG. 9 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 2 of the present invention.

FIG. 10 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 2 of the present invention.

FIG. 11 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 3 of the present invention.

FIG. 12 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 3 of the present invention.

FIG. 13 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 3 of the present invention.

FIG. 14 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 4 of the present invention.

FIG. 15 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 4 of the present invention.

FIG. 16 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 4 of the present invention.

FIG. 17 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 5 of the present invention.

FIG. 18 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 5 of the present invention.

FIG. 19 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 5 of the present invention.

FIG. 20 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 6 of the present invention.

FIG. 21 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 6 of the present invention.

FIG. 22 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 6 of the present invention.

FIG. 23 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 6 of the present invention.

FIG. 24 is a fragmentary cross-sectional view of a semiconductor substrate showing a method of manufacturing a DRAM that is Embodiment 6 of the present invention.

[Explanation of symbols]

 1 semiconductor substrate 2 field oxide film 3 gate oxide film 4 gate electrode 5 silicon oxide film 6 n-type semiconductor region (source region, drain region) 7 silicon oxide film 8 BPSG film 9 connection hole 10 BPSG film 11 lower electrode 12 connection hole 13 Capacitance insulating film 14 Connection hole 15 Connection hole 16 Ti film 17 TiN film 18 W film 19 Upper electrode 20 Wiring 21 Wiring 22 Interlayer insulating film 23 Wiring 24 Wiring 25 Wiring 26 Wiring 27 Wiring 28 Connection hole 29 Connection hole 30 Interlayer insulating film 31 Wiring 32 Wiring 33 Wiring 35 W film 36 Al alloy film

Claims (9)

[Claims] 1. A capacitor for arranging a bit line above a memory cell selection MISFET formed on a semiconductor substrate, and arranging an information storage capacitive element above the bit line.
DR with over-bitline structure memory cell
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) patterning the first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a MISFET of a peripheral circuit, (b) the MISFET for memory cell selection and the above Opening a first insulating film deposited on the upper layer of the MISFET of the peripheral circuit to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the first connection The second conductive film deposited on the first insulating film including the inside of the hole is patterned, and the memory cell selection MISFE is patterned through the first connection hole.
Forming a bit line connected to one of the source and drain regions of T, (d) opening the second insulating film and the first insulating film deposited on the upper layer of the bit line to select the memory cell For forming a second connection hole reaching the other of the source and drain regions of the second MISFET, (e) the second
Information storage connected to the other of the source and drain regions of the memory cell selecting MISFET through the second connection hole by patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the connection hole Forming a lower electrode of the capacitive element for storage, (f) depositing a capacitive insulating film of the capacitive element for information storage on the upper layer of the lower electrode, and then forming the capacitive insulating film, the second insulating film, and the first insulating film. Open the
Forming a third connection hole reaching the MISFET of the peripheral circuit; (g) patterning the fourth conductive film deposited on the capacitance insulating film including the inside of the third connection hole to form an information storage capacitor element. Forming an upper electrode and a first wiring connected to the MISFET of the peripheral circuit through the third connection hole, (h) a third insulating film deposited on the upper electrode and the first wiring. Forming a fourth connection hole reaching the upper electrode and a fifth connection hole reaching the first wiring; (i) including the inside of the fourth connection hole and the fifth connection hole; Fifth deposited on the third insulating film
Patterning the conductive film to form a second wiring connected to the upper electrode through the fourth connection hole and a third wiring connected to the first wiring through the fifth connection hole. A method of manufacturing a semiconductor integrated circuit device, comprising: 2. A capacitor for disposing a bit line above a memory cell selecting MISFET formed on a semiconductor substrate, and disposing an information storage capacitive element above the bit line.
DR with over-bitline structure memory cell
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) patterning the first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a MISFET of a peripheral circuit, (b) the MISFET for memory cell selection and the above Opening a first insulating film deposited on the upper layer of the MISFET of the peripheral circuit to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the first connection The second conductive film deposited on the first insulating film including the inside of the hole is patterned, and the memory cell selection MISFE is patterned through the first connection hole.
Forming a bit line connected to one of the source and drain regions of T, (d) opening the second insulating film and the first insulating film deposited on the upper layer of the bit line to select the memory cell For forming a second connection hole reaching the other of the source and drain regions of the second MISFET, (e) the second
Information storage connected to the other of the source and drain regions of the memory cell selecting MISFET through the second connection hole by patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the connection hole Forming a lower electrode of the capacitive element for storage, (f) depositing a capacitive insulating film and a fourth conductive film of the capacitive element for information storage on the upper layer of the lower electrode, and then forming the fourth conductive film, the capacitive insulating film, The second insulating film and the first insulating film are opened to open the MI of the peripheral circuit.
Forming a third connection hole reaching the SFET, (g) patterning the fifth conductive film and the fourth conductive film deposited on the capacitive insulating film including the inside of the third connection hole,
Forming an upper electrode of the information storage capacitor and a first wiring connected to the MISFET of the peripheral circuit through the third connection hole, (h) the upper electrode and the first electrode
A third insulating film deposited on the upper layer of the wiring is opened to form a fourth connection hole reaching the upper electrode and a fifth connecting hole reaching the first wiring.
Forming a connection hole; (i) patterning a sixth conductive film deposited on the third insulating film including the insides of the fourth connection hole and the fifth connection hole, and through the fourth connection hole, A method of manufacturing a semiconductor integrated circuit device, comprising: forming a second wiring connected to an upper electrode and a third wiring connected to the first wiring through the fifth connection hole. 3. A capacitor for arranging a bit line above a memory cell selecting MISFET formed on a semiconductor substrate, and arranging an information storage capacitive element above the bit line.
DR with over-bitline structure memory cell
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) patterning the first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a MISFET of a peripheral circuit, (b) the MISFET for memory cell selection and the above Opening a first insulating film deposited on the upper layer of the MISFET of the peripheral circuit to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the first connection The second conductive film deposited on the first insulating film including the inside of the hole is patterned, and the memory cell selection MISFE is patterned through the first connection hole.
Forming a bit line connected to one of the source and drain regions of T, (d) opening the second insulating film and the first insulating film deposited on the upper layer of the bit line to select the memory cell For forming a second connection hole reaching the other of the source and drain regions of the second MISFET, (e) the second
Information storage connected to the other of the source and drain regions of the memory cell selecting MISFET through the second connection hole by patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the connection hole Forming a lower electrode of the capacitive element for storage, (f) depositing a capacitive insulating film of the capacitive element for information storage on the upper layer of the lower electrode, and then forming the capacitive insulating film, the second insulating film, and the first insulating film. Open the
Forming a third connection hole reaching the MISFET of the peripheral circuit; (g) embedding a fourth conductive film in the third connection hole; (h) the capacitive insulation including the inside of the third connection hole. The fifth conductive film deposited on the film is patterned to be connected to the upper electrode of the information storage capacitive element and the MISFET of the peripheral circuit through the third connection hole.
Forming a wiring, and (i) opening a third insulating film deposited on the upper electrode and the first wiring to form a fourth connection hole reaching the upper electrode and reaching the first wiring. Forming a fifth connection hole; (j) patterning the sixth conductive film deposited on the third insulating film including the insides of the fourth connection hole and the fifth connection hole to form the fourth connection hole; Forming a second wiring connected to the upper electrode through the fifth connection hole and a third wiring connected to the first wiring through the fifth connection hole. . 4. The method for manufacturing a semiconductor integrated circuit device according to claim 3, wherein the fourth conductive film is embedded in the third connection hole by depositing the fourth conductive film and etching back. Or a combination of the fourth conductive film deposition and a chemical polishing method, or a combination of the fourth conductive film deposition and a reflow method. Production method. 5. A capacitor for arranging a bit line above a memory cell selecting MISFET formed on a semiconductor substrate, and arranging an information storage capacitive element above the bit line.
DR with over-bitline structure memory cell
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) patterning the first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a MISFET of a peripheral circuit, (b) the MISFET for memory cell selection and the above Opening a first insulating film deposited on the upper layer of the MISFET of the peripheral circuit to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the first connection The second conductive film deposited on the first insulating film including the inside of the hole is patterned, and the memory cell selection MISFE is patterned through the first connection hole.
Forming a bit line connected to one of the source and drain regions of T, (d) opening the second insulating film and the first insulating film deposited on the upper layer of the bit line to select the memory cell For forming a second connection hole reaching the other of the source and drain regions of the second MISFET, (e) the second
Information storage connected to the other of the source and drain regions of the memory cell selecting MISFET through the second connection hole by patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the connection hole Forming a lower electrode of the capacitive element for storage, (f) depositing a capacitive insulating film and a fourth conductive film of the capacitive element for information storage on the upper layer of the lower electrode, and then forming the fourth conductive film, the capacitive insulating film, The second insulating film and the first insulating film are opened to open the MI of the peripheral circuit.
A step of forming a third connection hole reaching the SFET, (g) a step of burying a fifth conductive film inside the third connection hole,
(H) The sixth conductive film and the fourth conductive film deposited on the capacitance insulating film including the inside of the third connection hole are patterned to form an upper electrode of the information storage capacitive element and the third connection hole. Forming a first wiring connected to the MISFET of the peripheral circuit through (i) opening a third insulating film deposited on the upper electrode and the upper layer of the first wiring,
Forming a fourth connection hole reaching the upper electrode and a fifth connection hole reaching the first wiring; (j) on the third insulating film including the insides of the fourth connection hole and the fifth connection hole; The seventh conductive film deposited on the substrate is patterned to form a second wiring connected to the upper electrode through the fourth connection hole and a third wiring connected to the first wiring through the fifth connection hole. A method of manufacturing a semiconductor integrated circuit device, comprising: 6. The method for manufacturing a semiconductor integrated circuit device according to claim 5, wherein the fifth conductive film is embedded in the third connection hole by depositing the fifth conductive film and etching back. Or a combination of the deposition of the fifth conductive film and a chemical mechanical polishing method, or a combination of the deposition of the fifth conductive film and a reflow method. Device manufacturing method. 7. A capacitor for arranging a bit line above a memory cell selecting MISFET formed on a semiconductor substrate, and arranging an information storage capacitive element above the bit line.
DR with over-bitline structure memory cell
A method for manufacturing a semiconductor integrated circuit device having an AM,
(A) patterning the first conductive film deposited on a semiconductor substrate to form a gate electrode of a MISFET for memory cell selection and a MISFET of a peripheral circuit, (b) the MISFET for memory cell selection and the above Opening a first insulating film deposited on the upper layer of the MISFET of the peripheral circuit to form a first connection hole reaching one of the source and drain regions of the memory cell selecting MISFET, (c) the first connection The second conductive film deposited on the first insulating film including the inside of the hole is patterned, and the memory cell selection MISFE is patterned through the first connection hole.
Forming a bit line connected to one of the source and drain regions of T, (d) depositing a second insulating film on the upper layer of the bit line, and then forming the second insulating layer on the upper layer of the MISFET for memory cell selection Etching the film to reduce the film thickness of the second insulating film in the upper layer of the MISFET for memory cell selection as compared with that in the upper layer of the MISFET of the peripheral circuit, (e) the second insulating film and the The first insulating film is opened to form the memory cell selection MISF.
Forming a second connection hole reaching the other of the source and drain regions of ET; (f) patterning the third conductive film deposited on the upper layer of the second insulating film including the inside of the second connection hole; Forming a lower electrode of an information storage capacitive element connected to the other of the source and drain regions of the memory cell selection MISFET through the second connection hole;
(G) After depositing the capacitive insulating film of the information storage capacitive element on the upper layer of the lower electrode, the capacitive insulating film, the second insulating film, and the first insulating film are opened to form the MI of the peripheral circuit.
A step of forming a third connection hole reaching the SFET, (h) a step of burying a fourth conductive film inside the third connection hole,
(I) The fifth conductive film deposited on the capacitive insulating film is patterned to form an upper electrode of the information storage capacitive element and a first wiring connected to the MISFET of the peripheral circuit through the third connection hole. Forming step, (j) opening a third insulating film deposited on the upper electrode and the first wiring to form a fourth connection hole reaching the upper electrode, and a fifth connection reaching the first wiring. Forming a hole, and (k) the fourth step.
The sixth conductive film deposited on the third insulating film including the inside of the connection hole and the fifth connection hole is patterned to form a second wiring connected to the upper electrode through the fourth connection hole, and the fifth wiring. A step of forming a third wiring connected to the first wiring through a connection hole, the method for manufacturing a semiconductor integrated circuit device. 8. The method for manufacturing a semiconductor integrated circuit device according to claim 7, wherein the fourth conductive film is embedded inside the third connection hole by depositing the fourth conductive film and chemically polishing the fourth conductive film. And a method of manufacturing a semiconductor integrated circuit device, the method comprising: 9. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the conductive film forming the upper electrode of the information storage capacitor and the first wiring is , A polycrystalline silicon film, a titanium film, a titanium nitride film, a tungsten film, a tungsten silicide film, an aluminum film, and a titanium silicide film, or a combination of two or more thereof. Manufacturing method.