JPH0964362A - MOS type semiconductor device and manufacturing method thereof - Google Patents
MOS type semiconductor device and manufacturing method thereofInfo
- Publication number
- JPH0964362A JPH0964362A JP7236147A JP23614795A JPH0964362A JP H0964362 A JPH0964362 A JP H0964362A JP 7236147 A JP7236147 A JP 7236147A JP 23614795 A JP23614795 A JP 23614795A JP H0964362 A JPH0964362 A JP H0964362A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- semiconductor device
- gate
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/60—Electrodes characterised by their materials
- H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
- H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
- H10D64/693—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
- H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
- H10D64/01332—Making the insulator
- H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
- H10D64/01338—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the conductor
Landscapes
- Formation Of Insulating Films (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】 Ｖｔｈの制御性と絶縁耐性を兼ね備るたゲー
ト絶縁膜を形成したＭＯＳ型半導体装置および、その製
造方法を提供する。
【解決手段】 Ｐ型シリコン基板１上に形成したゲート
酸化膜（ゲート絶縁膜）２、フィールド酸化膜３の全面
にポリシリコン膜を積層した後、熱拡散法によりリンを
ポリシリコン中に拡散させて低抵抗化させた。フォトリ
ソグラフィーおよびエッチングによりポリシリコン４
（ゲート電極）およびフォトレジスト５をパターニング
した。フォトレジスト５を除去した後、窒素イオン６を
回転斜め注入法によりイオン注入した後、熱処理を施す
ことにより、ゲート酸化膜２のうちポリシリコン４の端
部直下部分からフィールド酸化膜３の直近部分までを窒
化酸化膜７に変えた。
Kind Code: A1 A MOS type semiconductor device having a gate insulating film having Vth controllability and insulation resistance, and a method for manufacturing the same are provided. A polysilicon film is laminated on the entire surface of a gate oxide film (gate insulating film) 2 and a field oxide film 3 formed on a P-type silicon substrate 1, and then phosphorus is diffused into the polysilicon by a thermal diffusion method. To lower the resistance. Polysilicon 4 by photolithography and etching
The (gate electrode) and the photoresist 5 were patterned. After the photoresist 5 is removed, nitrogen ions 6 are ion-implanted by the rotary oblique implantation method, and then heat treatment is performed, so that a portion of the gate oxide film 2 immediately below the end portion of the polysilicon 4 to a portion immediately adjacent to the field oxide film 3 is subjected. Up to the nitride oxide film 7.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、ＭＯＳ型半導体装
置および、その製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type semiconductor device and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】デバイスの微細化に伴って、ゲート絶縁
膜の薄膜化が進んでいる。しかし、ゲート絶縁膜として
現在よく用いられているゲート酸化膜では、これを薄膜
化した場合の絶縁耐圧の劣化が重要な問題となってき
た。2. Description of the Related Art With the miniaturization of devices, the gate insulating film is becoming thinner. However, in the gate oxide film that is often used as the gate insulating film at present, the deterioration of the dielectric breakdown voltage has become an important issue when it is thinned.
【０００３】最近では、オキシナイトライド膜が、絶縁
耐圧特性およびホットキャリア耐性が酸化膜に比べて優
れているため注目されている。この膜は、ＮＨ3 雰囲気
中でのアニールにより酸化膜を熱窒化して形成される。
このオキシナイトライド膜では、アニールによりＨ原子
が導入されるため、電子トラップを導くという重大な欠
点があるが、この欠点は、この膜を高温で熱処理して前
記Ｈ原子をアニールアウトすることで取り除くことがで
きる。Recently, the oxynitride film has been attracting attention because it has excellent withstand voltage characteristics and hot carrier resistance as compared with the oxide film. This film is formed by thermally nitriding an oxide film by annealing in an NH 3 atmosphere.
In this oxynitride film, H atoms are introduced by annealing, so that there is a serious drawback that electron traps are introduced. This drawback is that the H atoms are annealed out by heat-treating this film at a high temperature. Can be removed.
【０００４】しかし、デバイスを微細化した場合、上記
高温の熱処理により増加した熱履歴が、デバイス特性に
悪影響を及ぼす問題があった。また、このオキシナイト
ライド膜は、信頼性の点では優れているものの、界面準
位、固定電荷の増加により移動度、Ｖｔｈ制御等の性能
面が、酸化膜に比べて劣るという問題もあった。However, when the device is miniaturized, there has been a problem that the thermal history increased by the high temperature heat treatment adversely affects the device characteristics. Further, although this oxynitride film is excellent in reliability, there is also a problem that performances such as mobility and Vth control are inferior to those of the oxide film due to increase of interface state and fixed charge. .
【０００５】一方、Ｈ原子の導入が伴わないＮ2 Ｏ雰囲
気中でのアニールも検討されている。この方法で形成さ
れた膜は、ＮＨ3 雰囲気中でのアニールによるオキシナ
イトライド膜に比べて性能面で優れているが、この膜中
に含まれる窒素濃度が低い（窒素原子濃度は２〜３原子
％）ため信頼性の面で、ＮＨ3 雰囲気中でのアニールに
よるオキシナイトライド膜に比べて劣るという問題があ
った。On the other hand, annealing in an N 2 O atmosphere without introduction of H atoms has also been studied. The film formed by this method is superior in performance to the oxynitride film obtained by annealing in an NH 3 atmosphere, but the nitrogen concentration contained in this film is low (the nitrogen atom concentration is 2 to 3). Therefore, there is a problem in terms of reliability that it is inferior to the oxynitride film obtained by annealing in an NH 3 atmosphere.
【０００６】オキシナイトライド膜の形成方法として、
ゲート酸化膜を形成し、このゲート酸化膜上から窒素イ
オンを注入した後、熱処理を施すものがあるが、この方
法では、拡散領域の全体で窒素濃度が一様になってしま
うという不具合があった。As a method of forming an oxynitride film,
There is a method in which a gate oxide film is formed, nitrogen ions are implanted from above the gate oxide film, and then heat treatment is performed. However, this method has a problem that the nitrogen concentration becomes uniform in the entire diffusion region. It was
【０００７】その一例として、特開平５−２８３６７９
号公報に、ゲート絶縁膜の固定電荷を減らし、しきい値
電圧のシフトを少なくするとともに、酸化膜トラップを
減らし、チャネルホットエレクトロン注入によるホット
キャリア劣化を抑えたＭＩＳ型半導体装置が開示されて
いる。この半導体装置におけるゲート絶縁膜は、チャネ
ル領域との界面部を構成する、窒素原子を１０19／ｃｍ
3 以上含む窒化酸化膜と、該窒化酸化膜上に配置され
た、窒素原子を１０19／ｃｍ3 以下の濃度で含むシリコ
ン酸化膜とからなる２層構造としたものである。[0007] As an example thereof, JP-A-5-283679
The publication discloses a MIS type semiconductor device in which fixed charges of a gate insulating film are reduced, threshold voltage shift is reduced, oxide film traps are reduced, and hot carrier deterioration due to channel hot electron injection is suppressed. . The gate insulating film in this semiconductor device has nitrogen atoms of 10 19 / cm 3 which form an interface with the channel region.
It has a two-layer structure of a nitrided oxide film containing 3 or more and a silicon oxide film arranged on the nitrided oxide film and containing nitrogen atoms at a concentration of 10 19 / cm 3 or less.
【０００８】また、特開平６−１５１８２９号公報に
は、固定電荷の発生や不安定化、界面準位の増大などを
防止することができるゲート絶縁膜を備えた半導体装置
の製造方法が記載されている。この製造方法は、シリコ
ン基板上に形成されたシリコン窒化酸化膜をゲート絶縁
膜として用い、このゲート絶縁膜上にゲート電極を形成
する半導体装置の製造方法において、シリコン窒化酸化
膜、またはシリコン窒化酸化膜とシリコン基板との界面
に窒素イオンをイオン注入することを特徴としている。
しかし、これら公報記載の技術では、ゲート絶縁膜の全
面にわたってシリコン窒化酸化膜を用いている。Further, Japanese Unexamined Patent Publication (Kokai) No. 6-151829 discloses a method of manufacturing a semiconductor device having a gate insulating film capable of preventing the generation and destabilization of fixed charges and the increase of interface states. ing. In this manufacturing method, a silicon nitride oxide film formed on a silicon substrate is used as a gate insulating film, and a gate electrode is formed on the gate insulating film. It is characterized in that nitrogen ions are implanted into the interface between the film and the silicon substrate.
However, in the techniques described in these publications, the silicon oxynitride film is used over the entire surface of the gate insulating film.
【０００９】さらに、特開平３−３８８３９号公報およ
び、特開平３−４２８７２号公報には、半導体装置の製
造に当たり、基板中に窒素イオンを注入することが開示
されている。しかし、この窒素イオン注入は、ソースお
よびドレインの拡散層の拡がりを抑制することを目的と
したものである。Further, Japanese Patent Application Laid-Open Nos. 3-38839 and 3-42872 disclose that nitrogen ions are implanted into a substrate when manufacturing a semiconductor device. However, this nitrogen ion implantation is intended to suppress the spread of the diffusion layers of the source and drain.
【００１０】[0010]
【発明が解決しようとする課題】ゲート絶縁膜の絶縁破
壊は、一般にゲートエッジで発生すると言われている。
これを防止するには、ゲート絶縁膜の窒素濃度を高くす
ることにより絶縁耐性を向上させればよい。しかし、窒
素濃度が高くなると、チャネル領域直上部のゲート絶縁
膜の固定電荷が増加してＶｔｈをシフトするため、Ｖｔ
ｈの制御性が劣るという問題が発生する。It is said that the dielectric breakdown of the gate insulating film generally occurs at the gate edge.
In order to prevent this, the insulation resistance may be improved by increasing the nitrogen concentration of the gate insulating film. However, when the nitrogen concentration increases, the fixed charge of the gate insulating film immediately above the channel region increases and Vth shifts, so that Vt
There is a problem that the controllability of h is poor.
【００１１】本発明は、上記の点に鑑みなされたもの
で、その目的は、Ｖｔｈの制御性と絶縁耐性を兼ね備え
るゲート絶縁膜を形成したＭＯＳ型半導体装置および、
その製造方法を提供することにある。The present invention has been made in view of the above points, and an object thereof is a MOS type semiconductor device having a gate insulating film having both Vth controllability and insulation resistance, and
It is to provide the manufacturing method.
【００１２】[0012]
【課題を解決するための手段】本発明のＭＯＳ型半導体
装置は、ゲート電極端部直下のゲート絶縁膜中の窒素濃
度を高くし、ゲート電極中央部（チャネル領域直上）の
ゲート絶縁膜中の窒素濃度を低くすることで、上記のよ
うに優れた特性を有するゲート絶縁膜を設けたものであ
る。また、本発明のＭＯＳ型半導体装置の製造方法は、
上記ゲート絶縁膜を形成するために、ゲートエッジに窒
素イオンを導入するようにしたものである。In the MOS semiconductor device of the present invention, the nitrogen concentration in the gate insulating film immediately below the end of the gate electrode is increased so that the gate insulating film in the central portion (immediately above the channel region) of the gate electrode is formed. By lowering the nitrogen concentration, the gate insulating film having excellent characteristics as described above is provided. Further, the method for manufacturing a MOS semiconductor device of the present invention is
In order to form the gate insulating film, nitrogen ions are introduced at the gate edge.
【００１３】すなわち、請求項１に記載のＭＯＳ型半導
体装置は、半導体基板上に第１導電型半導体からなるド
レイン領域およびソース領域と、これらの領域間にチャ
ネル領域と、このチャネル領域の表面にゲート絶縁膜
と、このゲート絶縁膜上にゲート電極とを有するＭＯＳ
型半導体装置において、ゲート絶縁膜のうちゲート電極
端部直下の部分に含まれる窒素原子濃度が、ゲート絶縁
膜のうちゲート電極中央部直下の部分に含まれる窒素原
子濃度に比べて高いことを特徴とする。That is, in the MOS semiconductor device according to the first aspect, the drain region and the source region made of the first conductivity type semiconductor are formed on the semiconductor substrate, the channel region is provided between these regions, and the surface of the channel region is formed. MOS having a gate insulating film and a gate electrode on the gate insulating film
-Type semiconductor device is characterized in that the concentration of nitrogen atoms contained in the portion of the gate insulating film directly below the end of the gate electrode is higher than the concentration of nitrogen atoms contained in the portion of the gate insulating film directly below the central portion of the gate electrode. And
【００１４】請求項２に記載のＭＯＳ型半導体装置は、
請求項１において、ゲート絶縁膜のうちゲート電極端部
直下の部分に含まれる窒素原子濃度が３．０原子％以上
であることを特徴とする。A MOS type semiconductor device according to a second aspect is
In Claim 1, the nitrogen atom concentration contained in the portion of the gate insulating film immediately below the end of the gate electrode is 3.0 atomic% or more.
【００１５】請求項３に記載のＭＯＳ型半導体装置の製
造方法は、請求項１に記載のＭＯＳ型半導体装置を製造
する方法であって、半導体基板上にゲート絶縁膜と、該
ゲート絶縁膜上にゲート電極とを形成し、これらゲート
絶縁膜上およびゲート電極上からゲート絶縁膜および、
ゲート絶縁膜と半導体基板との界面に窒素イオンをイオ
ン注入法により導入した後、熱酸化処理またはアニール
処理を施すことを特徴とする。A method of manufacturing a MOS type semiconductor device according to a third aspect is the method of manufacturing a MOS type semiconductor device according to the first aspect, wherein the gate insulating film is formed on the semiconductor substrate, and the gate insulating film is formed on the gate insulating film. A gate electrode on the gate insulating film and the gate insulating film from above the gate electrode,
The method is characterized in that nitrogen ions are introduced into the interface between the gate insulating film and the semiconductor substrate by an ion implantation method, and then thermal oxidation treatment or annealing treatment is performed.
【００１６】請求項４に記載のＭＯＳ型半導体装置の製
造方法は、請求項３においてイオン注入法による窒素イ
オンの導入を、回転斜め注入法を用いて行うことを特徴
とする。According to a fourth aspect of the present invention, there is provided a method of manufacturing a MOS type semiconductor device, wherein the introduction of nitrogen ions by the ion implantation method is performed by using the rotary oblique implantation method.
【００１７】本発明に係るＭＯＳ型半導体装置では、ゲ
ート電極エッジ部のゲート絶縁膜の窒素濃度を、ゲート
電極中央部直下のゲート絶縁膜（チャネル領域のゲート
絶縁膜）の窒素濃度よりも高くしたことで絶縁耐性が向
上し、かつＶｔｈの制御性が良いゲート絶縁膜を形成す
ることができる。In the MOS semiconductor device according to the present invention, the nitrogen concentration of the gate insulating film at the edge portion of the gate electrode is made higher than the nitrogen concentration of the gate insulating film (gate insulating film in the channel region) immediately below the central portion of the gate electrode. As a result, it is possible to form a gate insulating film having improved insulation resistance and good Vth controllability.
【００１８】本発明に係るＭＯＳ型半導体装置の製造方
法では、ゲート電極エッジ部のゲート絶縁膜に窒素をイ
オン注入法で導入するため、ゲート絶縁膜における最適
な窒素濃度分布の形成が可能となる。そのうえ、Ｈ原子
が導入されないので、高温の熱処理を施すことなく高信
頼性、かつ高性能のゲート絶縁膜を提供することができ
る。In the method of manufacturing the MOS semiconductor device according to the present invention, nitrogen is introduced into the gate insulating film at the edge of the gate electrode by the ion implantation method, so that the optimum nitrogen concentration distribution in the gate insulating film can be formed. . Moreover, since H atoms are not introduced, it is possible to provide a highly reliable and high performance gate insulating film without performing high temperature heat treatment.
【００１９】[0019]
【実施例】次に、本発明に係るＭＯＳ型半導体装置の製
造方法の実施例を、図面を参照して説明する。 実施例 図１は、この製造方法を工程順に示す断面図である。Ｐ
型シリコン基板１上に膜厚１０〜４０ｎｍの保護酸化膜
を、次いで膜厚８０〜１５０ｎｍの窒化シリコン膜を積
層し、フォトリソグラフィー技術およびエッチング技術
でパターニングし、窒化シリコン膜をマスクにして膜厚
４００〜８００ｎｍのフィールド酸化膜を形成した。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a method for manufacturing a MOS type semiconductor device according to the present invention will be described with reference to the drawings. Example FIG. 1 is a sectional view showing this manufacturing method in order of steps. P
A protective oxide film having a film thickness of 10 to 40 nm and then a silicon nitride film having a film thickness of 80 to 150 nm are laminated on the type silicon substrate 1 and patterned by a photolithography technique and an etching technique. A field oxide film of 400 to 800 nm was formed.
【００２０】窒化シリコン膜および保護酸化膜をウエッ
トエッチングで除去した後、８５０〜９５０℃のウエッ
ト酸化工程により、図１（Ａ）に示すように膜厚８〜２
０ｎｍのゲート酸化膜（ゲート絶縁膜）２を形成した。
３はフィールド酸化膜である。なお、ゲート酸化膜２に
代えて、９５０〜１０５０℃のＮ2 Ｏ，Ｏ2 混合ガス雰
囲気中でＲＴＰ法（Rapid Thermal Process ）で処理す
ることにより、膜厚８〜２０ｎｍのオキシナイトライド
膜を形成してもよい。After removing the silicon nitride film and the protective oxide film by wet etching, a wet oxidation process at 850 to 950 ° C. is performed to obtain a film thickness of 8 to 2 as shown in FIG.
A 0 nm gate oxide film (gate insulating film) 2 was formed.
3 is a field oxide film. Instead of the gate oxide film 2, an oxynitride film having a thickness of 8 to 20 nm is formed by performing the RTP method (Rapid Thermal Process) in an N 2 O, O 2 mixed gas atmosphere at 950 to 1050 ° C. You may form.
【００２１】ゲート酸化膜２、フィールド酸化膜３の全
面に膜厚２００〜４００ｎｍのポリシリコン膜を積層し
た後、熱拡散法によりリンをポリシリコン中に拡散させ
て低抵抗化させた。図１（Ｂ）に示すように、フォトリ
ソグラフィー技術およびエッチング技術にでパターニン
グした。４はポリシリコン（ゲート電極）、５はフォト
レジストである。After depositing a polysilicon film having a film thickness of 200 to 400 nm on the entire surfaces of the gate oxide film 2 and the field oxide film 3, phosphorus was diffused into the polysilicon by a thermal diffusion method to reduce the resistance. As shown in FIG. 1B, patterning was performed by a photolithography technique and an etching technique. Reference numeral 4 is polysilicon (gate electrode), and 5 is a photoresist.
【００２２】図１（Ｃ）に示すように、フォトレジスト
５を除去した後、ゲート酸化膜２およびポリシリコン４
の上方から窒素イオン６を回転斜め注入法によりイオン
注入した。この場合、注入エネルギーを５〜２０ｋｅ
Ｖ、ドーズ量を１〜５Ｅ１４ｃｍ-2、注入角度を１０〜
４０°とした。その後、８５０〜９５０℃のＮ2 Ｏ雰囲
気中で酸化処理（または８５０〜９５０℃のＮ2 雰囲気
中でアニール処理）を施した。これにより、ゲート酸化
膜２のうち露出部分および、ポリシリコン４の端部直下
の部分を窒化酸化膜７に変え、この窒化酸化膜７に含ま
れる窒素原子濃度を３．０原子％以上とした。ゲート酸
化膜２のうちポリシリコン４の中央部直下部分は、ゲー
ト酸化膜のままにした。すなわち、図１（Ｃ）において
Ｒ1 ，Ｒ2 の部分は窒化酸化膜７とし、Ｒ3 の部分はゲ
ート酸化膜２のままとした。As shown in FIG. 1C, after removing the photoresist 5, the gate oxide film 2 and the polysilicon 4 are removed.
Nitrogen ions 6 were ion-implanted from above by a rotary oblique implantation method. In this case, the implantation energy is 5 to 20 ke
V, dose amount 1-5E14 cm -2 , implantation angle 10-
40 °. Then, an oxidation treatment (or an annealing treatment in an N 2 atmosphere at 850 to 950 ° C.) was performed in an N 2 O atmosphere at 850 to 950 ° C. As a result, the exposed portion of the gate oxide film 2 and the portion immediately below the end of the polysilicon 4 were changed to the nitride oxide film 7, and the nitrogen atom concentration contained in the nitride oxide film 7 was set to 3.0 atom% or more. . The portion of the gate oxide film 2 immediately below the central portion of the polysilicon 4 was left as the gate oxide film. That is, in FIG. 1C, the portions of R 1 and R 2 are the nitride oxide film 7, and the portion of R 3 is the gate oxide film 2.
【００２３】図１（Ｄ）に示すようにソース領域８の拡
散層および、ドレイン領域９の拡散層をイオン注入と、
その後の熱処理で形成し、ＣＶＤ技術、フォトリソグラ
フィ技術ーおよびエッチング技術でコンタクト孔、次い
でメタル配線１０を形成してＭＯＳ半導体装置を得た。
なお、１１はポリメタ層間膜である。As shown in FIG. 1D, the diffusion layer of the source region 8 and the diffusion layer of the drain region 9 are ion-implanted,
It was formed by subsequent heat treatment, and a contact hole and then a metal wiring 10 were formed by a CVD technique, a photolithography technique and an etching technique to obtain a MOS semiconductor device.
Reference numeral 11 is a polymeta-interlayer film.
【００２４】[0024]
【発明の効果】以上の説明で明らかなように、本発明の
ＭＯＳ型半導体装置は、例えば、ゲート絶縁膜のうちゲ
ート電極端部直下の部分からフィールド酸化膜直近の部
分までを窒化酸化膜とすることにより、この窒化酸化膜
に含まれる窒素原子濃度を、ゲート絶縁膜のうちゲート
電極の中央部直下の部分に含まれる窒素原子濃度に比べ
て高くしたものである。このため本発明のＭＯＳ型半導
体装置におけるゲート絶縁膜では、絶縁耐性およびホッ
トキャリア劣化耐性が向上すると同時に、Ｖｔｈ制御性
および移動度が高まる。また、半導体基板中に導入され
た窒素イオンはソース、ドレインの拡散層の拡がりを抑
制することができる。このように、本発明によれば、特
性の優れたＭＯＳ型半導体装置を提供することができ
る。As is apparent from the above description, in the MOS semiconductor device of the present invention, for example, a portion of the gate insulating film immediately below the end of the gate electrode to a portion immediately adjacent to the field oxide film is referred to as a nitride oxide film. By doing so, the concentration of nitrogen atoms contained in this oxynitride film is made higher than the concentration of nitrogen atoms contained in the portion of the gate insulating film immediately below the central portion of the gate electrode. Therefore, in the gate insulating film in the MOS semiconductor device of the present invention, the insulation resistance and the hot carrier deterioration resistance are improved, and at the same time, the Vth controllability and the mobility are improved. Further, the nitrogen ions introduced into the semiconductor substrate can suppress the spread of the diffusion layers of the source and drain. As described above, according to the present invention, it is possible to provide a MOS semiconductor device having excellent characteristics.
【図１】ＭＯＳ型半導体装置の製造方法の実施例に係る
もので、この製造方法を工程順に示す断面図である。FIG. 1 is a cross-sectional view showing an example of a method for manufacturing a MOS semiconductor device and showing the manufacturing method in the order of steps.
１ Ｐ型シリコン基板 ２ ゲート酸化膜 ３ フィールド酸化膜 ４ ポリシリコン ５ フォトレジスト ６ 窒素イオン ７ 窒化酸化膜 ８ ソース領域 ９ ドレイン領域 １０ メタル配線 １１ ポリメタ層間膜 1 P-type silicon substrate 2 Gate oxide film 3 Field oxide film 4 Polysilicon 5 Photoresist 6 Nitrogen ion 7 Nitric oxide film 8 Source region 9 Drain region 10 Metal wiring 11 Poly meta interlayer film
Claims (4)
るドレイン領域およびソース領域と、これらの領域間に
チャネル領域と、このチャネル領域の表面にゲート絶縁
膜と、このゲート絶縁膜上にゲート電極とを有するＭＯ
Ｓ型半導体装置において、ゲート絶縁膜のうちゲート電
極端部直下の部分に含まれる窒素原子濃度が、ゲート絶
縁膜のうちゲート電極中央部直下の部分に含まれる窒素
原子濃度に比べて高いことを特徴とするＭＯＳ型半導体
装置。1. A drain region and a source region made of a first conductivity type semiconductor on a semiconductor substrate, a channel region between these regions, a gate insulating film on the surface of the channel region, and a gate on the gate insulating film. MO with electrodes
In the S-type semiconductor device, the concentration of nitrogen atoms contained in the portion of the gate insulating film immediately below the end of the gate electrode is higher than the concentration of nitrogen atoms contained in the portion of the gate insulating film immediately below the central portion of the gate electrode. Characteristic MOS type semiconductor device.
直下の部分に含まれる窒素原子濃度が３．０原子％以上
であることを特徴とする請求項１に記載のＭＯＳ型半導
体装置。2. The MOS semiconductor device according to claim 1, wherein the nitrogen atom concentration contained in the portion of the gate insulating film immediately below the end portion of the gate electrode is 3.0 atom% or more.
製造する方法であって、半導体基板上にゲート絶縁膜
と、該ゲート絶縁膜上にゲート電極とを形成し、これら
ゲート絶縁膜上およびゲート電極上からゲート絶縁膜お
よび、ゲート絶縁膜と半導体基板との界面に窒素イオン
をイオン注入法により導入した後、熱酸化処理またはア
ニール処理を施すことを特徴とするＭＯＳ型半導体装置
の製造方法。3. The method for manufacturing a MOS semiconductor device according to claim 1, wherein a gate insulating film and a gate electrode are formed on the semiconductor substrate, and the gate insulating film is formed on the gate insulating film. And a method of manufacturing a MOS semiconductor device characterized by performing thermal oxidation treatment or annealing treatment after introducing nitrogen ions into the gate insulating film from above the gate electrode and at the interface between the gate insulating film and the semiconductor substrate by an ion implantation method. Method.
入を、回転斜め注入法を用いて行うことを特徴とする請
求項３に記載のＭＯＳ型半導体装置の製造方法。4. The method for manufacturing a MOS type semiconductor device according to claim 3, wherein the introduction of nitrogen ions by the ion implantation method is performed by using a rotary oblique implantation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7236147A JPH0964362A (en) | 1995-08-21 | 1995-08-21 | MOS type semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7236147A JPH0964362A (en) | 1995-08-21 | 1995-08-21 | MOS type semiconductor device and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0964362A true JPH0964362A (en) | 1997-03-07 |
Family
ID=16996459
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7236147A Pending JPH0964362A (en) | 1995-08-21 | 1995-08-21 | MOS type semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0964362A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0887842A1 (en) * | 1997-06-25 | 1998-12-30 | Lucent Technologies Inc. | Field effect devices with improved gate insulator and method of manufacturing the same |
| KR100353402B1 (en) * | 1999-04-19 | 2002-09-18 | 주식회사 하이닉스반도체 | Method of fabricating a semiconductor device |
| US6979658B2 (en) | 1997-03-06 | 2005-12-27 | Fujitsu Limited | Method of fabricating a semiconductor device containing nitrogen in a gate oxide film |
| US7119408B2 (en) | 2004-04-13 | 2006-10-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2012204648A (en) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | Field effect transistor and manufacturing method of the same |
| CN110571266A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | FINFET device and preparation method thereof |
-
1995
- 1995-08-21 JP JP7236147A patent/JPH0964362A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6979658B2 (en) | 1997-03-06 | 2005-12-27 | Fujitsu Limited | Method of fabricating a semiconductor device containing nitrogen in a gate oxide film |
| US7005393B2 (en) | 1997-03-06 | 2006-02-28 | Fujitsu Limited | Method of fabricating a semiconductor device containing nitrogen in an oxide film |
| EP0887842A1 (en) * | 1997-06-25 | 1998-12-30 | Lucent Technologies Inc. | Field effect devices with improved gate insulator and method of manufacturing the same |
| KR100353402B1 (en) * | 1999-04-19 | 2002-09-18 | 주식회사 하이닉스반도체 | Method of fabricating a semiconductor device |
| US7119408B2 (en) | 2004-04-13 | 2006-10-10 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
| JP2012204648A (en) * | 2011-03-25 | 2012-10-22 | Toshiba Corp | Field effect transistor and manufacturing method of the same |
| CN110571266A (en) * | 2018-06-05 | 2019-12-13 | 中芯国际集成电路制造(上海)有限公司 | FINFET device and preparation method thereof |
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