JPH0964668A - Amplifier with automatic gain control circuit - Google Patents

Abstract

It is possible to avoid the problem that the output amplitude of the preamplifier becomes abnormally large in the packet start time region when a high-speed burst signal is received. An amplifier of a main signal system for amplifying an input signal,
An impedance variable circuit that is connected in parallel to the amplifier and that divides the input signal to the amplifier and an automatic gain control circuit that changes the impedance of the impedance variable circuit to control the divided flow rate of the input current. , Outputting an error between the output level of the amplifier and a predetermined level
Second control system having a first control system having an error amplifier, a peak detector for detecting a peak level of the output of the amplifier, and a second error amplifier outputting an error between the output of the peak detector and a predetermined level. The output of the first control system in the time domain in which the head signal of 1 or more bits of the input signal is input, and the output of the second control system in areas other than the time domain in which the head signal is input. Controls the impedance of the variable impedance circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical receiver circuit used for optical fiber communication or the like, and more particularly to an amplifier having an automatic gain control circuit for the optical receiver circuit.

[0002]

2. Description of the Related Art Optical fiber communication is being developed from a trunk system to a network (subscriber system, LAN, intra-device data transmission, etc.). In the network, in addition to the one-to-one communication between the transmission side and the reception side, one-to-many, many-to-one, or many-to-many signal transmission / reception is required.

Therefore, not only the continuous signal but also the continuous signal shown in FIG.
It is required to be able to handle burst signals as shown in (1). In addition, since the transmission paths between the devices in the network vary widely, the intensity of the optical signal received by a certain device may change significantly each time the transmission source is switched. Therefore,
An optical receiver circuit used in a network type optical communication system is required to have two requirements, that is, a wide dynamic range and the ability to handle burst signals at the same time.

Many optical receiver circuits having a wide dynamic range have already been announced. Many of them are shown in Figure 1.
The configuration is as shown in FIG. That is, depending on the magnitude of the current amplitude input to the preamplifier 1, the feedback circuit 2 formed of a feedback resistor and the bypass transistor 3 arranged in parallel with the feedback circuit 2 are turned on / off to shunt the input current.

Thus, the output voltage amplitude of the preamplifier 1 can be supplied through the output buffer amplifier 4 within the input voltage range of the main amplifier. The control of the amount of current shunted by the bypass transistor 3 is performed by the automatic gain control (AGC) circuit 5.

The AGC circuit 5 detects the signal amplitude from the main signal system circuit of the preamplifier 1, and the bypass transistor 3
Change the resistance value of. When the amplitude of the current input to the preamplifier 1 is small, the bypass transistor 3 is turned off (the resistance value of the bypass transistor 3 is large) to increase the transimpedance gain of the preamplifier 1.

When the current amplitude input to the preamplifier 1 is large, the bypass transistor 3 is turned on (the resistance value of the bypass transistor 3 is small) to reduce the transimpedance gain of the preamplifier 1.

The burst signal has a different amplitude for each packet as shown in FIG. 10 mentioned above, and the time when the head signal of each packet is input to the receiving circuit is not completely periodic. Therefore, in the burst signal preamplifier, the AGC circuit 5 of FIG. 11 operates instantaneously at the beginning of the packet,
It is necessary to return to the initial state (state in which the bypass transistor 3 is off) after the end of the packet.

A conventional burst signal preamplifier is an AG
A peak detection circuit was often used for the C circuit 5. An example of the circuit configuration is shown in FIGS. In FIG. 12, the peak detector 50 and the error amplifier 51 are connected in series, and the reset circuit 52 resets the peak detector 50 at the input timing of the reset signal. In the case of FIG. 12, the reset circuit 52 is used to return the output of the peak detection circuit to the initial state after the end of the packet. The bypass transistor 3 is turned off by the input of the reset signal.

FIG. 13 shows an example in which only the error amplifier 51 is used. When the difference between the branch output of the main signal system and the predetermined reference value becomes large, an output that can switch the bypass transistor 3 to the ON state is generated.

[0011]

The preamplifier using the conventional AGC circuit shown in FIGS. 12 and 13 can basically receive a burst signal having a wide dynamic range. However, the AG of FIG. 12 using the peak detector 50
In the C circuit, it takes time to detect the signal amplitude and stabilize the resistance value of the bypass transistor 3.

This is because a capacitor is used in the peak detector 50, and it takes time to charge the capacitor. Therefore, when the speed of the burst signal becomes high, the peak detection circuit cannot follow the large amplitude input signal. For this reason, the conventional A shown in FIG.
Output waveform of preamplifier using GC circuit [Fig.
In (a)], the output amplitude of the preamplifier 1 becomes abnormally large at the leading bit of the packet.

If the output amplitude of the preamplifier 1 becomes abnormally large, the main amplifier in the next stage cannot normally perform the identification operation, and the entire receiving circuit malfunctions, which is a serious problem.

Further, FIG. 13 using only the error amplifier 51.
In the AGC circuit of FIG. 14, the transimpedance gain of the entire preamplifier changes for each bit of the signal, and the response time difference between the error amplifier 51 and the main signal system circuit causes
As shown in (b), the output waveform of the preamplifier pulsates in all bits. Therefore, since the transmission data is included in the time region excluding the vicinity of the first bit of the burst signal packet, if a pulsation occurs in this region, the error rate of data reproduction becomes high, which is a serious problem.

From the above point of view, the object of the present invention is to avoid the problem that the output amplitude of the preamplifier becomes abnormally large in the head time region of a packet when a high-speed burst signal is received, and at the same time, to the data time region of the packet. It is an object of the present invention to provide an amplifier having a new automatic gain control (AGC) circuit for preventing the output waveform from pulsating.

[0016]

An amplifier having an automatic gain control circuit according to the present invention which achieves the above object has, as a basic configuration, a main signal amplifier for amplifying an input signal and a parallel connection to the amplifier. And an automatic gain control circuit for controlling the divided flow rate of the input current by varying the impedance variable circuit for shunting the input signal to the amplifier and the impedance of the variable impedance circuit. A first control system having a first error amplifier that outputs an error between an output level and a predetermined level, and a peak detector that detects a peak level of the output of the amplifier, and an error between the output of the peak detector and the predetermined level And a second control system having a second error amplifier that operates in the time domain in which the leading signal of one or more bits of the input signal is input.
The output of the second control system controls the impedance of the impedance variable circuit by the output of the control system and in the area other than the time domain in which the head signal is input.

With this structure, even when a high-speed input burst signal is received for a burst signal, the problem that the output amplitude of the preamplifier becomes abnormally large in the head time region of the packet is avoided, and the packet It is possible to prevent the output waveform from pulsating in the data time domain.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the same or similar components in the drawings will be described with the same numerals and numbers.

FIG. 1 shows the principle configuration of the AGC circuit of the present invention. The AGC circuit of the present invention has two control circuits, a high-speed control system including only the error amplifier 501 and a peak detection system in which the peak detector 500 and the error amplifier 502 are connected in series.

The high-speed control system operates in the time domain near the first bit of the burst signal packet, and the peak detection system operates in the other time domains. To switch between the high speed control system and the peak detection system, the timing circuit 5 is operated by setting the first switch 503 and the second switch 504 placed in the subsequent stage of each system.
It is performed by controlling with the output of 06.

The timing circuit 506 inputs the time when the first bit is input based on the information of the output amplitude a from the branch terminal of the main signal system, the output amplitude b of the peak detection circuit 500, and the output amplitude c of the reset circuit 507. Detection and switch 50
The time for switching 3 and 504 is set.

The above operation will be further described with reference to FIGS. In FIG. 2, the first and second switches 503, 5 are shown.
04 transition state and the state of the peak detector 500. FIG. 3 shows a time chart of the data input and the reset signal. In FIG. 3A, the data input has a preamble portion I and a data portion II.

Further, in FIG. 3B, the periods p1 to p4 are shown in correspondence with the above data input. Of these,
p1 is the timing of the reset signal. Also p1 to p
The first and second switches 50 shown in FIG.
The operations of 3, 504 and the peak detector 500 are associated with the same reference number.

Referring to FIGS. 2 and 3, when the reset signal is input p1, the reset circuit 507 causes the capacitance (not shown) in the peak detector 500 to be discharged. At this time, the first switch 503 is turned on,
The second switch 504 is turned off, and the output of the high speed control system is enabled. The output of this system controls the bypass transistor 3 (see FIG. 12).

Furthermore, there is no input signal in the time domain p2 (see FIG.
In the reference), the states of the first and second switches 503 and 504 do not change, and the peak detector 500 detects that the signal is at the zero level.

Further, when the data input reaches the preamble I (area p3) at the beginning of the packet, the peak detector 500 is in the charging state. When the charging is completed, the states of the first and second switches 503 and 504 are reversed, the first switch 503 is turned off and the second switch 504 is turned on.

Next, when the data area p4 is reached, the peak detector 500 detects the peak level of the signal. Therefore, the conduction of the bypass transistor 3 is controlled by the output of the second switch 504, that is, the output of the peak detection system.

FIG. 4 shows the effect obtained by the present invention having the above-mentioned principle configuration, and is an output waveform of a preamplifier using the AGC circuit of the present invention. Input signal speed is 156
Mb / s. When the input current is small (5 μA or less in the example in FIG. 4), the signal amplitude from the branch terminal of the main signal system is small, so the first switch 503 is turned on and the second switch 504 is turned on in the entire time region. Turns off.

Therefore, the control system of only the error amplifier 501 is connected to the bypass transistor 3, but the control signal amplitude is small and the output waveform of the preamplifier 1 is AGC.
It is almost the same as when there is no circuit.

On the other hand, when the input current becomes large (20 μA or more in the example in FIG. 4), the switch 1 is turned on and the switch 2 is turned on near the leading bit by the action of the timing circuit 506.
Is turned off, and the switch 1 is turned off and the switch 2 is turned on in the time region after the third bit. As a result, the high-speed control system operates near the leading bit and suppresses overshoot of the output waveform of the preamplifier 1.

The peak detection system starts charging from the first bit, and almost completes charging from the second bit onward and reaches a constant control voltage. Therefore, a stable output waveform without pulsation can be obtained from the third bit onward, which is switched to the peak detection system.

FIG. 5 shows a first embodiment of the present invention.
In this embodiment, the timing circuit 506 is connected to the comparator 52.
6, a delay circuit 536, and an inverter 546. The input of the error amplifier 501 (in FIG. 5) and the output voltage of the peak detector 500 (in FIG. 5) are input to the comparator 526.

When no packet signal is input to the preamplifier 1 (phases P1 and P2), the input voltage from the branch output terminal of the main signal system to the error amplifier 501 is the peak detector 50.
An offset is given so that it is larger than the voltage from 0. Therefore, the output of the comparator 526 becomes LOW level, and since the inverter 546 is present, the first switch 503 is turned on and the second switch 504 is turned off.

When the packet signal is input to the preamplifier 1 and the voltage from the peak detector 500 becomes larger than the input voltage to the error amplifier 501 (phases P3 and P4), the output of the comparator 526 is HIGH level, the first level. Switch 5
03 is turned off and the second switch 504 is turned on.

However, the delay circuit 536 adjusts the time difference between the ON / OFF switching of the first switch 503 and the second switch 504 after the output of the comparator 526 becomes HIGH level.

This time difference is set longer than the time required for the peak detector 500 to start charging and reach the peak value of the signal. Further, it is set shorter than the time of the preamble bit area I (see FIG. 3) provided at the beginning of the packet signal.

When the packet signal ends and the reset signal is input to the reset circuit 507, the peak detector 500 starts discharging and the output voltage of the peak detector 500 becomes smaller than the voltage (see phase P1 in FIG. 6). .

As a result, the output of the comparator 526 becomes LOW.
Level, switch 1 is on, switch 2 is off,
The AGC circuit returns to the initial state. Also in this case, the comparator 5
A delay circuit 536 causes a time lag until the first switch 503 and the second switch 504 are switched on and off after the output of the switch 26 goes high. This time difference needs to be shorter than the time domain (guard bit domain) between packets. This is because when the time difference is longer than the guard bit area, the peak detection system AGC circuit is still connected to the bypass transistor 3 in the first bit of the next packet, so that the output waveform of the preamplifier 1 has an overshoot. This is because it occurs.

Therefore, the maximum set value of the delay time in the delay circuit 536 is limited by the shorter time of the preamble bit area and the guard bit area.

The AGC circuit of FIG. 5 can realize the preamplifier characteristic equivalent to that described with reference to FIG. 4 by the above operation. Further, in order to prevent erroneous ON / OFF operation of the first and second switches 503 and 504 in the data area of the packet signal, the comparator 526 uses a comparator having a hysteresis characteristic. The delay circuit 536 can be realized using an analog circuit in which a transistor, a resistor, and a capacitor are combined, or a digital circuit such as a flip-flop using a clock signal.

FIG. 7 shows a second embodiment of the present invention.
In this embodiment, the timing circuit 506 uses a comparator 526, a delay circuit 536, an inverter 546, and a reference voltage generation circuit 516, as in the first embodiment. The operation is basically the same as the operation description (FIG. 6) of the embodiment of FIG. 5 except that the reference voltage generation circuit 516 is provided.

In FIG. 7, the comparator 526 receives the voltage from the reference voltage generation circuit 516 (shown in FIG. 7) and the voltage from the peak detector (shown in FIG. 7). When the packet signal is not input to the preamplifier 1, the output voltage of the reference voltage generation circuit 516 is applied so that the voltage becomes higher than the voltage, and the output of the comparator 526 is LOW level.
The first switch 503 is turned on and the second switch 504 is turned off.

When the packet signal is input to the preamplifier 1 and the voltage becomes higher than the voltage, the output of the comparator 526 is HIGH level, the first switch 503 is off and the second switch 504 is on. However, the delay circuit 536
After the output of the comparator 526 becomes HIGH level, the time difference is set until the ON / OFF of the first switch 503 and the second switch 504 is switched.

This time difference is longer than the time required for the peak detector 500 to start charging and reach the peak value of the signal. Also, it is set shorter than the time of the preamble bit area provided at the beginning of the packet signal.

When the packet signal ends and the reset signal is input, the peak detector 500 starts discharging and the voltage becomes lower than the voltage. As a result, the output of the comparator 526 is at LOW level, the first switch 503 is on, the second switch 504 is off, and the AGC circuit returns to the initial state.

Also at this time, the delay circuit 536 causes a time difference until the switch is switched after the output of the comparator 526 becomes the HIGH level. This time difference needs to be shorter than the time domain (guard bit domain) between packets. This is because when the time difference is longer than the guard bit area, the peak detection system AGC circuit is still connected to the bypass transistor 3 in the first bit of the next packet, so that the output waveform of the preamplifier 1 has an overshoot. This is because it occurs.

Therefore, the maximum setting value of the delay time in delay circuit 536 is limited by the shorter one of the preamble bit area and the guard bit area.

With the AGC circuit of FIG. 7 as well, the preamplifier characteristic equivalent to that of FIG. 4 can be realized by the above-described operation. First and second switches 50 in the data area of the packet signal
In order to prevent erroneous ON / OFF operation of 3, 504, a comparator having a hysteresis characteristic is used as compared with a normal comparator.

The delay circuit 536 is formed by using an analog circuit in which a transistor, a resistor and a capacitor are combined, or a digital circuit such as a prep flop using a clock signal.

FIG. 8 shows a third embodiment of the present invention.
In this embodiment mode, the timing circuit 506 shown in FIG.
In addition to the above configuration, the third to sixth switches 561 to 564
And reference voltage generation circuits (A to C) 551 to 553.

In the comparator 526, the voltage from the branch output terminal of the main signal system through the third switch 561 to the first input terminal or the voltage from the reference voltage generating circuit (A) 551 through the fourth switch 562 ( 8) and the voltage of the reference voltage generation circuit (B) 552 or the sixth switch 5 through the fifth switch 563 to the second input terminal thereof.
The voltage (of FIG. 8) from the reference voltage generation circuit (C) 553 is input through 64.

Here, in the configuration of FIG. 8, the output voltage of the reference voltage generation circuit (C) 553 is larger than the output voltage of the reference voltage generation circuit (A) 551 and the output voltage of the reference voltage generation circuit (A) 551. Is a reference voltage generation circuit (B) 55
It is designed to be larger than the output voltage of 2. Further, the output voltage of the reference voltage generation circuit (B) 552 is designed to be higher than the voltage of the branch output terminal of the main signal system when the packet signal is not input to the preamplifier 1.

Referring to the operation explanatory diagram of FIG. 9, when the packet signal is not input to the preamplifier 1 (phase P2 of FIG. 9)
The first switch 503 is turned on and the first switch 5 is turned on.
04 is turned off. Therefore, the third switch 561 is turned on, the fourth switch 562 is turned off, the fifth switch 563 is turned on, and the sixth switch 564 is turned off. At this time, the voltage is higher than the voltage, and the output of the comparator 526 becomes LOW level.

A packet signal is input to the preamplifier 1,
When the voltage of becomes larger than the voltage of (phase P in FIG.
3), the output of the comparator 526 is HIGH level, the first switch 503 is off, and the second switch 504 is on. When the output of the comparator 526 becomes HIGH level, the third switch 561 is turned off and the fourth switch 562 is turned on.

As a result, the reference voltage generating circuit (A) 55
The voltage connected to 1 is the reference voltage generation circuit (B) 55.
It is kept higher than the voltage connected to 2 and the output of the comparator 526 is kept HIGH regardless of whether the signal after the next bit is "0" or "1" (see FIG. 9). Phase P4).

After the output of the comparator 526 becomes HIGH level, the delay circuit 536 is turned off until the first switch 503 is turned off and the second switch 504 is turned on.
Set the time difference by. This time difference is set longer than the time required for the peak detector to start charging and reach the peak value of the signal and shorter than the time of the preamble bit area provided at the beginning of the packet signal. The peak detector 500 starts charging after the packet signal is input to the preamplifier 1 and outputs a stable voltage that reaches the peak value of the signal before the second switch 504 is turned on.

When the packet signal ends and the reset signal is input (phase P1 in FIG. 9), the peak detector 500 starts discharging. Further, within the time when the reset signal is input, the output voltage of the reset circuit 507 becomes HIGH level, the fifth switch 563 is turned off and the sixth switch is turned on.

The voltage is the reference voltage generation circuit (A) 551.
Is greater than the voltage connected to the comparator 526
Output changes to LOW level. As a result, the third switch 561 is turned on and the fourth switch 562 is turned off, but the voltage connected to the branch output terminal of the main signal system is
Since the voltage is lower than the voltage connected to the reference voltage generation circuit (C) 553 (there is no input signal during the guard bit area for inputting the reset signal), the output of the comparator 526 remains at the LOW level.

After a predetermined delay time of the delay circuit 536, the first switch 503 is turned on and the first switch 504 is turned off. This delay time needs to be shorter than the guard bit area. This is because when the delay time is longer than the guard bit area, the AGC circuit of the peak detection system remains connected to the bypass transistor 3 in the first bit of the next packet, so that the output waveform of the preamplifier 1 is overshot. Is generated.

Therefore, the maximum setting value of the delay time in delay circuit 536 is limited by the shorter one of the preamble bit area and the guard bit area.

When the input of the reset signal is completed, the output voltage of the reset circuit 507 becomes the LOW level, the fifth switch 563 is turned on and the sixth switch 564 is turned off, but the reference voltage generation circuit (B) 552. Since the voltage connected to is still higher than the voltage connected to the branch output terminal of the main signal system, the output of the comparator 526 is LOW.
It remains at the level (phase P2 in FIG. 9). Therefore,
Switch 1 is on, switch 2 is off,
The GC circuit returns to the initial state (phase P2 in FIG. 9).

The AGC circuit of FIG. 8 can realize the preamplifier characteristic equivalent to that of FIG. 4 by the above operation. In order to prevent erroneous ON / OFF operation of the switches 1 and 2 in the data area of the packet signal, a comparator having a hysteresis characteristic is used as compared with a normal comparator. The delay circuit 536 is formed using an analog circuit in which a transistor, a resistor, and a capacitor are combined, or a digital circuit such as a flip-flop which uses a clock signal.

[0063]

The embodiments of the present invention have been described above with reference to the drawings. However, according to the present invention, the problem that the output amplitude of the preamplifier becomes abnormally large in the head time region of a packet when a high-speed burst signal is received To provide a new automatic gain control (AGC) circuit for avoiding and preventing the output waveform from pulsating in the data time domain of a packet.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is an operation explanatory diagram of FIG. 1;

FIG. 3 is an operation time chart of FIG.

FIG. 4 is a diagram showing an output waveform of a preamplifier using the AGC circuit of the present invention.

FIG. 5 is a diagram showing a first embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of FIG. 5;

FIG. 7 is a diagram showing a second embodiment of the present invention.

FIG. 8 is a diagram showing a third embodiment of the present invention.

FIG. 9 is an operation explanatory diagram of FIG. 8;

FIG. 10 is a diagram showing an example of a burst signal.

FIG. 11 is an example of a burst signal receiving circuit having a wide dynamic range.

FIG. 12 is a conventional AGC circuit (No. 1).

FIG. 13 is a conventional AGC circuit (No. 2).

FIG. 14 is an output waveform of a preamplifier using a conventional AGC circuit.

[Explanation of symbols]

 1 Main Signal Preamplifier 2 Feedback Circuit 3 Bypass Transistor 4 Output Buffer 5 Automatic Gain Control Circuit 500 Peak Detector 501, 502 Error Amplifier 503, 504, 561-564 Switch 506 Timing Circuit 507 Reset Circuit 516, 551-553 Reference Voltage Generation circuit 526 Comparator 536 Delay circuit 546 Inverter

Claims (7)

[Claims] 1. A main signal system amplifier for amplifying an input signal,
An impedance variable circuit that is connected in parallel to the amplifier and that divides the input signal to the amplifier; and an automatic gain control circuit that changes the impedance of the impedance variable circuit to control the divided flow rate of the input current. The automatic gain control circuit includes a first control system having a first error amplifier that outputs an error between the output level of the amplifier and a predetermined level, a peak detector that detects a peak level of the output of the amplifier, and the peak detector. A second control system having a second error amplifier that outputs an error between the output of the detector and a predetermined level is provided, and the first control unit is provided in the time domain where the head signal of 1 or more bits of the input signal is input. The impedance of the impedance variable circuit is controlled by the output of the second control system by the output of the control system and in the time region other than the time domain where the head signal is input. That amplifier. 2. The first control system according to claim 1, further comprising a first switch on an output side of the first error amplifier, and the second control system includes:
A second switch is provided on the output side of the second error amplifier, and the first switch is transitioned from a cutoff state to a conduction state in a time region where there is no input signal between signal packets, and the second switch is provided. An amplifier characterized in that the switch of the switch is changed from a conductive state to a cutoff state. 3. The timing circuit according to claim 2, further comprising a timing circuit for controlling the timing of conduction and interruption of the first and second switches, the timing circuit comprising the output of the amplifier of the main signal system and the peak. A comparator for comparing the output of the detector, a delay circuit to which the output of the comparator is input, and an inverter connected to the output side of the delay circuit, the output of the delay circuit being the first An amplifier configured to control the conduction / interruption timing of the switch and the output of the inverter to control the conduction / interruption timing of the second switch. 4. The timing circuit according to claim 2, further comprising a timing circuit for controlling the timing of conduction and interruption of the first and second switches, the timing circuit including a reference voltage generation circuit and the reference voltage generation circuit. Of the delay circuit, an inverter connected to the output side of the delay circuit, and a delay circuit to which the output of the comparator is input. An amplifier configured such that an output controls timing of conduction and interruption of the first switch, and an output of the inverter controls timing of conduction and interruption of the second switch. 5. A timing circuit according to claim 2, further comprising a timing circuit for controlling the timing of conduction and interruption of the first and second switches, the timing circuit including first to third reference voltage generation circuits. A comparator having first and second input terminals, a delay circuit to which the output of the comparator is input, and an inverter connected to the output side of the delay circuit, the output of the delay circuit being The output of the inverter is configured to control the timing of conduction and interruption of the first switch, and the output of the inverter is configured to control the timing of conduction and interruption of the second switch, and the output of the inverter is connected to the first input terminal of the comparator. The output signal of the amplifier of the main signal system or the output of the first reference voltage generating circuit is the second signal of the comparator.
An amplifier characterized in that the output of the second or third reference voltage generating circuit is connected to the input terminal of the input terminal according to the state of the input signal. 6. The output voltage of the third reference voltage generating circuit is greater than the output voltage of the first reference voltage generating circuit, and the output voltage of the first reference voltage generating circuit is the output voltage of the first reference voltage generating circuit. The output voltage of the second reference voltage generating circuit is set to be higher than the output voltage, and
The output voltage of the reference voltage generating circuit is set to be larger than the voltage of the output signal of the main signal system amplifier when the input signal is not input. 7. The amplifier according to claim 3, 4, 5, or 6, wherein the comparator has hysteresis in input / output characteristics.