JPH0964775A - High frequency device - Google Patents

Abstract

(57) [Abstract] [Purpose] The present invention relates to a device for receiving and demodulating an RF-converted digital signal, and more particularly to a device for receiving a digital signal by using a CATV network, which is intended for downsizing. is there. An input terminal 1 to which a digitally modulated high frequency signal is input, a tuner section 2 to which the input terminal 1 is connected to one input and the output of a PLL circuit 3 is connected to the other input, and The digital demodulation unit 4 connected to the output of the tuner unit 2 and the output terminal 5 connected to the output of the digital demodulation unit 4 are provided in one metal housing, and are generated by the digital demodulation unit 4. The configuration is such that the PLL circuit 3 is controlled by a signal obtained from the clock frequency.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device for receiving and demodulating an RF-converted digital signal, and more particularly to a high frequency device for receiving a digital signal using a CATV network.

[0002]

2. Description of the Related Art A conventional high frequency device is shown in FIG.
An input terminal 61 to which a digitally modulated high frequency signal is input, and the input terminal 61 is connected to one input and the output of a PLL circuit 62 is connected to the other input for controlling the oscillation frequency of a local oscillator. Tuner section 63
And a digital demodulation section 64 connected to the output of the tuner section 63, and an output terminal 65 connected to the output of the digital demodulation section 64. The digital demodulation unit 64 was mounted in another housing. Also, P
A reference oscillator 66 was connected to the LL circuit 62.

[0003]

However, in such a conventional configuration, a tuner section 63 for converting a high frequency signal into an intermediate frequency signal, and a digital demodulation section for demodulating the intermediate frequency signal output from the tuner section 63 are provided. 64 and has a problem that becomes a really large order has been provided in a separate enclosure.

The present invention is intended to solve such problems and to provide a miniaturized high frequency device.

[0005]

In order to achieve this object, a high-frequency device of the present invention is provided with a tuner section and a digital demodulation section in one metal housing and is generated by the digital demodulation section. The clock frequency is a reference frequency of the PLL circuit.

[0006]

With this configuration, the tuner and the digital signal demodulator are integrated, and the clock supplied to the PLL circuit is generated by the digital demodulator, so that the reference oscillator is not required. Therefore, a miniaturized high frequency device can be provided.

[0007]

An embodiment of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 is a block diagram of a high frequency device according to an embodiment of the present invention. As shown in FIG. 1, the high-frequency device of the present invention includes a first input terminal 1 and a first input terminal 1.
Is connected to one input and the other input for controlling the oscillation frequency of the local oscillator 10 is connected to the PLL.
The tuner section 2 to which the output of the circuit 3 is connected, the digital demodulation section 4 to which the output of the tuner section 2 is connected, the first output terminal 5 and the second output terminal 5 to which the output of the digital demodulation section 4 is connected. The output terminal 6 and the output terminal 6 are provided in one metal housing. And the tuner section 2
For details, refer to the first tuning filter 7 to which the signal from the first input terminal 1 is input, the first amplifier 8 connected to the first tuning filter 7, and the first amplifier 8. The second tuned filter 9 connected thereto, and the mixer 11 having the output of the second tuned filter 9 connected to one input and the output of the local oscillator 10 connected to the other input.
And a second amplifier 1 connected to the output of this mixer 11.
2 and an intermediate frequency filter 13 connected to the output of the second amplifier 12. On the other hand, the digital demodulation unit 4 includes a demodulator 14 to which the output of the intermediate frequency filter 13 is connected, the first output terminal 5 and the second output terminal 6 connected to the demodulator 14, and the second output terminal 6 and the second output terminal 6, respectively. Two input terminals 15 and a clock signal generator 16;
A third output terminal 17 connected to the clock signal generator 16, the output terminal 17 being connected to a third input terminal 18 for providing a reference frequency to the PLL circuit 3 connected to the local oscillator 10. It has been configured.

This high frequency device has specifications of the United States of America. A digitally modulated signal of 50 MHz to 120 MHz is input to an input terminal 1, a mixer 11 converts it to an intermediate frequency of 44 MHz, and a demodulator 14 demodulates it. ,
It outputs to the 1st output terminal 5 and the 2nd output terminal 6. The input signal input to the input terminal 1 is Q
This is a band of 3 MHz per PR-modulated channel, which is a level 7 to 10 dB lower than that of a normal CATV signal.

The operation will be described below. The input signal input from the input terminal 1 is filtered by the first tuning filter 7 to remove unnecessary signals outside the input signal band. The tuning frequency of the first tuning filter 7 is controlled by the tuning voltage supplied from the PLL circuit 3. The output of the first tuning filter 7 is amplified by the first amplifier 8. Here, the gain is controlled by the AGC voltage supplied from the demodulator 14 described later. The output of the first amplifier 8 is
Unwanted signals that are input to the second tuning filter 9 and are outside the input signal band are removed. Here, as in the first tuning filter 7, the tuning frequency is controlled by the tuning voltage supplied from the PLL circuit 3. Second tuning filter 9
The output of is input to one input of the mixer 11. In the mixer 11, the output of the local oscillator 10 is supplied to the other input, mixed, converted into an intermediate frequency, and output. PLL
In the circuit 3, the output of the local oscillator 10 is supplied, the phase is compared with the reference signal of the third output terminal 17 output from the clock signal generator 16 described later, and the tuning voltage is output. This tuning voltage controls the oscillation frequency of the local oscillator 10 and the tuning frequencies of the first tuning filter 7 and the second tuning filter 9. The intermediate frequency signal output from the mixer 11 is further amplified by the second amplifier 12 to remove unnecessary signals by the intermediate frequency filter 13, and then supplied to one input of the demodulator 14. Demodulator 14
A clock signal generator 16 produces a frequency of 36 MHz on the other input of the above, which is output from the third output terminal 17 and is external to the high frequency device (not shown). The synchronous clock signal whose frequency is divided by the frequency divider is supplied through the second input terminal 15. This demodulator 1
At 4, the oscillation frequency of the clock signal generator 16 is controlled, and the supplied intermediate frequency signal is demodulated and output to the first output terminal 5 and the second output terminal 6.

Here, the tuner section 2 and the digital demodulation section 4 each require a power source, and the first amplifier 8 needs to be supplied with the AGC voltage from the demodulator 14, but in the present invention, the tuner is used. Since the unit 2 and the digital demodulation unit 4 are integrated, they may be connected internally,
It is possible to downsize because there is no need to connect terminals to the outside.

Further, the output of the local oscillator 10 is supplied to the PLL circuit 3, and the tuning voltage is generated by comparing the phase of this output with the reference signal and is supplied to the local oscillator 10. This reference signal has conventionally been obtained by adding a crystal oscillator and a capacitive element to the PLL circuit. Since the reference signal is supplied to the PLL circuit 3 from the third input terminal 18 in the present invention, the crystal oscillator and the capacitive element can be eliminated, so that the size can be reduced and the cost can be reduced. Further, this reference signal is the third output terminal 1
A 4 MHz synchronous clock signal output from 7 and frequency-divided to 1/9 by a frequency divider outside the high-frequency device (not shown) is used. Since the reference signal is generated from the received signal by the demodulator 14 as described above, there is also an advantage that an accurate and stable tuning voltage can be supplied without drift due to temperature and humidity.

(Embodiment 2) FIG. 2 is a block diagram of a high frequency device according to a second embodiment of the present invention. The present embodiment is different from the first embodiment only in that the DC-DC converter 19 is connected to the PLL circuit 3 shown in the first embodiment, and the other parts are the same as the first embodiment. Therefore, the DC-DC converter 19 connected to the PLL circuit 3
Only explain. Conventionally, a DC voltage of +30 V is usually used as a power source for the tuning voltage. However, the power supply for the other circuits is a DC voltage such as + 5V or + 9V and cannot be shared, so another power supply terminal was required. In this embodiment, since the DC-DC converter 19 is built in and + 9V supplied to the tuner section 2 is converted to + 30V, another power supply terminal is not required and there is an advantage that the size can be reduced.

FIG. 3 is a perspective view of a high frequency device according to the first embodiment of the present invention. The arrangement in the first embodiment is as follows. That is, the first partition plate 41 that abuts both lateral side faces in the longitudinal direction at the substantially central portion of the rectangular housing 40.
And a tuner section 2 is provided in one of the compartments partitioned by the first partition plate 41, and a second partition plate 42 is provided in the other compartment substantially parallel to the first partition plate 41. The demodulator 14 is provided in order from the compartment side of the tuner unit 2.
And a clock signal generator 16. The input terminal 1 is provided on the tuner portion 2 side of one lateral side surface 40a, and the first output terminal 5, the second output terminal 6, and the third output terminal are provided on the demodulator 14 side of the other lateral side surface 40b. 17 are provided.

This high-frequency device has three oscillators, the local oscillator 10, the clock signal generator 16 and the local oscillator in the demodulator 14, which interfere with each other to generate spurious and give interference. There was a problem. In the present embodiment, the tuner section 2, the digital demodulation section 4, and the clock signal generator 16 are partitioned from each other by the first partition plate 41 and the second partition plate 42, so that there is no interference and no spurious is generated. There is an advantage.

FIG. 4 is a perspective view of a high frequency device according to the second embodiment of the present invention. That is, the first partition plate 41 that abuts both lateral side faces in the longitudinal direction at the substantially central portion of the rectangular housing 40.
And a tuner section 2 is provided in one of the compartments partitioned by the first partition plate, and a second partition plate 42 is provided in the other compartment substantially parallel to the first partition plate 41. , The demodulator 14 in order from the compartment side of the tuner unit 2.
And a clock signal generator 16 are provided on one side surface 4
0a is provided with the input terminal 1 on the side of the tuner section 2 and the other side face 40b is provided with the first output terminal 5, the second output terminal 6, and the third output terminal 17 on the side of the demodulator 14. . A third partition plate 51 is provided substantially parallel to the lateral side surface on the side of the compartment where the tuner section 2 is provided, and one lateral side surface 40a provided with the third partition plate 51 and the input terminal 1 is provided.
The tuner section 2 is mounted in the compartment provided on the side, and the DC-DC converter section 19 is arranged in the compartment provided on the side of the third partition plate 51 and the other lateral side surface 40b. The DC-DC converter section 19 is further surrounded by a ground pattern on the printed circuit board. This will be explained next.

FIG. 5 is a pattern diagram of a printed circuit board according to the second embodiment of the present invention. In the DC-DC converter unit 19 (mounted within the dotted line), the supplied DC voltage is converted into an AC voltage, boosted, and then converted into a DC voltage again. At this time, the harmonics of the converted AC voltage become spurious and cause interference. In this embodiment, the DC-DC converter 19 is connected to the third partition plate 51.
Since it is partitioned by, and is further surrounded by the ground pattern 52 on the printed circuit board, there is an advantage that spurious is not generated.

[0018]

As described above, in the high frequency device of the present invention, the tuner section, the digital demodulation section, and the digital demodulation section are provided in one metal housing and generated by the digital demodulation section. Since the clock frequency is used as the reference frequency of the PLL circuit, the reference oscillator is not required, and a miniaturized high frequency device can be provided.

[Brief description of drawings]

FIG. 1 is a block diagram of a high frequency device according to a first embodiment of the present invention.

FIG. 2 is a block diagram of a high frequency device according to a second embodiment of the present invention.

FIG. 3 is a perspective view of the high frequency device according to the first embodiment of the present invention.

FIG. 4 is a perspective view of a high frequency device according to a second embodiment of the present invention.

FIG. 5 is a pattern diagram of a printed circuit board according to a second embodiment of the present invention.

FIG. 6 is a block diagram of a conventional high frequency device.

[Explanation of symbols]

 1 Input Terminal 2 Tuner Section 3 PLL Circuit 4 Digital Demodulation Section 5 First Output Terminal 6 Second Output Terminal 14 Demodulator 16 Clock Signal Generator 17 Third Output Terminal 18 Third Input Terminal

Claims (4)

[Claims] 1. An input terminal to which a digitally modulated high frequency signal is input, and this input terminal is connected to one input and the output of a PLL circuit is connected to the other input for controlling the oscillation frequency of a local oscillator. The tuner part
A digital demodulation unit connected to the output of the tuner unit and an output terminal connected to the output of the digital demodulation unit are provided in one metal housing, and the clock frequency generated by the digital demodulation unit is A high-frequency device that uses the reference frequency of the PLL circuit. 2. The power source input to the tuner unit is DC-D
The high frequency device according to claim 1, further comprising a DC-DC converter that performs C conversion and supplies the C circuit to the PLL circuit. 3. A rectangular partition is provided with a first partition plate which is in contact with both lateral side faces in the longitudinal direction at a substantially central portion of the rectangular housing, and one compartment is partitioned by the first partition plate, and a tuner part is provided in the other partition chamber. In this compartment, a second partition plate is further provided substantially parallel to the first partition plate, and a digital signal demodulation section and a clock frequency generation circuit are provided in order from the compartment side of the tuner section, and one side The high-frequency device according to claim 1, wherein an input terminal is provided on the side of the tuner section and an output terminal is provided on the other side of the digital signal demodulation section. 4. A rectangular partition is provided with a first partition plate which is in contact with both lateral side surfaces in the longitudinal direction at a substantially central portion of the rectangular housing, and one partition chamber partitioned by the first partition plate is provided with a tuner part and the other partition wall. In this compartment, a second partition plate is further provided substantially parallel to the first partition plate, and a digital signal demodulation section and a clock frequency generation circuit are provided in order from the compartment side of the tuner section, and one side An input terminal is provided on the side of the tuner portion and an output terminal is provided on the other side surface of the digital signal demodulation portion, and a third partition is provided on the side of the compartment where the tuner portion is provided, substantially parallel to the side surface. A plate is provided and this third
The partition section and the input terminal are provided in one compartment on the side surface side, the tuner section is mounted, and the third compartment plate and the other compartment surface on the other side surface side are provided with DC. The high-frequency device according to claim 2, further comprising: a -DC converter section, the DC-DC converter section being further surrounded by a ground pattern on the printed circuit board.