JPH096502A - Serial data transfer circuit - Google Patents

Abstract

PURPOSE: To attain precise signal processing without superposing noises to an integrated circuit or the like for processing video and sound signals even when two microcomputers for serial interfaces are not arranged in the periphery of the integrated circuit or the like. CONSTITUTION: The amplitude of a serial clock CLK and serial data DATA transferred between 1st and 2nd microcomputers 1, 2 can be switched to different amplitude based upon an instruction inputted from a CPU 16 arranged in the 2nd microcomputer 2. When it is necessary to prevent the generation of malfunction in an integrated circuit arranged in the periphery of the microcomputers 1, 2, the amplitude of the seirial clock CLK and serial data DATA can be switched to 2nd small amplitude.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for transferring a serial clock from one microcomputer to another microcomputer and transferring serial data from the other microcomputer to one microcomputer in synchronization with the serial clock. The present invention relates to a serial data transfer circuit suitable for use in.

[0002]

2. Description of the Related Art Generally, a serial clock is transferred from one microcomputer to another microcomputer between two microcomputers, and then a serial of a predetermined bit is transferred from the other microcomputer to one microcomputer in synchronization with the serial clock. There is a system that transfers data and performs predetermined arithmetic processing on the predetermined bit serial data inside one of the microcomputers. In this system, the amplitudes of the serial clock and serial data transferred between both microcomputers depend on the power supply voltage of a buffer or the like provided in the input / output portion for the interface of both microcomputers, and are, for example, 5 volts. It was fixed.

[0003]

The above-mentioned two microcomputers are rarely used alone, and are arranged on a printed circuit board together with other integrated circuits in order to control the operation of some electronic equipment. Mostly used. For example, in the case of video equipment and audio equipment, both microcomputers are arranged on a printed circuit board together with an integrated circuit for processing video or audio signals. However, when a serial clock and serial data having an amplitude of about 5 volts are transferred between both microcomputers on this printed circuit board, noise occurs when the rising and falling edges of the serial clock and serial data change. To do. In particular, when the noise is superimposed on the signal line of the integrated circuit for video and audio signal processing existing around both macrocomputers, the integrated circuit for video and audio signal processing may perform erroneous signal processing. There is a problem that accurate information cannot be transmitted to the listener.

Therefore, according to the present invention, even when two microcomputers for a serial interface are arranged around an integrated circuit for video and audio signal processing, noise is generated in the integrated circuit for video and audio signal processing. An object of the present invention is to provide a serial data transfer circuit that can realize accurate signal processing without superimposing them.

[0005]

The present invention has been made to solve the above-mentioned problems, and is characterized in that the first microcomputer and the second microcomputer are provided with A serial data transfer circuit for transferring a serial clock from a first microcomputer to the second microcomputer and transferring data of a predetermined bit from the second microcomputer to the first microcomputer in synchronization with the serial clock, A first input section to which a serial clock having a first threshold voltage and varying with a first amplitude or a second amplitude smaller than the first amplitude is applied; and the serial having a second threshold voltage lower than the first threshold voltage A second input section to which a clock is commonly applied; and a first output section that sets a predetermined bit of serial data as the first amplitude A second output unit that sets the constant bit of the serial data to the second amplitude; and a control unit that switches outputs of the first and second input units and switches outputs of the first and second output units. A second input unit which is built in the second microcomputer and which has the first threshold voltage and to which the serial data selectively output from the first or second output unit is applied; and the second threshold voltage. A fourth input section to which the serial data selectively output from the first or second output section is applied, a third output section having a serial clock as the first amplitude, and the serial clock as the second amplitude. The amplitude of the selected output of the fourth output section and the first or second output section is discriminated, and the selected serial clock from the third or fourth output section is sent to the second microcomputer based on the discrimination result. A discriminating unit to be applied to the first microcomputer, and the control unit issues an instruction to transfer the serial data from the first microcomputer to the second microcomputer at the second amplitude. A transfer of the serial clock of the second amplitude from the first microcomputer to the second microcomputer by using the determination result of the determination unit, and from the second microcomputer to the second clock in synchronization with the serial clock. The point is that the serial data of the second amplitude is transferred to one microcomputer.

[0006]

According to the present invention, the amplitudes of the serial clock and the serial data transferred between the first and second microcomputers are different based on the instruction from the control unit provided inside the second microcomputer. Amplitude can be switched. Therefore, when it is necessary to prevent the malfunction of the integrated circuits arranged around the first and second microcomputers, the amplitude of the serial clock and the serial data can be set to the small second amplitude.

[0007]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. FIG. 1 is a diagram showing a serial data transfer circuit of the present invention. In FIG. 1, (1) is a first microcomputer, (2) is a second microcomputer, and the first and second microcomputers (1) and (2) are clock output terminals for serial clock CLK transfer ( 3) and a clock input terminal (4) via a clock line (5), and a data line between a data output terminal (6) and a data input terminal (7) for serial data DATA transfer. It is connected via (8).

In the inside of the second microcomputer (2), reference numeral (9) is a buffer (first input section) having the first threshold voltage Vth1 and the first threshold voltage Vth1.
When the power supply of the second microcomputer (2) is 5 volts, it is 1/2, which is 2.5 volts. The input of the buffer (9) is connected to the clock input terminal (4). (10) is a comparator (second input section),
The + (non-inverting input) terminal is connected to the clock input terminal (4), and the- (inverting input) terminal is connected to the connection point of the resistors (11) and (12) connected in series between the power supply Vdd and the ground. A reference voltage is applied. This reference voltage is the second threshold voltage and is set to, for example, 1 volt. The AND gates (13) and (14) and the OR gate (15) form a multiplexer. The output of the buffer (9) is connected to one input of the AND gate (13) and the AND gate (1
The output of the comparator (10) is connected to one input of 4). (16) is the second microcomputer (2)
Which is a CPU for controlling the operation of the AND gate (13)
A control signal e for complementary opening and closing of (14) is output. That is, when the output of the buffer (9) is switched from the OR gate (15), the control signal e becomes logic "1", and conversely, when the output of the comparator (10) is switched from the OR gate (15) and output. e becomes logical "0". Here, even when the amplitudes of the serial clocks applied to the clock input terminal (4) are different, the amplitude output from the OR gate (15) is the same for the buffer (9) and the comparator (10). Therefore, the amplitude is the same (5 volts).

Reference numeral (17) is a buffer (first output section), which has an amplification factor for making the output the first amplitude (5 volts). Further, (18) is also a buffer and has an amplification factor for making the output the second amplitude (2 volts). Serial data of a predetermined bit generated in response to an instruction from the CPU (16) is applied to the inputs of these buffers (17) and (18). Reference numeral (19) is a switching unit for switching the outputs of the buffers (17) and (18) to output from the data output terminal (6). The control signal f generated from the CPU (16) is synchronized with the control signal e and has the same logical value. And the control signal f
Becomes logical "1", the switching unit (19) causes the buffer (1
When the control signal f becomes the logic "0", the switching section (19) switches to the output side of the buffer (18).

On the other hand, inside the first microcomputer (1), reference numeral (20) is a serial clock generating circuit, which generates a serial clock b of 8 cycles by applying the clock signal a. Reference numeral (21) is a latch clock generation circuit, which generates a latch clock c in response to the fall of the clock signal a.
(22) is a buffer (third input section) having the first threshold voltage, the input of which is connected to the data input terminal. (23) is a comparator (fourth input section) having the second threshold voltage, the + terminal is connected to the data input terminal (7), and the-terminal is a resistor (in series) connected between the power supply Vdd and the ground. 24) It is connected to the connection point of (25). (26) is a latch circuit (discrimination unit),
The terminal is connected to the output of the buffer (22), and the latch clock c is applied to the C terminal. AND gate (27)
(28) and the OR gate (29) form a multiplexer (selection unit), one input of the AND gate (27) is connected to the output of the buffer (22), and the AND gate (2
One input of 8) is connected to the output of the comparator (23). Furthermore, the Q terminal output of the latch circuit (26) is directly applied to the other input of the AND gate (27), and A
The other input of the ND gate (28) has a latch circuit (2
The Q terminal output of 6) is inverted and applied. That is, AN
The D gates (27) and (28) complementarily open and close the gates according to the output of the latch circuit (26).

Reference numeral (30) is a buffer (third output section) having an amplification factor with the serial clock b as the first amplitude. Reference numeral (31) is a buffer (fourth output unit), which has an amplification factor with the serial clock b as the second amplitude. (32) is a switching unit, and the buffer (3
One of the outputs 0) and (31) is switched to be output from the clock output terminal (3). The switching of the switching unit (32) is performed by the output of the Q terminal of the latch circuit (26). That is, when the output of the latch circuit (26) is logic "1", the output of the buffer (30) is selected,
When the output of the latch circuit (26) is logic "0", the output of the buffer (31) is selected.

The operation of FIG. 1 configured as above will be described with reference to the time chart of FIG. First, when the first and second microcomputers (1) and (2) are arranged together with an integrated circuit for processing audio or video signals on a printed circuit board inside a video device or an audio device, the first and second microcomputers ( Noise that occurs when the serial clock CLK and the serial data DATA transferred between 1) and 2) change is a problem. Therefore, the serial clock CL between the first and second microcomputers (1) and (2)
It is necessary to reduce the amplitudes of K and the serial data DATA (second amplitude) for transfer. In this case, CP
A program for performing the transfer operation at the second amplitude is set in U (16) in advance. Then, the first and second microcomputers (1) and (2) are activated, and the control signals e and f of logic "0" are generated from the CPU (16). Then
The outputs of the comparator (10) and the buffer (18) are selected. Then, the serial data is going to be derived from the data output terminal (6) via the buffer (18) and the switching unit (19) inside the second microcomputer (2), but the serial data is still output from the first microcomputer (1). Since the serial clock CLK of is not transferred to the second microcomputer (2), the serial data is in an indeterminate state. Here, when the serial data is in an uncertain state, it is assumed that the high level state of the amplitude continues. The output of the buffer (18) is an output of 2 volt in which the logic "1" is 2 volt and the logic "0" is 0 volt, but as described above, it changes to 2 volt at this point. There is no such thing. The serial data DATA in this state is transferred to the first via the data input terminal (7).
When applied to the buffer (22) inside the microcomputer (1), the logic "1" level of the serial data DATA does not reach the first threshold voltage (2.5 volts) of the buffer (22). The output of 22) becomes low level.

When the latch clock c is generated in synchronization with the fall of the clock signal a, the buffer (22)
Is latched by the latch circuit (26), the output of the latch circuit (26) becomes low level, and the AND gate (2
8) opens the gate. That is, the serial data DATA is output after being compared with the reference voltage of 1 volt by the comparator (23) and output from the OR gate (29) via the AND gate (28). On the other hand, the switching unit (32) is switched to the buffer (31) side by the low level output of the latch circuit (26). Therefore, the serial clock b is made into a serial clock CLK having an amplitude of 2 volts which varies between 0 and 2 volts by the buffer (31) and is applied from the clock output terminal (3) to the clock input terminal (4). This serial clock CL
K is compared with a reference voltage (1 volt) by a comparator (10) to open the AND gate (1
It is taken into the inside of the second microcomputer (2) from the OR gate (15) via 4) as a serial clock having an amplitude of 5 volts. Inside the second microcomputer (2), 8-bit serial data is generated in synchronization with the serial clock output from the OR gate (15). This serial data is 2 in the buffer (18)
The amplitude of the volt is set to the serial data DATA (d0 to d) from the data output terminal (6) through the switching unit (19).
7) and the comparator (2) inside the first microcomputer (1) is output via the data input terminal (7).
In 3) it is compared with a reference voltage of 1 volt. Since the AND gate (28) opens the gate, the comparator (2
The output of 3) is output from the OR gate (29) with an amplitude of 5 volts, and is subjected to predetermined arithmetic processing inside the first microcomputer (1).

From the above, when the serial clock CLK and the serial data DATA are transferred between the first and second microcomputers (1), the line (5) for externally connecting the both microcomputers (1) and (2).
Serial data CLK and serial data D in (8)
Since the amplitude of the ATA can be reduced, it is possible to prevent noise from being superposed on the peripheral integrated circuits, and thus to prevent malfunction in the peripheral integrated circuits.

In the case of a system in which it is not necessary to consider the influence of noise or the like on the peripheral integrated circuits, or because of the influence of noise from the periphery, the amplitudes of the serial clock CLK and the serial data DATA must be increased. When the influence of the noise cannot be ignored, the amplitude of the serial clock CLK and the serial data DATA transferred through the clock line (5) and the data line (8) needs to be 5 volts. In this case, CPU (1
The control signals e and f output from 6) may be set to the high level. By doing so, the same operation as described above is performed, and the serial clock CLK and the serial data DATA (D0 to D7) having an amplitude of 5 volts can be obtained.

[0016]

According to the present invention, when the serial clock and the serial data are transferred between the first and second microcomputers, they are connected to the externally connected line for the purpose of interface between the two microcomputers. The amplitude of the serial clock and the serial data to be superimposed can be switched to increase or decrease. As a result, the amplitudes of the serial clock and the serial data may be switched according to the characteristics of the integrated circuits existing around the first and second microcomputers, and especially when the peripheral integrated circuits are easily affected by noise. In addition, by reducing the amplitude, it is possible to prevent noise from being superposed on the integrated circuits existing in the periphery, and to obtain an advantage that malfunctions in the peripheral integrated circuits can be prevented.

[Brief description of drawings]

FIG. 1 is a diagram showing a serial data transfer circuit of the present invention.

FIG. 2 is a time chart of FIG.

[Explanation of symbols]

(1) First microcomputer (2) Second microcomputer (9) (17) (18) (22) (30) (31) Buffer (10) (23) Comparator (16) CPU (19) (32) Switching unit (26) Latch circuit (27) (28) AND gate (29) OR gate

Claims (2)

[Claims] 1. A serial clock is transferred from the first microcomputer to the second microcomputer between a first microcomputer and a second microcomputer, and is synchronized with the serial clock from the second microcomputer. A serial data transfer circuit for transferring data of a predetermined bit to the first microcomputer, wherein a serial clock having a first threshold voltage and varying with a first amplitude or a second amplitude smaller than the first amplitude is applied.
An input unit, a second input unit having a second threshold voltage lower than the first threshold voltage, to which the serial clock is commonly applied, and a first output unit having a predetermined amplitude of serial data of a predetermined bit, A second output section that sets the predetermined amplitude of the serial data to the second amplitude; and a control section that switches the outputs of the first and second input sections and the outputs of the first and second output sections. It has a second threshold voltage, and a third input section which is built in the second microcomputer and which has the first threshold voltage and to which the serial data selectively output from the first or second output section is applied. A fourth input section to which the serial data selectively output from the first or second output section is applied, a third output section having a serial clock as the first amplitude, and the serial clock as the second amplitude. First Four
The output section and the amplitude of the selected output of the first or second output section are discriminated, and the selected serial clock from the third or fourth output section is applied to the second microcomputer based on the discrimination result. A discriminating unit, which is built in the first microcomputer, and the discriminating unit is operated when the control unit issues an instruction to transfer the serial data with the second amplitude from the first microcomputer to the second microcomputer. The serial clock having the second amplitude is transferred from the first microcomputer to the second microcomputer by using the determination result of the section, and the second microcomputer transfers the serial clock to the first microcomputer in synchronization with the serial clock. Serial data transfer characterized in that the serial data of the second amplitude is transferred to circuit. 2. A selection unit for selecting the outputs of the third and fourth input units according to the discrimination output of the discrimination unit and outputting the same amplitude is provided inside the first microcomputer. 1. The serial data transfer circuit described in 1.