JPH096690A - Supervisory control device - Google Patents

Abstract

(57) [Summary] [Object] A monitoring control device for monitoring various devices in a communication system, etc., so as not to miss an alarm signal even during a DMA operation or a processor failure period. [Structure] Processor 1, transmitter / receiver 2, and memory 3
In the supervisory control device having the DMAC 4 and the alarm receiving unit 5, the control unit 6 for identifying the occupation or release of the bus 11 by the DMAC 4, and the DMAC 4 controlled by the control unit 6 during the DMA operation period. When the control storage unit 7 that stores a certain information and the fact that the DMA operation period is being stored by the control storage unit 7, the bus switching command S
The alarm receiving unit 5 is switched and connected to the latch unit 10 side by W by the bus switching unit 9 by W, the received alarm signal of the alarm receiving unit 5 is held in the latch unit 10, and the processor 1 latches via the bus 11 when the DMA operation is completed. A holding unit 8 for reading an alarm signal from the unit 10 is provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a monitor control device for monitoring various devices in a communication system or the like. The monitoring control device includes a processor and a memory, collects alarm signals from various devices of the system, and transmits / receives monitoring information and the like to / from a host device. In transmitting and receiving the monitoring information and the like, a memory is interposed, and therefore direct memory access (DMA; Dir)
ect Memory Access) has been applied. It is desired that the alarm signal can be collected even during the direct memory access operation.

[0002]

2. Description of the Related Art FIG. 14 is an explanatory view of a conventional example. Reference numeral 61 is a processor (CPU), 62 is a transmitting / receiving unit for transmitting / receiving various data to / from an external device, 63a and 63b are memories (MEM), Is a direct memory access controller (DMAC), 65 is an alarm receiving unit for receiving alarm signals from various devices, 66 is a data bus, 67 is a clock generating unit, 68 is a reset circuit for initializing the state of the processor, 69 Is an alarm detector for detecting a runaway of the processor.

The processor 61, the transmission / reception unit 62, the memories 63a and 63b, the direct memory access controller 64, and the alarm reception unit 65 are respectively connected to the data bus 6.
6 are connected. Further, the processor 61 periodically accesses the alarm receiving unit 65, reads the received alarm signal via the data bus 66, and monitors whether or not various devices are normal.

Further, when various data is transmitted / received to / from an external device via the transmission / reception unit 62, direct memory access (hereinafter abbreviated as DMA) by a direct memory access controller (hereinafter abbreviated as DMAC) 64 is performed. For example, a memory 63a having a work area
And the transmission / reception unit 62 are allowed to transfer data without the processor 61 intervening.

For example, when the transmitter / receiver 62 receives data from an external device, the transmitter / receiver 62 sends a DMAC to the data.
Make a DMA request to 64. The DMAC 64 issues a bus release request to the processor 61 and sends a bus release response to the DMAC 64 when the processor 61 is not using the data bus 66. As a result, the DMAC 64 occupies the data bus 66 and controls the transfer of the data received by the transmitter / receiver 62 to the memory 63a via the data bus 66. The DMAC 64 releases the data bus 66 when the DMA ends.

[0006]

The processor 61 periodically accesses the alarm receiving section 65 to read the received alarm signal. For example, the DMAC 64 occupies the data bus 66 and the transmitting / receiving section 62 is used. And memory 63
When the DMA transfer is being performed between the alarm receiving unit 6 and
When the alarm signal is received at 5, the data bus 66 becomes D
Since it is occupied by the MAC 64, the processor 6
No. 1 cannot read the reception alarm signal of the alarm reception unit 65. Therefore, there is a problem that the alarm signal is missed.

When the processor 61 is in an alarm occurrence state such as program runaway, the alarm detection unit 69 can detect the alarm in the processor 16, but the alarm signal during the alarm state cannot be read. Further, even when the power supply of the processor 61 is in a voltage abnormal state such as a power failure, the processor 61 is in a stopped state, so that the alarm signal cannot be read. There is a problem that the alarm signal is missed during such a failure occurrence period.

Further, as the processor 61, a one-chip chip which does not have a reception function such as a wait function for a bus release request
If the microprocessor is used, the configuration using the DMAC64 cannot be realized. In that case, the data transfer between the transmission / reception unit 62 and the memory 63a is executed by the processor 61, and there is a problem that the efficiency of the data transfer decreases. It is an object of the present invention to enable DMA even in the case of a processor that does not have a bus release request acceptance function, and to prevent a warning signal from being missed even during DMA or during a processor failure period.

[0009]

A monitoring control apparatus according to the present invention will be described with reference to FIG. 1. (1) A data transmission / reception unit 2 for communicating with an external device, the transmission / reception unit 2 and a bus 11. A memory (MEM) 3 connected via the bus, a DMAC 4 that occupies the bus and controls data transfer between the transmission / reception unit 2 and the memory 3, and a processor (CPU) connected to the bus 11 and controls each unit. 1 and an alarm receiver 5 for receiving an alarm signal from an external device,
Control unit 6 for identifying bus occupation or release by MAC4
And D controlled by the DMAC 4 under the control of the control unit 6.
A control storage unit 7 for storing that the MA operation period is in progress;
The control storage unit 7 holds the alarm signal received by the alarm receiving unit 5 when the fact that the DMA operation period is being stored is stored.
And a holding unit 8 for reading the alarm signal held via 1. Further, 9 is a bus switching unit, and 10 is a latch unit.

(2) Further, the control unit 6 identifies whether the DMAC 4 occupies or releases the bus 11, and at the same time, the processor 1
Whether or not an alarm has occurred is identified, and DM by DMAC4
A configuration may be provided in which the control storage unit 7 stores during the A operation period and during the alarm occurrence of the processor 1.

(3) Further, when the controller 6 identifies that the DMAC 4 is in the DMA operation period, the processor 1
A clock control unit for stopping the clock signal to the device can be provided.

(4) Further, a voltage monitoring / switching unit and a backup power supply are provided, and the voltage monitoring / switching unit notifies the control unit 6 when an abnormal state of the voltage of the power supply is detected, and at least the backup power supply A configuration may be provided in which the control unit 6, the control storage unit 7, the holding unit 8, and the alarm receiving unit 5 are switched to supply the operating voltage.

(5) Further, a plurality of alarm receiving units for receiving alarm signals from an external device, a holding unit common to the plurality of alarm receiving units, a control storage unit corresponding to the plurality of alarm receiving units, and a control unit. Identifies at least that the DMAC is in the DMA operation period, and adds the activation signal to the control storage unit corresponding to the alarm reception unit when the alarm reception unit outputs the activation request signal indicating that the alarm signal has been received. And can be provided.

[0014]

[Action]

(1) Since the bus switching command is not added to the holding unit 8 when the DMA operation period is not in progress, the alarm receiving unit 5 is switched and connected to the bus 11 side by the bus switching unit 9. Thereby,
The processor 1 can read the received alarm signal of the alarm receiver 5 via the bus 11. Also, from the transmitter / receiver 2 to
When the DMA request signal RQ is sent to C4, the DMAC 4 sends the bus release request signal BRR to the processor 1. When the processor 1 sends the bus release response signal BRA for releasing the bus, the control unit 6 receives the bus release request signal BRR and the bus release response signal BRA, and sends the bus release response signal BRA to the DMAC 4, and A start signal ST is applied to the control storage unit 7 by identifying the start of the DMA operation.

The DMAC 4 sends a DMA response signal AS to the transceiver 2 in response to the bus release response signal BRA and occupies the bus 11 to control data transfer between the transceiver 2 and the memory 3. Further, the control unit 6 sends an enable signal EN to the alarm receiving unit 5, a bus switching command SW to the bus switching unit 9 of the holding unit 8 and a latch signal to the latch unit 10 of the holding unit 8. The control storage unit 7 stores that the DMA operation period is in progress, and the holding unit 8 causes the bus switching unit 9 to move the alarm reception unit 5 to the latch unit 10 side so that the reception alarm signal of the alarm reception unit 5 can be held. Switch connection. Thereby,
The alarm signal received by the alarm receiver 5 can be latched in the latch unit 10. When the DMA operation is completed, D
Since the MAC 4 releases the bus 11 and the bus switching command SW is released, the bus switching unit 9 of the holding unit 8 returns to the original state. Further, the processor 1 can read the alarm signal held in the holding unit 8 via the bus 11. Therefore, D
The alarm signal will not be missed during the MA operation period.

(2) The presence / absence of an alarm such as a program runaway of the processor 1 is identified, and when the alarm occurs, the processor 1 cannot read the reception alarm signal of the alarm reception unit 5, so that the control unit 6 operates in the DMA operation period. Similarly to the inside, by switching the alarm receiving unit 5 to the latch unit 10 side of the holding unit 8, it is possible to hold the received alarm signal during alarm generation.

(3) During the DMA operation period, the processor 1
Since the bus 11 is released to enter the wait state, the supply of the clock signal is stopped by the clock control unit, and the DMA operation is enabled even when the processor having no function of accepting the bus release request is used. be able to.

(4) When the voltage monitoring / switching unit detects an abnormal state of the power supply voltage, such as a power failure or an abnormal decrease in operating voltage, the control unit 6 is notified and the backup power supply
The operating voltage is supplied to the control unit 6, the control storage unit 7, the holding unit 8, and the alarm receiving unit 5. Therefore, the control unit 6 controls the DM
As in the A operation period, the alarm receiving unit 5 is controlled to be switched and connected to the latch unit 10 side of the holding unit 8, and the received alarm signal of the alarm receiving unit 5 is held even in the abnormal state of the power supply voltage. It can be held by the part 8.

(5) Further, the alarm receiving section is divided into a plurality of sections, a control storage section is provided for each of the plurality of alarm receiving sections, and the control section 6 is a DM.
When it is identified that the A operation period is in progress, an activation signal is applied to the switching unit, and when any one of the plurality of alarm receiving units receives the alarm signal, an activation request signal is sent to the switching unit. The switching unit adds an activation signal to the control storage unit corresponding to the alarm receiving unit that has received this alarm signal. Accordingly, the control storage unit can control the holding unit so that the reception warning signal of the warning receiving unit can be latched, and thus the warning signal can be held during the DMA operation period.

[0020]

2 is an explanatory view of the first embodiment of the present invention, in which the same reference numerals as those in FIG. 1 indicate the same parts. Further, 13 is a random access memory (RAM), 14 is a read only memory (ROM), 15 is a data bus, 16 is an address bus, 17 is a decoding circuit, 18 is a counter, 19 is a read only memory, 20 is an OR circuit, 21 Is a photocoupler, and 22 is a bus driver. Further, CS1 to CSn from the decoding circuit 17 are chip select signals, and RQ is DM.
A request signal, AS is a DMA response signal, BRR is a bus release request signal, BRA is a bus release response signal, ST is a start signal, EN is an enable signal, LS is a latch signal, and SW is a bus switching instruction.

With respect to the processor (CPU) 1, a data bus 15 and an address bus 16 are used to provide a transceiver unit 2,
The DMAC 4, the random access memory 13, and the read-only memory 14 are connected, the decoding circuit 17 and the holding unit 8 are connected to the data bus 15, and the alarm receiving unit 5
Has a configuration connected to the data bus 15 via the holding unit 8.

The DMAC 4 is the DMA from the transmitter / receiver 2.
When the bus release request signal BRR is sent to the processor 1 by the request signal RQ and the bus release response signal BRA from the processor 1 is received via the control unit 6, DM is sent to the transmission / reception unit.
The A response signal AS is sent to control the data transfer between the read only memory 13 and the transmission / reception unit 2. The control unit 6
By the bus release request signal BRR from the DMAC4 and the bus release response signal BRA from the processor 1, the DMAC4
The bus release response signal BRA is sent to the control storage unit 7.

The alarm receiver 5 includes a photocoupler 21 and a bus driver 22, receives alarm signals from various devices (not shown) by the photocoupler 21, and the holding unit 8 via the bus driver 22. Send to. The holding portion 8
A bus switching unit 9 and a latch unit 10 are provided, and the bus switching unit 9 switches and connects the alarm receiving unit 5 to the data bus 15 side or the latch unit 10 side by a bus switching command SW via the control storage unit 7. Further, the latch unit 10 latches the reception alarm signal of the alarm reception unit 5 by the latch signal from the control storage unit 7 when it is applied via the bus switching unit 9, and when it is selected by the chip select signal CS5, Processor 1
Reads the alarm signal latched by the latch unit 10 via the data bus 15. Further, the control storage unit 7 includes a counter 18 and a read-only memory 19, and the counter 1
By the latch signal corresponding to the count content of 8, the alarm signal is latched in the latch unit 10 in correspondence with the input port of the alarm receiving unit 5.

When the DMA operation is not performed, the bus switching command SW is not added to the holding unit 8, so the bus switching unit 9
Connects the alarm receiver 5 to the data bus 15 side. Therefore, when the processor 1 sends the address of the alarm receiving unit 5 to the address bus 16, the decode circuit 17 outputs the chip select signal CS4, which is added to the alarm receiving unit 5 via the OR circuit 20. A reception warning signal is sent to the holding unit 8 via the bus driver 22 of the data bus 1 via the bus switching unit 9 of the holding unit 8.
A reception alert signal is sent to 5, and the processor 1 can read this reception alert signal. The processor 1 periodically reads the reception alarm signal of the alarm reception unit 5.

FIG. 3 is a flow chart of the first embodiment of the present invention. When the transmitter / receiver 2 sends out the DMA request signal RQ (A1), the DMAC 4 sends out the bus release request signal BRR (A2). The processor (CPU) 1 determines whether or not the bus release request signal BRR can be received (READY) (A3), and sends the bus release request signal BRR until it can be received. The bus release response signal BRA is transmitted (A5).

The control unit 6 identifies the start of the DMA operation from the bus release request signal BRR from the DMAC 4 and the bus release response signal BRA from the processor 1 and sends the bus release response signal BRA to the DMAC 4 to activate it. The signal ST is sent to the control storage unit 7, the bus switching command SW is sent to the holding unit 8, the enable signal EN is sent to the alarm receiving unit 5,
The latch signal LS is sent to the holding unit 8 (A5). Since the control section 6 sends the start signal ST upon the start of the DMA operation, it is possible to adopt a configuration in which the bus switching command SW, the latch signal LS, and the enable signal EN are sent by the processing in the control storage section 7. is there.

The DMAC 4 starts data transfer control between the transmission / reception unit 2 and the random access memory 13 by the bus release response signal BRA from the processor 1 via the control unit 6 (A6). Further, the holding unit 8 causes the bus switching unit 9 to switch the alarm receiving unit 5 to the latch unit 1 in response to the bus switching command SW.
Switch connection to 0 side (A7). Further, the alarm receiving unit 5 sends out a received alarm signal via the bus driver 22 in response to the enable signal EN via the OR circuit 20 (A8).
In the holding unit 8, the latch unit 1 is provided via the bus switching unit 9.
The received alarm signal of the alarm receiver 5 is added to 0, and the signal is latched according to the latch signal LS (A9).

Since the start signal ST is sent during the DMA operation period, it is judged whether or not this start signal is continuing (A1
0), if continuing, the step (A7) and the subsequent steps are repeated. When it is not continued, that is, when the DMA operation ends, the DMAC 4 releases the bus, and the control unit 6 releases the bus switching command SW and the enable signal EN.
Is canceled (A11).

As a result, the processor 1 sends the address of the holding unit 8 to the address bus 16,
The chip select signal CS5 is added to the holding unit 8 from the decoding circuit 17, and the alarm signal latched by the latch unit 10 is
It can be read via the data bus 15. Further, the processor 1 periodically sends the address of the alarm receiving unit 5 to the address bus 16, adds the chip select signal CS4 from the decoding circuit 17 to the alarm receiving unit 5 via the OR circuit 20, and holds the received alarm signal. The data can be read via the bus switching unit 9 of the unit 8 and the data bus 15 (A12).

As described above, during the DMA operation period, the alarm receiving unit 5 can receive the alarm signals from various devices and the latch unit 10 of the holding unit 8 can latch the alarm signals. When the DMA operation is completed, the processor 1 can read the alarm signal latched by the latch unit 10 via the data bus 15. Therefore, there is an advantage that the alarm signal is not missed.

FIG. 4 is an explanatory view of the second embodiment of the present invention, in which the same reference numerals as those in FIG. 1 indicate the same parts, and 31 is an alarm detecting section. In this embodiment, when the alarm detection unit 31 detects an alarm state such as a program runaway of the processor (CPU) 1, an alarm detection signal AL is sent to the control unit 6.
Add. Similarly to during the DMA operation period by the DMAC 4, the control unit 6 applies the activation signal ST to the control storage unit 7 and transmits the reception alarm signal of the alarm reception unit 5 to the latch unit 10 of the holding unit 8 via the bus switching unit 9. In addition, the reception alarm signal is latched.

FIG. 5 is a flowchart of the second embodiment of the present invention, in which the alarm detector 31 is a processor (CP).
When the alarm detection of (U) is performed (B1), the control unit 6 receives the alarm detection signal AL from the alarm detection unit 31,
The start signal ST is sent to the control storage unit 7, the bus switching command SW is sent to the holding unit 8, the enable signal EN is sent to the alarm receiving unit 5, and the latch signal to the latch unit 10 of the holding unit 8 is sent. Yes (B2). The bus switching command SW, the latch signal, and the enable signal EN in this case can also be sent by the processing of the control storage unit 7, as described above.

The holding unit 8 switches and connects the alarm receiving unit 5 to the latch unit 10 side by the bus switching unit 9 according to the bus switching command SW (B3), and the alarm receiving unit 5 enables the enable signal EN.
In response to the received warning signal (B4), the holding unit 8
The reception warning signal is latched in the latch unit 10 according to the latch signal (B5).

The control unit 6 determines whether or not the alarm detection of the processor 1 is continued in the alarm detection unit 31 (B6), and if it is continued, the step (B5).
Repeat the following. Further, when it is not continued, it means that the processor 1 has returned to the normal state, and therefore the bus switching command SW and the enable signal EN are released (B7). The processor 1 also includes the latch unit 10 of the holding unit 8.
Read the alarm signal latched in
After that, the alarm reception unit 5 is periodically accessed to read the received alarm signal via the bus 11 (B8).

As described above, when an alarm such as program runaway of the processor 1 is detected, the processor 1 cannot read a normal alarm signal, but the alarm signal received by the alarm receiver 5 is held by the processor 1. 8 latch section 10
Since the alarm signal latched in the latch unit 10 is read when the processor 1 returns to the normal state, there is an advantage that the alarm signal is not missed.

FIG. 6 is an explanatory view of the third embodiment of the present invention. The same reference numerals as those in FIG. 1 denote the same parts, 32 is a voltage monitoring / switching unit, 33 is a backup power supply, and 34 is a power supply, For example, it is a power source that rectifies a commercial AC voltage and outputs a stabilized DC voltage. Under normal conditions, the operating voltage is supplied from the power supply 34 to each part. The voltage monitoring / switching unit 32
When the voltage of the power supply 34 is monitored and an abnormal state such as a power failure or an abnormal voltage drop is detected, the power supply voltage abnormality detection signal VD is added to the control unit 6, and an alarm is issued as shown in (5) to (8). The monitoring unit 5, the control unit 6, the control storage unit 7, and the holding unit 8 are switched so that the operating voltage is supplied from the backup power supply 33.

FIG. 7 is a flow chart of the third embodiment of the present invention. In the voltage monitoring / switching unit 32, the power source 34 is used.
When a power failure or an abnormal state in which the voltage has dropped to a predetermined value or less is detected (C1), the backup power source 33 is switched to and an abnormal voltage detection signal VD is added to the control unit 6 to notify the abnormal voltage (C2). ). The control unit 6 sends the start signal ST to the control storage unit 7, sends the bus switching command SW to the holding unit 8, and sends the enable signal E to the alarm receiving unit 5.
N is sent, and a latch signal to the holding unit 8 is sent (C
3).

The holding unit 8 switches and connects the alarm receiving unit 5 to the latch unit 10 side by the bus switching unit 9 (C4), and the alarm receiving unit 5 sends the received alarm signal to the holding unit 8 (C5).
Further, the holding unit 8 latches the reception alarm signal applied via the bus switching unit 9 in the latch unit 10 (C6).

Further, the control section 6 judges whether or not the abnormal state of the voltage of the power source 34 is continuing by the abnormality detection signal VD from the voltage monitoring / switching section 32 (C7). If the abnormal state is continuing, , Step (C5) and subsequent steps are repeated. When the normal state is restored, the control unit 6 releases the bus switching command SW and the enable signal EN (C8). Further, the processor 1 reads the alarm signal latched in the latch unit 10 of the holding unit 8, and thereafter restarts the operation of periodically accessing the alarm receiving unit 5 to read the alarm signal (C
9).

As described above, when the voltage of the power source 34 is in an abnormal state, the processor 1 cannot operate, but the operating voltage is applied to the functional portion for receiving and holding the alarm signal from the backup power source 33. And the alarm receiver 5
When the power supply 34 returns to the normal state by latching the received alarm signal of No. 2 in the latch unit 10, the processor 1 becomes operable and the alarm signal latched in the latch unit 10 can be read. Therefore, there is an advantage that the alarm signal is not missed, and since the backup power supply 33 supplies only a small portion, the backup power supply 33 can be composed of a small capacity battery or the like. That is, it is possible to economically latch the alarm signal at the time of abnormality.

FIG. 8 is an explanatory view of the fourth embodiment of the present invention, in which the same reference numerals as those in FIG. 1 denote the same parts, 35 is a clock generator, and 36 is a clock controller. This example is
The case where the processor (CPU) 1 does not have a function of receiving the bus release request signal BRR is shown. When the DMA operation is not in progress, the clock signal from the clock generation unit 35 is applied to the processor 1 via the clock control unit 36, and the bus switching unit 9 of the holding unit 8 switches the alarm receiving unit 5 to the bus 11 side. Connected. Therefore, the processor 1 can periodically read the received alarm signal of the alarm receiver 5 via the bus 11 in synchronization with the clock signal.

When the DMA request signal RQ is added to the DMAC 4 from the transmitter / receiver 2, the DMAC 4 receives the bus release request signal B.
Send RR. Since the processor 1 does not have a function of receiving the bus release request signal BRR, the control unit 6
Sends a bus release response signal BRA to the DMAC 4 in response to the bus release request signal BRR. The DMAC 4 processes in the same manner as the bus release response signal BRA from the processor 1, sends out the DMA response signal AS to the transmitting / receiving unit 2, and starts the DMA operation between the memory (MEM) 3 and the transmitting / receiving unit 2.

The control unit 6 also applies the control signal CKC to the clock control unit 36 to stop the clock signal from the clock generation unit 35 to the processor 1. As a result, the processor 1 enters the wait state and the bus 11 is released. That is, even when a one-chip microprocessor or the like that does not have a function of accepting a bus release request is used, the DMA operation can be performed, and the D
The reception alarm signal during the MA operation period can be retained. Further, upon completion of the DMA operation, the control unit 6 causes the control signal CK
Since C is stopped, the clock signal from the clock generator 35 is applied to the processor 1 via the clock controller 36, and the processor 1 can return to normal operation.

FIG. 9 is an explanatory view of the fifth embodiment of the present invention, in which the same reference numerals as those in FIG. 1 indicate the same parts, and 5-1 and 5-2.
Is an alarm receiving unit, 7-1 and 7-2 are control storage units, 8A is a holding unit, 9-1 and 9-2 are bus switching units, and 40 is a switching unit. In this embodiment, a plurality of alarm receiving units 5-1 and 5-2 are provided, and the control storage unit 7 corresponding to the alarm receiving units 5-1 and 5-2 is provided.
-1, 7-2 are provided, and the holding unit 8A is provided in common to the plurality of alarm receiving units 5-1 and 5-2, but the holding unit 8A corresponds to the alarm receiving units 5-1 and 5-2. Bus switching unit 9-1, 9-
2 is provided.

When the DMA operation is not in progress, the bus switching commands SW1 and SW2 are not added to the holding unit 8A.
The bus switching units 9-1 and 9-2 switch and connect the alarm receiving units 5-1 and 5-2 to the bus 11 side. Therefore, the processor (CPU) 1 periodically receives the alarm receiving units 5-1 and 5-2.
Can be sequentially accessed to read the reception alarm signal.

When the transmitter / receiver 2 sends out the DMA request signal RQ, the DMAC 4 sends out the bus release request signal BRR, and the processor 1 sends out the bus release response signal BRA, the controller 6 sends the bus release response signal BRA to the DMAC 4. And the activation signal ST to the switching unit 40. Also DM
The AC 4 sends a DMA response signal AS to the transmission / reception unit 2 and controls data transfer between the memory (MEM) 3 and the transmission / reception unit 2.

Upon receiving the alarm signal, the alarm receiving units 5-1 and 5-2 inform the switching unit 40 of the activation request signals SR1 and SR2.
Is sent. The switching unit 40 uses the activation signal S from the control unit 6.
T and the activation request signal S from the alarm receivers 5-1 and 5-2
The start signals ST1 and ST2 are sent to the control storage units 7-1 and 7-2 by R1 and SR2. That is, the switching unit 40
Is to switch and send the start signal to the control storage unit on the side to which the start request signal is added.

Further, the control storage units 7-1 and 7-2 have a holding unit 8
A has bus switching commands SW1 and SW2, an alarm receiver 5-1
The alarm receiving units 5-1 and 5-2 which have transmitted the enable signals EN1 and EN2 to 5-2 and have received the alarm signal, send the alarm signal to the bus side by a bus driver (not shown) according to the enable signals EN1 and EN2. Send out. Further, according to the bus switching commands SW1 and SW2, the bus switching units 9-1 and 9-2 switch and connect the alarm receiving units 5-1 and 5-2 to the latch unit 10 side, so that the received alarm signal is latched in the latch unit 10. be able to. In this case, the control storage unit corresponding to the alarm receiving unit that has received the alarm signal and the bus switching unit operate to latch the received alarm signal in the latch unit 10.

Therefore, when the DMA operation is completed, the DMAC
4 releases bus 11, processor 1
The alarm signal latched in the latch unit 10 can be read via the. That is, the reception processing can be performed by the processor 1 without missing the alarm signal during the DMA operation period.

FIG. 10 is a flow chart of the fifth embodiment of the present invention. When the transmitter / receiver 2 sends out the DMA request signal RQ (D1), the DMAC 4 causes the bus release request signal BRR.
Is transmitted (D2). The processor (CPU) 1 determines whether the bus release request signal BRR can be received (READY) (D3), and the bus release request signal B is received until it can be received.
Send RR. Further, when it becomes possible to accept, the processor 1 sends out a bus release response signal BRA (D4).

The control unit 6 informs the DMAC 4 of the bus release response signal B by the bus release request signal BRR from the DMAC 4 and the bus release response signal BRA from the processor 1.
RA is sent and a start signal ST is sent to the switching unit 40 (D5).

Upon receiving the bus release response signal BRA, the DMAC 4 starts data transfer between the memory 3 and the transmitting / receiving unit 2 (D6). The alarm receiving units 5-1 and 5-2 determine whether or not an alarm signal is received (D7), and when the alarm signal is received, the activation request signals SR1 and SR2 are sent to the switching unit 40 (D8). The switching unit 40 controls the control storage units 7-1 and 7 according to the activation signal ST from the control unit 6 and the activation request signals SR1 and SR2 from the alarm reception units 5-1 and 5-2.
-2, and sends start signals ST1 and ST2 (D9).

For example, when the alarm receiving unit 5-1 receives the alarm signal, the activation request signal SR1 is added to the switching unit 40, so that the switching unit 40 causes the control storage unit 7-1 to activate the activation signal S.
Add T1. As a result, the bus switching command SW1 is sent from the control storage unit 7-1 to the holding unit 8A, and the enable signal EN1 is sent to the alarm receiving unit 5-1 (D1.
0). The alarm receiving unit 5-1 sends a reception alarm signal to the bus side in response to the enable signal EN1. In the holding unit 8A, the bus switching unit 9-1 switches and connects the alarm receiving unit 5-1 to the latch unit 10 side, so that the alarm signal received by the alarm receiving unit 5-1 is latched in the latch unit 10 (D11). .

Further, it is judged whether or not the activation signal from the control unit 6 to the switching unit 40 is continuing, that is, whether or not the DMA operation is in progress (D12). When it is repeatedly executed and is no longer in progress, that is, DM
When the A operation is completed, the control unit 6 releases the bus switching command SW1 and the enable signal EN1 (D13). As described above, the bus switching commands SW1 and SW2 and the enable signals EN1 and EN are processed by the control storage units 7-1 and 7-2.
2 is transmitted from the control unit 6 to the control storage unit 7-
By sending the release command to the bus terminals 1 and 7-2, the bus switching commands SW1 and SW2 and the enable signals EN1 and EN2 are sent.
And can be canceled.

Further, the processor 1 reads an alarm signal from the latch section 10 through the bus 11 upon completion of the DMA operation,
After that, the alarm receivers 5-1 and 5-2 are periodically accessed to read the alarm signal (D14). Therefore, the alarm signal during the DMA operation is held in the holding unit 8A, and the processor 1 reads it when the DMA operation is completed. Therefore, there is an advantage that the alarm signal is not missed. Two alarm receivers 5-
1, 5-2 and control storage units 7-1, 7-2 corresponding thereto
And a case where the bus switching units 9-1 and 9-2 are provided,
It is also possible to adopt a configuration in which it is further divided.

FIG. 11 is an explanatory view of the sixth embodiment of the present invention. The same reference numerals as those in FIG. 9 indicate the same parts, and 41 is an alarm detector. The alarm detection unit 41 corresponds to the alarm detection unit 31 in FIG.
U) The alarm state such as program runaway of 1) is detected and the alarm detection signal AL is added to the control unit 6.

The control section 6 applies the activation signal ST to the switching section 40 in the same manner as during the DMA operation period by the DMAC 4.
Further, when the alarm receivers 5-1 and 5-2 receive the alarm signal,
Since the activation request signals SR1 and SR2 are added to the switching unit 40, the switching unit 40 causes the control storage units 7-1 and 7-2 on the side corresponding to the activation request signals SR1 and SR2 to activate signals ST1 and ST1.
Add ST2.

In response to the start signals ST1 and ST2, the control storage units 7-1 and 7-2 cause the bus switching commands SW1 and SW2.
Is added to the holding unit 8A, and the alarm receiving units 5-1 and 5-
2 to the enable signals EN1 and EN2. As a result, the alarm signals from the alarm receiving units 5-1 and 5-2 that have received the alarm signal are added to and latched by the latch unit 10 via the bus switching units 9-1 and 9-2.

When the processor 1 returns to the normal state, the alarm detection signal AL is released, and the processor 1 can read the alarm signal latched by the latch unit 10 via the bus 11. Therefore, even if the processor 1 is in an abnormal state, the alarm signal will not be missed.

FIG. 12 is an explanatory view of the seventh embodiment of the present invention, in which the same symbols as in FIG. 9 indicate the same parts, 42 is a voltage monitoring / switching unit, 43 is a backup power supply, and 44 is a power supply. The voltage monitoring / switching unit 42, the backup power supply 43, and the power supply 44 correspond to the voltage monitoring / switching unit 32, the backup power supply 33, and the power supply 34 in FIG. 6, and the voltage of the power supply 34 is controlled by the voltage monitoring / switching unit 42. When the abnormal state of the voltage due to a power failure or the like is monitored by monitoring the
In addition to the backup power source 43, the alarm receiver 5
-1, 5-2, the control unit 6, the control storage units 7-1, 7-2, and the holding unit 8A include (5-1), (5-2), (6),
As shown as (7-1), (7-2), (8A),
Switch to supply operating voltage.

Further, the control section 6 sends the start signal ST to the switching section 40.
By adding the same as in the above-mentioned DMA operation or the alarm state of the processor 1, the alarm receiving units 5-1 and 5 are added.
The alarm signal received by -2 is latched in the latch unit 10, and when the power supply 44 is restored to the normal state, the alarm signal latched in the latch unit 10 can be read from the processor 1 via the bus 11.

FIG. 13 is an explanatory view of the eighth embodiment of the present invention, in which the same reference numerals as those in FIG. 9 designate the same parts, 45 is a clock generator, and 46 is a clock controller. The clock generator 45 and the clock controller 46 correspond to the clock generator 35 and the clock controller 36 in FIG.

In the case where the processor (CPU) 1 does not have a function of accepting the bus release request signal BRR, when the DMA request signal RQ is sent from the transmitting / receiving section 2, the DMAC 4 sends the bus release request signal BRR. Send out.
The control unit 6 sends a bus release response signal BRA to the DMAC 4 in response to the bus release request signal BRR, and the switching unit 40.
To the clock controller 46, and the control signal CKC to the clock controller 46. The clock control unit 46 controls the clock generator 45 from the processor 1 according to the control signal CKC.
Since the clock signal to the CPU 1 is stopped, the processor 1 enters the wait state and the bus 11 is released. Therefore, the DMAC 4 occupies the bus 11, and the transmitter / receiver 2
The data transfer between the memory and the memory 3 can be controlled.

Further, the alarm receiving units 5-1 and 5- during the DMA operation
In the case of receiving the alarm signal in 2, the bus switching command SW is output from the control storage units 7-1 and 7-2, as in the above-described embodiment.
1, SW2 and the enable signals EN1 and EN2 are transmitted, so that the reception alarm signal can be latched in the latch unit 10. Then, since the start signal ST and the control signal CKC from the control unit 6 are released by the end of the DMA operation, the supply of the clock signal to the processor 1 is started, and the processor 1 latches in the latch unit 10 via the bus 11. The alarm signal can be read.

The present invention is not limited to the above-described embodiments, but various additions and modifications can be made. For example, the embodiments may be combined. Further, in the holders 8 and 8A, the alarm receivers 5, 5-1 and 5
A configuration for detecting a change in the received signal at -2 may be provided. If there are many alarm signal receiving ports,
It is also possible to adopt a configuration in which reading is performed in a divided manner according to the bus width.

[0066]

As described above, according to the present invention, the DMA
The receiving alarm signals of the alarm receiving units 5, 5-1 and 5-2 during the operation period are held in the holding units 8 and 8A, and the processor 1 outputs the alarm signals held in the holding units 8 and 8A when the DMA operation ends. Since the warning signal is not missed during the DMA operation, there is an advantage that the system can be effectively monitored.

Further, even in an abnormal state such as a power failure of the processor 1 or a program runaway, the alarm receiving units 5, 5-1 and 5
-2, the alarm signal received at -2 can be held in the latch unit 10 of the holding units 8 and 8A, so that there is an advantage that the alarm signal is not missed.

Further, even when the supervisory control device is configured by using a processor that does not have a function of accepting a bus release request, it is possible to perform the DMA operation by controlling the supply and stop of the clock signal to the processor, and the DMA operation. Since the received alarm signal during the period can be held in the holding units 8 and 8A, there is an advantage that the alarm signal is not missed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram of a first embodiment of the present invention.

FIG. 3 is a flowchart of the first embodiment of the present invention.

FIG. 4 is an explanatory diagram of a second embodiment of the present invention.

FIG. 5 is a flow chart of a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a third embodiment of the present invention.

FIG. 7 is a flowchart of a third embodiment of the present invention.

FIG. 8 is an explanatory diagram of a fourth embodiment of the present invention.

FIG. 9 is an explanatory diagram of a fifth embodiment of the present invention.

FIG. 10 is a flow chart of a fifth embodiment of the present invention.

FIG. 11 is an explanatory diagram of the sixth embodiment of the present invention.

FIG. 12 is an explanatory diagram of a seventh embodiment of the present invention.

FIG. 13 is an explanatory diagram of an eighth embodiment of the present invention.

FIG. 14 is an explanatory diagram of a conventional example.

[Explanation of symbols]

1 processor (CPU) 2 transceiver unit 3 memory (MEM) 4 direct memory access controller (DMA)
C) 5 alarm receiving unit 6 control unit 7 control storage unit 8 holding unit 9 bus switching unit 10 latch unit 11 bus

Claims (5)

[Claims] 1. A transmission / reception unit for transmitting / receiving data to / from an external device,
A memory connected to the transmission / reception unit via a bus, a direct memory access controller that occupies the bus and controls data transfer between the transmission / reception unit and the memory, and each unit connected to the bus In a supervisory control device having a processor for controlling an alarm signal and an alarm receiving unit for receiving an alarm signal of an external device, a control unit for identifying occupation or release of the bus by the direct memory access controller; A control memory unit for storing that the direct memory access operation period is controlled by the direct memory access controller and storing the fact that the direct memory access operation period is stored by the control storage unit. The alarm signal received by the alarm receiver is retained and the direct memory access is performed. Monitoring controller, wherein the processor by work end and a holding portion for reading said alarm signal held via the bus. 2. The control unit identifies whether the bus is occupied or released by the direct memory access controller, identifies whether or not an alarm has occurred in the processor, and performs a direct memory access operation by the direct memory access controller. 2. The supervisory control device according to claim 1, further comprising a configuration for storing in the control storage unit during the period and during the alarm occurrence of the processor. 3. A clock controller for stopping a clock signal to the processor when the controller identifies that the direct memory access controller is in a direct memory access operation period. The monitoring control device according to claim 1. 4. A voltage monitoring / switching unit and a backup power supply are provided, and when the voltage monitoring / switching unit detects an abnormal state of the voltage of the power supply, the voltage monitoring / switching unit notifies the control unit and at least from the backup power supply. The control unit, the control storage unit, the holding unit, and the alarm receiving unit are configured to switch so as to supply an operating voltage. 4. Monitoring and control equipment. 5. A plurality of the alarm receiving units for receiving an alarm signal from an external device, a holding unit common to the plurality of alarm receiving units, the control storage unit corresponding to the plurality of alarm receiving units, The control unit has at least the direct memory access
When the controller recognizes that it is in the direct memory access operation period and outputs an activation request signal indicating that the alarm receiving unit has received an alarm signal, an activation signal to the control storage unit corresponding to the alarm receiving unit. 5. The monitoring control apparatus according to claim 1, further comprising a switching unit for adding the.