JPH096829A - Circuit drawing generation method - Google Patents

Abstract

(57) [Summary] [Object] To provide a circuit drawing generation method for efficiently and automatically generating circuit drawing data having coordinate information from connection data of a circuit having no coordinate information. [Structure] The number of stages is given to the instances in consideration of the arrangement positions of the input / output external terminals, the input / output buffer, the latched instances, and the like. The placement coordinate of the instance is determined so that the placement between the ports can be made as straight as possible, and the unique name of the instance, the connected port number, the line overlap check, the wiring area required for the line passing between the instances, etc. It is decided in consideration of.
The line connecting the ports between the instances is wired so as to pass through the wiring area determined when the instances are arranged. Also, when connecting ports between non-adjacent instances, wiring is performed so as to pass over the symbol occupied area, and after passing, wiring processing is performed while expanding and updating the symbol occupied area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit drawing generating method for automatically generating circuit drawing data having coordinate information from connection data of a circuit having no coordinate information.

[0002]

2. Description of the Related Art In recent years, after performing circuit synthesis from a functional diagram or a hardware description language (HDL), a circuit diagram is automatically generated to confirm the synthesis result, or a circuit diagram is obtained from a netlist having no coordinate information. Is required to be automatically generated.

Further, in such a case, it is required to generate a circuit drawing at high speed as the circuit scale increases.

In the conventional circuit drawing generating method, when the symbols are arranged and wired, whether the symbols and the lines are not overlapped, the lines are not overlapped, or the cross connection is not performed. I was wiring while checking.

However, since the scale of a circuit to be designed has increased, the number of symbols to be wired and the number of lines to be wired are enormous, and along with this, there is a tendency that the processing time for checking the placement and wiring increases.

[0006]

Therefore, even if the functional diagram or the hardware description language (HDL), which is an input for circuit synthesis, is slightly modified when the line scale becomes large, a circuit diagram is generated after circuit synthesis. There was a problem that it took a long time.

Therefore, an object of the present invention is to provide a method for generating a circuit drawing in a short time.

[0008]

According to the circuit drawing generating method of the present invention, the number of arranged output external terminals is fixed to 1 and the number of output external terminals is set to 1 at the input port of the output external terminal. When an instance with 1 input and 1 output is connected, the instance is regarded as an output buffer and the number of arranged stages is fixed to 2 and when an instance with 1 input and 1 output is connected to the input port of the input external terminal, the instance is input. It is regarded as a buffer, and the number of arrangement steps is (maximum step number −
Fixed to 1), fix the number of wiring stages of all input external terminals to the maximum number, and set the number of wiring stages n of an instance that is neither an output external terminal, an output buffer, an input buffer nor an input external terminal to 2 <n <(maximum stage number- Set to 1).

Further, the invention according to claim 2 further checks whether or not the instances are latch-connected to each other, and when they are latch-connected, the number of arranged stages of the instances is made the same.

The invention according to claim 3 is in the above,
Further, it has a table for managing the instance table storing the information of the instance for each number of arrangement steps, and rearranges the instance table in ascending or descending order with the instance name as a key.

According to a fourth aspect of the present invention, the output ports of the instances of each arrangement stage are given consecutive numbers from top to bottom, the input ports of the instances are checked, and the instance arranged to the left of the instance is inspected. A method of generating a circuit drawing, wherein the smallest number among the output ports of the above is set as the ID number of the instance, and the instance at each placement stage is rearranged in ascending or descending order using the ID number as a key.

Further, in the invention described in claim 5, in the above, if there is an input buffer (maximum stage number-1), there is no input buffer (maximum stage number-2).
As an instance of a stage, and an instance in which the number of stages arranged is smaller than that of the instance, the y coordinate is determined so that the output port of the stage adjacent to the left of the instance and the input port of the instance are connected by a straight line as much as possible, and the maximum stage number is determined. An instance of a certain input external terminal is arranged in y coordinates so that the input port of the instance of (maximum stage number-1) or (maximum stage number-2) stages and the output port of the instance are connected by a straight line as much as possible.

With the above arrangement, the y coordinate can be determined for each instance. At the same time, a wiring connecting the instances in the x direction is created.

Further, the invention according to claim 6 of the present invention is
In the above, it is checked whether or not the layout is such that lines are overlapped when wiring is performed in adjacent instances, and if lines are overlapped as a result of the check, the layout y coordinate of either instance is set to Δ (<minimum pin (Space) so that the lines do not overlap.

In the invention according to claim 7, a vertical line passing between adjacent instances passes through the x coordinate position determined by the ID number of the port of the instance connected to the line.

According to the eighth aspect of the invention, the pull-up / pull-down instance (constant instance) is arranged at the same x coordinate position as the input external terminal.

According to the invention described in claims 6 to 8, the arrangement coordinates of the instance in the x direction can be determined according to the present invention.

According to the ninth aspect of the invention, when one net has a plurality of sink destinations, the nets connected to the sink ports of the instances in each stage are connected and a horizontal line connecting the sink nets is connected. After wiring on the occupied area of all symbols, the horizontal line is connected to each sync net.

Further, the invention according to claim 10 is characterized in that the horizontal line connecting the instances of each arrangement stage is wired on the occupied area of all symbols, and then the occupied area of all symbols is newly set. Circuit drawing generation method.

According to the invention described in claims 9 and 10, when one net has a plurality of sources or sinks, it is possible to connect the nets between the instances.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or similar components are designated by the same reference symbols and numbers in the description.

FIG. 1 is a block diagram of a preferred embodiment of a circuit diagram generation system to which the circuit diagram generation method of the present invention is applied.

The present invention processes a netlist file, which is the basic data for generating a circuit diagram, as a basic configuration by an application program according to the method of the present invention, so that a circuit diagram having instance arrangement and wiring coordinate information can be obtained. It generates and outputs data.

Therefore, in FIG. 1, in the storage device 1 storing the netlist file and the central processing unit (not shown), the functional units S1 to S1 of the respective steps realized in the execution of the control program according to the present invention.
1 is realized, and thereby the circuit drawing generation processing is completed, and this is stored in the storage device 2 as a drawing data file. At the same time, the drawing data file is output by a printer on paper or displayed on a monitor.

Next, the function processing units S1 to S1 in FIG.
The contents of item 1 will be sequentially described in detail with reference to the drawings. [Table Converting Unit: Step S1 in FIG. 1] The netlist stored in the storage device 1 is text data in which, for example, connection information between cell terminals of a circuit is described in the circuit design. Therefore, it is difficult to understand the arrangement of elements, the state of wiring, etc. from this text data.

Therefore, the table conversion unit S1 has a function of converting the contents described below by the computer into code data that can be processed by the method of the present invention and expanding the converted data on the memory. Have. [Step Processing Unit: Step S2 in FIG. 1] FIG. 2 to FIG. 6 First, the instances forming the circuit are automatically arranged, and the number of arranged steps of the instances is added before wiring.
Here, the instance means a circuit element, a connection terminal, or the like. As for the number of stages, the number of stages of all output external terminals is set to 1 as shown in FIG. 2, and the number of stages is added while tracing the net connected to the input port from right to left as shown in FIG.

Further, as shown in FIG. 2, if an instance (output buffer) of 1 input and 1 output is connected to the input port of the output external terminal, the number of stages of the instance is set to 2. If an instance other than the output buffer is connected to the input port of the output external terminal, the number of stages is set to 3.

Further, as shown in FIG. 4, if an instance (input buffer) having one input and one output is connected to an output port of an input external terminal, the number of stages of the instance is (maximum stage number-
1). Also, set all input external terminals to the maximum number of stages.

When the number of stages is set as described above, an arrangement stage as shown in FIG. 5 is obtained. Then, when arranging the instances, the input and output external terminals can be arranged on the same x coordinate (same stage), so that it becomes easy to follow the signal from the output external terminal. The coordinate data of the instance is specified by the table conversion unit S1 as shown in FIG.

Since input and output buffers can be arranged on the same x-coordinate (same stage), buffers unrelated to the logic can be shifted aside, and the buffers can be placed in the logic circuit. It is possible to prevent mixing.

Further, as a step numbering process, it is next checked whether or not the instances are latch-connected. Checking the latch means that for all the instances, as shown in (1) of FIG.
Check the instance connected to the output port of 1.

The input port of the instance INS02 is connected to the output port of INS01. Further, its output port is connected to the input port of INS01.
In such a case, it is determined that INS01 and INS02 are latched.

Further, as shown in FIG. 6B, the latched instance is replaced with the same number of stages as either instance. In FIG. 6, the instance INS
02 from n + 1 [FIG. 6 (1)] to n [FIG.
(2)] has been changed.

If the number of logical stages of the instances connected by the latch is different, the instances forming the latch are separated when they are arranged. Therefore, by arranging the same number of stages as described above and arranging them in the same stage, it becomes easy to determine the latched portion in the circuit diagram.

[Instance Information Table Sorting Unit: Step S3 in FIG. 1] FIG. 7 to FIG. 10 As shown in FIG. 7, the management table A for storing the instance information table B corresponding to each stage is prepared. Also, FIG.
As described above, the instance information table B is sorted using the instance names (A0, B0, etc.) as keys.

According to the present invention, when arranging the instances, the information about the instance for each stage number is necessary because the process is performed for each stage number. An instance having a bit width is generally given a new instance name with a number added to the original instance name when macro-expanded or bit-expanded as shown in FIG.

Therefore, if the objects are sorted by name and arranged in that order, there is a high possibility that related instances will be arranged near each other. Use this as a guide when creating a drawing from a netlist where the appearance of instances is random. [Instance placement y-coordinate determination unit: step S in FIG. 1]
4] FIGS. 10 to 14 The placement reference points of the instance are defined as shown in FIG. That is, in FIG. 10, y0 is an arrangement reference point,
O is a symbol exclusive area.

Instances of (maximum stage number-2) stages are sorted in the instance information table B in the vertical direction (y
Direction) and place them at intervals. At this time, the horizontal arrangement (arrangement x coordinate) is not considered.

For the instances after the (maximum number of stages −3) stages that can be connected to the output port of the left adjacent instance by a straight line, the arrangement y coordinate is determined as y1 as shown in FIG. Here, the coordinate y1 is y1 with reference to the reference point y0.
= (Y0-d0) + d1.

Instances after the (maximum number of stages-3) stages that cannot be connected to the output port of the left adjacent instance by a straight line or are not connected to the left adjacent instance are arranged y coordinate y2 as shown in FIG. To decide. Here, the coordinate y2 is represented by y2 = y1−h−s with reference to the reference point coordinate y1 of the instance arranged so as to be connected to the instance having the reference point y0.

For an instance of (maximum number of stages-1) or more stages that can be connected to the input port of the adjacent instance on the right by a straight line, the arrangement y coordinate y1 is determined as shown in FIG.

Instances with (maximum number of stages-1) or more stages that cannot be connected to the input port of the adjacent instance on the right by a straight line or are not connected to the adjacent instance on the right are arranged with y coordinate y2 as shown in FIG. To decide.

In FIGS. 11, 12, 13, and 14 described above, the arrangement interval s of each instance is set to be larger than the minimum pin interval of the instances.

Since the ports between the instances are arranged so that they can be wired as straight as possible, the logic can be easily followed. According to the present invention, the output buffer and the output external terminal can be connected to the output port on the left side by a straight line as much as possible. Similarly, an instance with 1 input and 1 output such as an inverter can be connected to the output port on the left by a straight line as much as possible, so when the inverter is used for logical inversion,
The inverter can be located near the output port of the instance.

The input buffer and the input external terminal can be connected to the input port on the right by the straight line as much as possible.
Therefore, it is possible to reduce the bending of the line, which is an obstacle when following the signal. [Port ID sort section of instance: Step S in FIG. 1
5] FIG. 16 When the y-coordinates to be arranged for all the instances are decided, as shown in (1) of FIG. 15, the output ports of the instances are sequentially numbered from top to bottom for each arrangement stage.
(I = 1, 2, ..., N) Also, if the input port of the instance is checked and it is connected to the output port of the instance to the left of it, the smallest of the serial numbers of the output ports of the instance to the left of The additional number is the ID number of the instance.

An instance having no instance on the left side to be connected has its ID set to (maximum output port number + 1). In the example of FIG. 15 (1), the ID of the instance of A1
Is 10 (maximum output port number 9 + 1).

Next, the instance information table B (see FIG. 7) is sorted in ascending order using the ID number as a key. The instance information table B is sorted in ascending order using the ID number as a key [FIG. 15 (2)]. After sorting, the arrangement y-coordinate is re-determined by performing the same processing as the procedure in the [instance arrangement y-coordinate determining unit] described above.

Even if the instances are arranged in the order of the sorted instance names, the wiring may be twisted as shown in FIG. 15 (1). Therefore, by arranging the order of placement of the instances connected to the adjacent instance on the left side by the order of the output ports of the adjacent instance on the left side (unique serial number from top to bottom), the arrangement with less line kinking It can be performed.

When the instance that is not connected to the adjacent instance on the left side is sorted in ascending order by adding (maximum additional number +1) of its output port, the processing order of that instance is that it is connected to the instance on the left side. After the existing instance, it will not affect the placement and wiring of the instance connected to the adjacent instance on the left. [Instance placement y-coordinate overlap adjustment unit: Step S in FIG. 1
6] FIG. 16-FIG. 17 Next, it is checked whether or not the arrangement is such that lines are overlapped when wiring is performed as shown in (1) of FIG. If the lines are arranged so as to overlap each other, the y coordinate of the instance is shifted downward by Δ (<minimum pin interval) as shown in (2) of FIG.

Since the arrangement interval S of each instance is set to be larger than the minimum pin interval, the instances will not overlap even if they are shifted downward by Δ.

The check whether the lines overlap or not is performed as follows. First, as shown in FIG. 16, the input port of the right-hand instance having the adjacent number of arrangement stages is examined. Check if the input port is connected to the output port of any instance in the left placement stage.

In FIG. 17, when port 1 is connected to port 2 as shown in the figure, it is the output port of any instance of the arrangement stage on the left side on the same y coordinate as input port 1 of FIG. , Check if there is an output port.

Further, it is checked whether or not the port is connected to the input port of any instance in the arrangement stage on the right side (port 4 in FIG. 17). As a result of the examination as described above, if the ports 1, 2, 3, and 4 in FIG. 16 have the above relationship, it is determined that the instances A and B have the line overlapping arrangement.

As will be described later, since the horizontal line connecting the nets between the instances is drawn on the occupied area of all symbols, the lines do not overlap. The danger of overlapping lines with horizontal lines is when connecting between adjacent instances.

When connecting between adjacent instances, lines may overlap with each other on the same y coordinate (that is, horizontally) as shown in (1) of FIG. 16 and connected to adjacent instances. It is a port.

The reason for the overlap is that the ports are at the same y-coordinate, so either instance is offset slightly (with less than the smallest pin between the instances) so that the ports are not at the same y-coordinate.

By shifting, the ports are not on the same y-coordinate, so that the horizontal lines do not overlap. [Wiring area determination unit: step S7 in FIG. 1] FIG. 18 to FIG. 24 The above is the requirement for the line that connects the instances in the horizontal direction. The line that vertically passes between the adjacent instances is as shown in FIG. It is decided by the port number of the instance like.

That is, if the line connected to the port n is a vertical line in the wiring between the instances, the vertical line passes through the position of the nth vertical line in FIG.

With the above arrangement, the vertical lines do not overlap each other and the port lines can be connected, but since they are redundant, an extra gap is left.

Therefore, by predetermining the direction of the line connected to the output port and the input port of each instance, it is possible to eliminate an extra gap between adjacent instances.

First, the direction of the line coming out from the output port of each instance is obtained.

As shown in (1) of FIG. 19, when the y-coordinates of more than half of the sink ports of a net are higher than the y-coordinates of the sources of the net, wiring as shown in (2) of FIG. And In this case, the source extends up and the sink descends from the top.

Further, as shown in (1) of FIG. 20, when the y-coordinates of more than half of the sink ports of a net are lower than the coordinates of the source of the net, wiring as shown in (2) of FIG. become. In this case, the source extends down and the sink climbs up from the bottom.

Further, as shown in FIG. 21, the source a upwards →
Source b to bottom → sink c from bottom → sink d from top
In the order of, the wiring position of the line running vertically between the instances (not the x coordinate but the number from the right) is obtained.

However, when the instances on both sides are connected by a single line and also by a straight line like the ports 8 and 4'in FIG. 21, the wiring position of that line is not obtained (since there is no bend).

In addition, ports 1 and 4, 2 and 5, 3 in FIG.
And 6, 2'and 5 ', 1'and 3', the same x without the vertical lines connecting each port intersecting.
In the case of drawing on the coordinate, it is possible to eliminate the extra gap by giving the same position of the x-coordinate to each pair of ports as shown in FIG.

Further, as shown in FIG. 23, when a line is commonly connected to a plurality of ports of the instances in the same arrangement stage, the wiring positions of the vertical lines are made the same as in FIG. Make sure there are no extra gaps in between.

Finally, the x-coordinate (distance between arranged steps) at which the instance of each step is arranged is obtained from the number of lines passing between the adjacent instances.

In FIG. 24, the reference x coordinate of the left instance is x '= x + D + nΔx.

As described above, the vertical lines connected to the ports can be prevented from overlapping each other by passing through the predetermined place.

Further, since the place where the vertical line passes is determined for each line direction (source in the order of → source in the direction → source from the bottom → sync from the bottom → sync from the top), the generated lines have overlapping portions. Since it disappears, it is possible to generate a circuit diagram that easily follows the logic. [Pull-up / pull-down instance processing unit: Step S8 in FIG. 1] FIG. 25 As shown in FIG. 25, after all input external terminals are arranged, pull-up / pull-down instances (constant instances) are arranged at the x-coordinate positions of the input external terminals. Yes (Pull-up Z01 is up, pull-down Z00 is down) Pull-up and pull-down instances (constant instances) are always placed in fixed positions such as above and below the same x coordinate as the input external terminal. It becomes easy to understand which instance to connect to and which instance it is connected to. [Connection Information Table Sorting Unit: Step S9 in FIG. 1] FIG.
6-FIG. 27 As shown in FIG. 26, the net table A is created. This is the same as the connection order for one net. The connection destination arrangement stage table B is sorted in ascending order or descending order using the number of stages as a key as shown in FIG. Similarly, the connection destination port table C is sorted in ascending order or descending order using the port number assigned by the sorting by the port ID of the previous instance as a key.

Since the connection information table has the same connection structure as the net connection, the connection can be easily performed by extracting the connection ports in the storage order of the table.

By sorting the connection destination arrangement stage number table B in ascending order or descending order by the number of stages, the starting point and the end point of the arrangement stage when wiring is performed on the net can be known.

Similarly, by sorting the connection destination port table C in ascending or descending order by port number, the starting point and the ending point of the port at the time of wiring at each placement stage can be known [wiring processing unit: step S10 in FIG. 1]. 28-29 When a port between adjacent instances can be drawn by one line, a line is drawn by a straight line or (horizontal → vertical → horizontal). Although not adjacent to each other, if you can draw a port between instances with one line and it does not overlap with the occupied area of any instance, draw a line with a straight line or (horizontal → vertical → horizontal).

In addition to the above, when one net has a plurality of sources or sinks, the wiring method as shown in FIG. 28 is performed.

That is, in FIG. 28, FIG. 28 (1) shows a state in which no wiring is provided. Next, draw a net connected to the sink ports of the instances in the same row [Fig.
(2)]. Next, a line connected to the source port is drawn [Fig. 28 (3)].

Next, a horizontal line connecting the syncnets of the instances of each stage is wired in the symbol occupation area [FIG.
8 (4)]. Finally, the horizontal line is connected to each sync net [Fig. 28 (5)].

When one net has a plurality of sink destinations, wiring is performed as follows. By connecting the sinks in the same row, a group of the same net can be created in each arrangement row.

When not only the sink but also a plurality of sources exist in the net, a group of source nets is similarly formed in each arrangement stage, and connection is performed by a line extending vertically from one horizontal line.

In order to generate the entire net, the groups of sync nets and source nets generated at each placement stage are set to 1
Since it suffices to connect the horizontal line of the book to the vertically extended line, the net generation process can be easily performed.

Here, as shown in FIG. 29A, the horizontal line connecting the nets between the instances is drawn on the occupied area of all symbols. At this time, if there is a line connecting the instances in the distant stages, as shown in FIG. 29 (2), the occupied area AR of all the symbols is expanded to include the new line, and after the horizontal lines are wired, all the symbols are occupied. Set a new area.

As described above, in the case of wiring the instances of the number of layout steps that are not adjacent to each other, the horizontal lines connecting the nets between the instances are always drawn on the occupied area of all the symbols so that the horizontal lines connecting the nets between the instances overlap each other. Will not happen. This utilizes the fact that no line exists on or outside the occupied area of all symbols.

When a line is drawn on the occupied area of all symbols, the occupied area of all symbols is expanded to include the line so that the next line does not overlap with that line.

The circuit diagram is prepared by the method of the present invention by the above-mentioned procedure. In addition, in the above description of the procedure, the case where the additional numbers are sorted in ascending order has been described, but the method of the present invention is not limited to this, and conversely, it is also possible to sort in descending order. [Drawing Data Generation Unit: Step S11 in FIG. 1] As described above, the coordinate position where each instance is arranged, the wiring, etc. are specified. At this time, the created data is table data expanded on the memory. Therefore, the drawing data generation unit 11 is converted into data that can be output to a printer or a monitor and stored in the storage device 2 as a drawing data file.

Further, if necessary, it is output by a printer or a monitor. 30 and 31 are examples of circuit diagrams output by implementing the above-described circuit diagram creating method of the present invention. From this figure, the coordinate position of the instance and the wiring status can be easily understood.

[0086]

As described above according to the procedure according to the drawings, according to the method of the present invention, unlike the conventional method of avoiding obstacles, the area where wiring can be performed is secured in advance from the layout information. There is.

Therefore, there is no need for the process of checking for obstacles, which has the effect of enabling high-speed drawing generation, and shortens the time required for turnaround of circuit design by trial and error and the time until fault correction. It is possible,
It greatly contributes to improving the efficiency of circuit design.

[Brief description of drawings]

FIG. 1 is a preferred configuration diagram of a circuit drawing generation method to which the present invention is applied.

FIG. 2 is a diagram illustrating the number of stages of output external terminals.

FIG. 3 is a diagram illustrating the number of arrangement steps.

FIG. 4 is a diagram illustrating the number of stages of input external terminals.

FIG. 5 is a diagram illustrating a placement stage of instances.

FIG. 6 is a diagram illustrating the number of stages of instances that are latch-connected.

FIG. 7 is a diagram illustrating the structure of an instance information table.

FIG. 8 is a diagram illustrating sorting of an instance information table.

FIG. 9 is a diagram illustrating an instance name in macro expansion.

FIG. 10 is a diagram illustrating an instance arrangement reference point.

FIG. 11 is a diagram illustrating an arrangement when a straight line is connected to an instance of a stage on the left side.

FIG. 12 is a diagram illustrating an arrangement when the instance on the left adjacent stage is not connected by a straight line.

FIG. 13 is a diagram illustrating an arrangement when a straight line is connected to an instance on the right adjacent stage.

FIG. 14 is a diagram illustrating an arrangement when the instance on the right adjacent stage is not connected by a straight line.

FIG. 15 is a diagram illustrating rearrangement of instances by port ID.

[Fig. 16] Fig. 16 is a diagram for describing arrangement adjustment of instances.

FIG. 17 is a diagram illustrating checking whether lines overlap.

FIG. 18 is a diagram illustrating a bending position of a line.

FIG. 19 is a diagram illustrating a line direction (source to the top and sink from the top).

FIG. 20 is a diagram illustrating a line direction (source to the bottom and sink from the bottom).

FIG. 21 is a diagram illustrating a vertical line that passes between instances.

FIG. 22 is a diagram illustrating adjustment of the bending position of a line.

FIG. 23 is a diagram illustrating a case where a net is connected to a plurality of ports in the same arrangement stage.

FIG. 24 is a diagram illustrating adjustment when a net is connected to a plurality of ports in the same arrangement stage.

FIG. 25 is a diagram illustrating arrangement of pull-up / pull-down instances.

FIG. 26 is a diagram illustrating a net table.

FIG. 27 is a diagram illustrating sorting of the connection destination arrangement stage table or the connection destination port table.

FIG. 28 is a diagram illustrating a wiring method.

[Fig. 29] Fig. 29 is a diagram describing a change of a symbol occupied area.

FIG. 30 is an example of a circuit diagram drawn by the circuit drawing creation method of the present invention.

FIG. 31 is another example of a circuit diagram drawn by the circuit drawing creating method of the present invention.

[Explanation of symbols]

 1 Netlist storage device 2 Drawing data storage device 3 Circuit drawing output S1 Table conversion function S2 Stage numbering processing unit S3 Instance information table sorting unit S4 Instance placement y coordinate determination unit S5 Instance port ID sorting unit S6 Instance placement y coordinate duplication adjustment unit S7 wiring area determination unit S8 pull-down / up-down instance processing unit S9 connection table sorting unit S10 wiring processing unit S11 drawing data generation unit

Claims (10)

[Claims] 1. The number of arrangement stages of all output external terminals is 1 stage.
When the input port of the output external terminal is connected to an instance of 1 input and 1 output, the instance is regarded as an output buffer and the number of arranged stages is fixed to 2 and the input port of the input external terminal has 1 input. When one output instance is connected, the instance is regarded as an input buffer, the number of layout stages is fixed to (maximum number of stages-1), the number of wiring stages of all input external terminals is fixed to the maximum number of stages, and the output external terminals are also fixed. The number of wiring steps n for instances that are neither output buffers, input buffers, nor input external terminals is 2 <n
<(Maximum number of stages -1). 2. The circuit drawing generation according to claim 1, further comprising checking whether or not the instances are latch-connected to each other, and when the instances are latch-connected, the number of arrangement stages of the instances is made the same. Method. 3. The method according to claim 1, further comprising a table that manages an instance table storing the information of the instance for each number of arrangement steps, and rearranging the instance table in ascending or descending order with the instance name as a key. A circuit drawing generation method characterized by the above. 4. The method according to claim 1, wherein the output ports of the instances of each arrangement stage are numbered consecutively from top to bottom, and the input ports of the instances are checked,
The instance table is rearranged in ascending or descending order by using the smallest number of the output ports of the instance arranged on the left side of the instance as the ID number of the instance, and using the ID number as the instance of each arrangement stage. A method for generating a circuit drawing, which is characterized by the above. 5. The method according to claim 1, 2 or 3, wherein if there is an input buffer as a stage for starting the arrangement, the maximum stage number-
1) If there are no input buffers (maximum number of stages-2), the number of stages is smaller than that of the instance. For an instance with a smaller number of stages to be arranged, the output port of the stage next to the left of the instance and the input port of the instance are as much as possible. Arrangement y-coordinates are determined so that they are connected by a straight line, and the instance of the input external terminal that is the maximum number of stages is the input port of the instance of (maximum stage number-1) or (maximum stage number-2) stages and the output port of the instance. A method for generating a circuit drawing, characterized in that the arrangement y-coordinate is determined so as to be connected by a straight line as much as possible. 6. The method according to claim 5, wherein it is checked whether or not the layout is such that lines are overlapped when wiring is performed in adjacent instances, and as a result of the check,
A method for generating a circuit drawing, wherein if the lines overlap, the arrangement y coordinate of either instance is shifted downward by Δ (<minimum pin spacing). 7. The method according to claim 1, wherein a vertical line passing between adjacent instances passes through an x-coordinate position determined by an ID number of a port of an instance connected to the line. Circuit drawing generation method. 8. The circuit drawing generation method according to claim 7, wherein the pull-up / pull-down instance (constant instance) is arranged at the same x coordinate position as the input external terminal. 9. The system according to claim 7, wherein when one net has a plurality of sinks, the nets connected to the sync ports of the instances in each stage are connected and the horizontal line connecting the sync nets is occupied by all symbols. A method for generating a circuit drawing, characterized by connecting a horizontal line to each sync net after wiring on the area. 10. A circuit diagram according to claim 7, wherein after the horizontal line connecting the instances of each arrangement stage is wired on the occupied area of all symbols, the occupied area of all symbols is newly set. Generation method.