JPH0969545A - Semiconductor integrated circuit test apparatus and test method thereof - Google Patents

Abstract

(57) Abstract: Even if the chip size is different, it is possible to reduce the cost by minimizing the change of the corresponding probe card and making it common. SOLUTION: The conductor patterns 5 are parallel to each other in a direction orthogonal to the corresponding one side of the semiconductor chip 1 with a predetermined line width and extend to the vicinity of a diagonal line of the semiconductor chip 1 at the same intervals as the bonding pads 2, respectively. When the probe card 3a formed for each of them and the probe card 3a are superposed on the center line of the semiconductor chip 1 and brought into close contact with each other, protrusions are made at positions where the center lines of the conductor patterns 5 overlap the centers of the corresponding pads 2. When the probe cards 3a and 3b are stacked on the center line of the semiconductor chip 1 and closely contacted with each other by using the probe card 3b provided with electrodes, the pad 2, the conductive pattern 5 and the protruding electrode are electrically connected. In addition, these probe cards
Each is made of a transparent insulating substrate.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit testing apparatus and a testing method therefor, and more particularly to a semiconductor having improved probing means used in testing electrical characteristics of a plurality of semiconductor chips formed on a wafer. The present invention relates to an integrated circuit test device and a test method thereof.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have come to be used in a wide range of devices including industrial and consumer devices as the degree of integration thereof has increased with the improvement of fine processing technology. For this reason, the tendency of small-quantity, large-variety products has become prominent, as well as packages of shapes that are easy to use for respective devices such as miniaturization, thinning, cost reduction, and multi-pinning.

When testing the electrical characteristics of these semiconductor integrated circuits, a semiconductor tester (IC tester) is used. The IC tester stores in advance various information for confirming the electrical characteristics of the semiconductor integrated circuit to be tested. By supplying this information to the semiconductor integrated circuit under test, the semiconductor is tested. Check whether the integrated circuit is performing a predetermined operation.

Further, the electric characteristics of the semiconductor integrated circuit under test are tested by sequentially inputting the information of the operation result into the IC tester and comparing it with the expected value stored in advance.

The inspection process in the manufacturing process to which this IC tester is first applied is a wafer selection inspection process. In order to perform a test by an IC tester in a wafer state in which a large number of chips, each having a predetermined circuit function formed on a semiconductor substrate in a diffusion process, are arrayed, contact is made with each bonding pad of the semiconductor chip, called a probe card. Then I
Interface means is used to intervene in the input / output of signals with the C tester.

This probe card is prepared in advance for each semiconductor integrated circuit having a different chip size and number of pins, and is exchanged according to the chip shape of the semiconductor integrated circuit under test and set in the test station of the IC tester.

As described above, in the conventional probe card of this type, it is common to replace the probe card for each type of semiconductor integrated circuit, chip size or pin number, which is small. The number of probe cards prepared in advance has increased rapidly because the tendency of the variety has become remarkable.

That is, referring to FIG. 5A showing a plan view of an example of a main part of a conventional probe card and FIG. 5B showing a sectional view thereof, a station 4 of a test head of an IC tester is shown. The wafer 1 is mounted, and the probe needles 9 that intervene to contact the bonding pads of the semiconductor chips 2 formed in large numbers on the wafer 1 in a one-to-one relationship to input and output signals are arranged on the back surface of the probe card 8. It is set up.

At the time of wafer selection inspection, the station 4 on which the wafer is mounted is horizontally moved and positioned so that the bonding pad of the semiconductor chip and the tip of the probe needle 9 are overlapped with each other, and then the station 4 is pushed upward to raise the probe needle. 9 and the bonding pad are brought into close contact with each other.

Thereafter, when a predetermined power supply voltage and a test signal are supplied from the IC tester body to the probe card 8,
These signals are supplied to the bonding pad via the probe needle 9. The output signal from the semiconductor chip 1 follows the opposite route and is supplied from the bonding pad to the IC tester through the probe needle 9 to the IC tester, and is compared with an expected value prepared in advance, and The quality is judged.

An example of another probing means of this kind is described in Japanese Patent Laid-Open No. 2-237131. The test apparatus and test method described in the publication show FIG. 6 (a) showing a cross-sectional view of the main part configuration, FIG. 6 (b) showing a plan view of an insulating sheet, and a pad at the tip of a conductive pattern circuit. Referring also to FIG. 6C showing a plan view, a large number of electrode bumps 1a made of metal such as gold are formed around the upper surface of the semiconductor chip 1. An insulator sheet 10 is supported on the semiconductor chip 1 by a transmission circuit board 11 and a test head. The insulating sheet 10 has a quadrangular shape and is made of a transparent insulating material such as glass, and has conductive pattern circuits equal to the number of the semiconductor chips 1a formed on the lower surface thereof. The conductive pattern circuit 12 extends from the outer periphery of the insulator sheet 10 toward the center portion, and the center coordinate position of each tip is the center coordinate of the electrode pad so as to contact the electrode pad of the semiconductor chip 1 during the wafer selection inspection. Match the position.

Referring to FIG. 6 (b) showing a plan view of the pads at the tips of the conductive pattern circuits 12, circular pads are formed at the tips to facilitate contact with the electrode pads.

[0013]

As described above, in the conventional probe card, when the wafer is brought into contact with the probe needle of the probe card by pushing up the station during the wafer inspection, the probe needle is attached to the bonding pad of the semiconductor chip. It is necessary to precisely design the disposition positions of the respective probe needles so that the tips contact with each other with certainty.

However, due to recent rapid progress in device technology, the circuit function formed on a semiconductor chip has become complicated and large in scale, and the number of pins has been increased accordingly, for example, 30.
Semiconductor integrated circuits with 0 or more pins have also been realized. As a result, the number of bonding pads that the semiconductor chip has also increases, so the pad pitch becomes narrower, which makes the design of the probe card extremely difficult, and requires careful attention when handling the probe card during semiconductor chip inspection. To do.

Further, each probe needle of the probe card is fixed to an insulating substrate constituting the probe card,
Since the structure is such that it directly contacts each electrode pad of the semiconductor chip, if the number of bonding pads increases or decreases and the pad position changes, it is necessary to create a corresponding probe card each time, which is a factor that increases the manufacturing cost. It was also

Furthermore, the pressure applied to the entire probe needle by bringing the probe needle and the bonding pad into contact with each other during the wafer selection inspection causes the probe needle itself to gradually shift its position, and the wafer selection inspection is normally performed. Can not be carried out.

On the other hand, in the case of a probe card which uses a conductive pattern circuit instead of the probe needle, the conductive pattern is formed by etching, so that the pattern pitch can be narrowed, and probing can be performed corresponding to the increase in the number of pins. It is easy to increase the number of conductive patterns. However, since the conductive pattern circuit is formed on the insulating sheet, and the tip of the conductive pattern circuit must be designed to contact the protruding electrode provided on the semiconductor chip, the bonding pad position of the semiconductor chip may change. Every
It is necessary to create a probe card, which also causes an increase in manufacturing cost.

The object of the present invention has been made in view of the above-mentioned drawbacks. Even if the probe needle is repeatedly used, the positional deviation of the probe needle does not occur, and the increase in the number of electrode pads accompanying the increase in the number of pins is prevented. However, the object is to provide a probe card that can be easily handled and is easy to handle.

[0019]

The semiconductor integrated circuit testing apparatus of the present invention is characterized by a wafer having a predetermined function and a plurality of square chip size semiconductor chips formed on a semiconductor substrate. A semiconductor integrated circuit having a probing means that contacts each bonding pad of the semiconductor chip and intervenes in inputting and outputting a signal to and from an IC tester when the electrical characteristics of the semiconductor chip are measured on the wafer. In the test apparatus, the probing means is a conductor pattern in which the probing means are parallel to each other in a direction orthogonal to a corresponding one side of the semiconductor chip with a predetermined line width and extend to a vicinity of a diagonal line of the semiconductor chip at the same intervals as the bonding pads. Respectively include a first probe card formed on each side corresponding to the four sides of the semiconductor chip. .

Further, in the probing means, when the first probe card is placed on and closely adhered to the center line of the semiconductor chip, the center lines of the conductor patterns overlap the centers of the corresponding bonding pads. It may comprise a second probe card having protruding electrodes disposed at respective positions.

Further, the probing means causes the bonding pad, the conductive pattern, and the protruding electrode to be electrically connected when the first and second probe cards are overlapped and closely contacted with each other on the center line of the semiconductor chip. It is also possible to make a physical connection.

Furthermore, by using the probing means having the conductive pattern and the protruding electrode, even in a semiconductor chip in which the number of the bonding pads is increased and the pad interval is reduced, the line width of the conductive pattern and the protrusion are also formed. It can be tested by forming electrodes each having a size corresponding to a predetermined minimum distance between the bonding pads.

The first and second probe cards are each made of a transparent insulating substrate.

A feature of the semiconductor integrated circuit testing method of the present invention is a wafer having a plurality of square chip-size semiconductor chips having a predetermined function formed on a semiconductor substrate, wherein each of the semiconductor chips is a wafer. A semiconductor integrated circuit test method using a probing means that is in contact with each bonding pad of the semiconductor chip and intervenes in inputting and outputting a signal with an IC tester when the electrical characteristics of the semiconductor chip are measured on the wafer. As means, conductive patterns extending in parallel with a predetermined line width in a direction orthogonal to the corresponding one side of the semiconductor chip and extending to the vicinity of a diagonal line of the semiconductor chip at the same intervals as the bonding pads of the semiconductor chip, respectively. The first probe card formed corresponding to the four sides, and the first probe card on the center line of the semiconductor chip. When the probe cards of (1) and (2) are closely contacted with each other, by using the second probe card in which the protruding electrodes are respectively arranged at the positions where the center lines of the conductor patterns overlap the centers of the corresponding bonding pads, The first and second probe cards are respectively overlapped and closely adhered on the center line of the semiconductor chip so that the bonding pad, the conductive pattern, and the protruding electrode are electrically connected to each other. Measuring the electrical properties of each of the chips on the wafer.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION In an ASIC using an automatic placement / wiring method for gate arrays, standard cells, etc., the shape of the island of the lead frame on which the semiconductor chip is mounted is square. Is advantageous in terms of design time and cost, and is generally designed to be a square chip except for special cases. The present invention has been made paying attention to this point.

First, a first embodiment of the present invention will be described with reference to the drawings. FIG. 1A is a plan view showing a main part of a first embodiment of a semiconductor integrated circuit testing apparatus of the present invention, and FIG. 1B is a partial cross section taken along line XX ′. It is a figure. Referring to FIGS. 1A and 1B, electrical characteristics of each semiconductor chip 1 of a wafer 2 on which a large number of semiconductor chips 1 having a predetermined function formed on a semiconductor substrate are formed on the wafer. At the time of measurement, it has probe cards 3a and 3b which come into contact with the respective bonding pads of the semiconductor chip 1 and intervene in the input / output of signals with the IC tester. The arrangement relationship between these probe cards 3a and 3b and the semiconductor chip 1 is that the semiconductor chip 1 is mounted on the test bed 4 of the IC tester.
Is mounted, the probe card 3b is arranged immediately above it, and the probe card 3a is further arranged thereon, and they are arranged in close contact with each other during measurement.

This probe card 3a is a semiconductor chip 1.
When the semiconductor chips 1 are stacked on top of each other, they extend in the direction orthogonal to the corresponding sides of the semiconductor chip 1 to the vicinity of the diagonal line of the semiconductor chip 1 with a predetermined line width in parallel and at the same intervals as the bonding pads. The existing conductor pattern is formed on each side. That is, the conductor patterns extending on each side are arranged such that the pattern located at the center is the longest and the both ends are the shortest to present a triangular shape, and these triangular patterns are arranged on the four sides. It is supposed to exist.

Referring to FIG. 2, which shows a partially enlarged plan view of the semiconductor chip 1, the probe card 3a, and the probe card 3b which are arranged in close contact with each other, referring to FIG. When the probe card 3a is arranged between the cards 3a and is closely adhered to the center line of the semiconductor chip 1, the center line Y-Y 'of the conductor pattern 5 with respect to the center of the bonding pad 6 of the corresponding semiconductor chip 1 respectively. The protruding electrodes 7 are arranged at positions where they overlap.

That is, the protruding electrodes 7 are arranged on all the bonding pads 6, for example, on the bonding pads 6 on the center line XX ′, and the conductive patterns 5 are overlapped on the protruding electrodes 7. There is.

Referring to FIG. 3 showing a sectional view taken along the center line YY ′ and FIG. 4 showing a sectional view taken along the center line XX ′, respectively, the probe card will be described. The probe card 3b is closely arranged below the conductive pattern 5 provided on the lower surface of 3a, and one surface of the protruding electrode 7 provided on the probe card 3b is in contact with the lower surface of the conductive pattern 5. The other surface of the projecting electrode 7 comes into contact with the bonding pad 6 of the semiconductor chip 1 located right under each of them.

The probe cards 3a and 3b are made of transparent insulating substrates. The bump electrode 7 is formed of a metal such as Au so as not to wear due to repeated contact with the bonding pad 6.

The test method of the semiconductor chip 1 using the above-mentioned probe cards 3a and 3b is such that the semiconductor chip 1 is mounted on the station 4 of the IC tester, and the probe card 3b on which the protruding electrodes 7 are arranged. , The probe cards 3a provided with the conductive pattern circuits 5 are overlapped with each other and brought into close contact with the semiconductor chip 1.

At this time, since the probe cards 3a and 3b are each made of a transparent insulating substrate such as an acrylic plate, the bonding pad 6 of the semiconductor chip 1 has the conductive pattern 5 and the protruding electrode 7 in alignment. It becomes possible to align.

That is, referring again to FIG. 3, it is confirmed that the protruding electrode 7 of the probe card 3b and the conductive pattern 5 of the probe card 3a are correctly overlapped on the bonding pad 6 through the acrylic transparent substrate. .
Therefore, it is possible to avoid a malfunction due to contact with a pad other than the predetermined bonding pad.

By using the probe card having the above-mentioned structure, when testing a product having a different chip size, it is not necessary to change the probe card 3a having the conductive pattern 5, and the probe having the protruding electrode 7 is not required to be changed. It can be dealt with by changing only the card 3b.

That is, the pitch of the bonding pads 6 of the semiconductor chip 1 is designed to be constant, so that when the chip size increases, the position of the protruding electrode 7 on the probe card 3b is set to the conductive position on the probe card 3a. This can be dealt with by preparing a probe card 3b formed at a position shifted outward by a predetermined position along the center line YY 'of the pattern 5. Of course, since the number of bonding pads is also increased, it is possible to deal with it by sequentially using the patterns arranged next to both ends of the conductive pattern 5 which was originally used.

Similarly, in the case of a product having a smaller chip size, the position of the protruding electrode 7 on the probe card 3b is arranged along the center line YY 'of the conductive pattern 5 on the probe card 3a. This can be dealt with by preparing the probe card 3b formed at a position shifted inward by a predetermined position. In this case as well, the number of bonding pads naturally decreases, so the conductive pattern 5 originally used
This can be dealt with by not sequentially using the patterns arranged next to both ends of the.

By using the above-described structure, if the chip size is a semiconductor chip having a square shape, the pitches of the bonding pads 6 are standardized to commonly use the probe card 3a having the conductive patterns 5 matched to the pitch. Therefore, by changing only the probe card 3b corresponding to the chip size, it can be used for testing all the semiconductor chips having the above-mentioned conditions, and the cost of manufacturing an expensive probe card is lower than that of the conventional one. It can be reduced to about 1/8 or less.

Further, the probe card 3a having the conductive pattern 5 and the probe card 3b having the protruding electrode 7 are provided.
Even in a semiconductor chip in which the number of bonding pads is increased and the pad spacing is reduced in order to cope with the increase in the number of pins, the line width of the conductive pattern 5 and the protruding electrode 7 are set to the predetermined minimum spacings of the bonding pads. By forming with a corresponding size, it can be applied to a test of a semiconductor chip having a large number of bonding pads.

[0040]

As described above, the semiconductor integrated circuit testing apparatus and the testing method according to the present invention are parallel to each other with a predetermined line width in the direction orthogonal to the corresponding one side of the semiconductor chip and are the same as the bonding pad. When the first probe card in which the conductor patterns extending to the diagonal of the semiconductor chip at intervals are formed on the respective sides and the first probe card is placed on the center line of the semiconductor chip and brought into close contact with each other, A second probe card having protruding electrodes arranged at positions where the center line of the conductor pattern overlaps the center of the corresponding bonding pad is used, and the first and second probe cards are respectively arranged on the center line of the semiconductor chip. When the layers are brought into close contact with each other, the bonding pad, the conductive pattern, and the protruding electrode are electrically connected, and Since each of these probe cards is made of a transparent insulating substrate, the pitch of the bonding pads should be designed to be constant so that when the chip size increases, the position of the protruding electrode 7 on the second probe card will be changed. In the case of a product in which the chip size is reduced outward by a predetermined position along the center line of the conductive pattern on the first probe card, the placement position of the protruding electrode on the second probe card is set to the first position. This can be dealt with by preparing a second probe card formed at a position shifted inward by a predetermined position along the center line of the conductive pattern on the probe card.

Therefore, in the case of a semiconductor chip having a square chip size, by unifying the arrangement pitch of the bonding pads, it is possible to commonly use the first probe card having the conductive pattern matched to the pitch. By changing only the second probe card corresponding to the chip size, it can be used for testing all the semiconductor chips having the above-mentioned conditions, and the manufacturing cost of the expensive probe card is about 1/100 of the conventional cost. It can be reduced to 8 or less.

Further, by using the probing means having the conductive pattern and the protruding electrode, even in a semiconductor chip in which the number of bonding pads is increased and the pad interval is reduced, the line width of the conductive pattern and the protruding electrode are respectively set to predetermined values of the bonding pad. It can be applied to a test of a semiconductor chip having a large number of bonding pads by forming it with a size corresponding to the minimum distance.

Furthermore, during the test, the protruding electrode and the bonding pad are moved in the vertical direction to be brought into contact with each other, so that there is no displacement due to deformation of the tip of the conventional probe needle, which contributes to improvement in reliability.

[Brief description of drawings]

FIG. 1A is a plan view showing a main part of a first embodiment of a semiconductor integrated circuit testing apparatus of the present invention. FIG. 1B is a partial cross-sectional view taken along the line XX ′ in FIG.

FIG. 2 is a partially enlarged plan view when the semiconductor chip 1, the probe card 3a, and the probe card 3b are arranged in close contact with each other.

3 is a cross-sectional view taken along the line YY 'in FIG.

FIG. 4 is a cross-sectional view taken along the line XX ′ in FIG.

FIG. 5A is a plan view showing an example of a main part of a conventional probe card. (B) It is sectional drawing.

FIG. 6A is a cross-sectional view showing the configuration of the main part of another conventional example. (B) It is a top view of an insulator sheet. FIG. 6C is a plan view showing a pad at the tip of the conductive pattern circuit.

[Explanation of symbols]

 1 Semiconductor Chip 2 Wafers 3a, 3b, 8 Probe Card 4 Station 5 Conductive Pattern 6 Bonding Pad 7 Projection Electrode 9 Probe Needle 10 Insulating Sheet 11 Transmission Circuit Board 12 Conductor Pattern Circuit 12a Pad at the End of Conductor Pattern

Claims (6)

[Claims] 1. A wafer in which a plurality of semiconductor chips each having a predetermined function and having a square chip size are formed on a semiconductor substrate, and the electrical characteristics of each of the semiconductor chips are measured on the wafer. At this time, in a semiconductor integrated circuit testing apparatus having a probing means that contacts each bonding pad of the semiconductor chip and intervenes in inputting / outputting a signal to / from an IC tester, the probing means includes one side corresponding to the semiconductor chip. Conductor patterns parallel to each other in a direction perpendicular to each other with a predetermined line width and extending to the vicinity of the diagonal line of the semiconductor chip at the same intervals as the bonding pads are formed on the respective sides corresponding to the four sides of the semiconductor chip. A semiconductor integrated circuit testing device comprising a first probe card. 2. The probing means, when the first probe card is superposed on and closely adhered to the center line of the semiconductor chip, the center lines of the conductor patterns overlap the centers of the corresponding bonding pads. 2. The semiconductor integrated circuit testing device according to claim 1, further comprising a second probe card having protruding electrodes arranged at respective positions. 3. The probing means electrically connects the bonding pad, the conductive pattern and the protruding electrode to each other when the first and second probe cards are superposed and closely contacted with each other on the center line of the semiconductor chip. 3. The semiconductor integrated circuit testing device according to claim 1, wherein the semiconductor integrated circuit testing device is electrically connected. 4. The line width of the conductive pattern and the protruding electrode even in a semiconductor chip in which the number of the bonding pads is increased and the pad interval is reduced by using the probing means having the conductive pattern and the protruding electrode. 4. The semiconductor integrated circuit testing device according to claim 1, wherein the testing can be performed by forming each of the bonding pads with a size corresponding to a predetermined minimum distance between the bonding pads. 5. The semiconductor integrated circuit testing device according to claim 1, wherein the first and second probe cards are each made of a transparent insulating substrate. 6. A wafer in which a plurality of semiconductor chips each having a predetermined function and having a square chip size are formed on a semiconductor substrate, and the electrical characteristics of each semiconductor chip are measured on the wafer. In a method of testing a semiconductor integrated circuit using a probing means that contacts each bonding pad of the semiconductor chip and intervenes in inputting / outputting a signal to / from an IC tester, the probing means corresponds to one side of the semiconductor chip. Conductor patterns that are parallel to each other in a direction perpendicular to each other with a predetermined line width and extend to the vicinity of a diagonal line of the semiconductor chip at the same intervals as the bonding pads are formed corresponding to the four sides of the semiconductor chip, respectively. When the probe card and the first probe card are overlapped and closely contacted with each other on the center line of the semiconductor chip, Using the second probe card in which the protruding electrodes are respectively arranged at the positions where the center lines of the conductor patterns overlap the centers of the corresponding bonding pads, the first and the second probe cards are provided on the center line of the semiconductor chip. By stacking and closely contacting the second probe cards, the bonding pads, the conductive patterns, and the protruding electrodes are electrically connected to each other so that the electrical characteristics of each of the semiconductor chips are measured on the wafer. A method for testing a semiconductor integrated circuit, which is characterized by: