JPH0969737A - Amplifier circuit - Google Patents

Abstract

(57) Abstract: An amplifier circuit having good PSRR characteristics without requiring a voltage source with a small amount of noise from the outside for improving PSRR, and without inviting an increase in the number of elements. To provide. A differential pair including first and second transistors (T1, T2) for inputting a differential input signal, and a current source (I1) for supplying an operating current to the differential pair, Third and fourth transistors (T3, T4) connected to a cascade for inputting the differential output current of the differential pair, and a load (T5) for converting the output currents of the third and fourth transistors into a voltage. , T6), amplifying means (-A) for inverting and amplifying the converted voltage, and phase compensating means (CF) provided between the current input terminal of the fourth transistor and the output terminal of the amplifying means. Composed.

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a high PSRR (Pow)
er Supply Rejection Ratio).

[0002]

2. Description of the Related Art A high gain amplifier circuit having two or more amplifier stages is often used with a feedback circuit. At this time, a phase compensation capacitor is added to prevent oscillation and a phase margin is provided. In the case of a two-stage amplifier circuit, the phase compensation capacitance is
It is connected between the output terminal and the input terminal of the second amplification stage. This is commonly called mirror compensation. In this compensation method, as shown in FIG. 4, when the frequency of the transistor forming the second amplification stage becomes high, the phase compensation capacitance causes a short-circuiting diode connection between the base and the collector, and the transistor is connected to the emitter. Power supply noise is transmitted to the output from the power supply line. Therefore, in Miller compensation, PSRR (Power Supply Rejection Ratio) that indicates how much the fluctuation of the power supply voltage is suppressed at the output terminal
However, there is a drawback that it deteriorates at high frequencies.

A phase compensation method for improving this is Ribner.
("Design Techniques for CascodedCMOS Op Amps with
Improved PSRR and Common-Mode Input Range, "IEEE
JSSC vol.sc-19, No.6, pp.919-925 Dec. 1984). This includes a gate ground circuit in the phase compensation path, and prevents the PSRR from deteriorating by preventing the diode connection even if the frequency becomes high.

However, the gate of the transistor for grounding the gate is biased with a fixed bias voltage. For example, when a bias voltage is generated with reference to the power supply voltage as shown in FIG. There is a problem in that PSRR cannot be improved after all because it is transmitted to the output through the transistor of the grounded-gate circuit and the phase compensation capacitance.

[0005]

As described above, the PSRR is
In order to improve the above, the gate bias voltage of the transistor for grounding the gate must be driven by a power supply with less noise different from the power supply of the amplifier circuit, and when the amplifier circuit is integrated into a bias with less noise than the outside. There is the problem that a voltage source and pins for connection are required.

The present invention has been made in view of the above problems of the prior art, and an object of the present invention is to require a voltage source with less noise from the outside for improving PSRR as in the conventional case. And to provide an amplifier circuit having good PSRR characteristics without increasing the number of elements.

[0007]

According to the present invention, a differential pair composed of first and second transistors for inputting a differential input signal, and a current for supplying an operating current to the differential pair. A source, a third and a fourth transistor connected to a cascade for inputting the differential output current of the differential pair, and a load for converting the output current of the third and the fourth transistor into a voltage. It is characterized by comprising an amplifying means for inverting and amplifying the converted voltage, and a phase compensating means provided between the current input terminal of the fourth transistor and the output terminal of the amplifying means.

Further, in the present invention, the third and fourth transistors are biased with a voltage corresponding to a common mode voltage of a differential input signal. Further, in the present invention, the voltage of the common emitter or the common source of the differential pair is used as the voltage according to the common mode voltage of the differential input signals.

[0009]

According to the amplifier circuit of the present invention, the mirror compensating capacitor inserts a transistor constituting the second amplifying stage at a high frequency into the phase compensating path in order to prevent the PSRR from deteriorating due to diode connection. By not fixing the gate bias voltage of the transistor to a voltage corresponding to the common mode voltage of the differential input signals, a voltage source with less noise from the outside can be eliminated.

Further, by using the voltage of the common emitter or the common source of the differential pair as the voltage corresponding to the common mode voltage of the differential input signals, the number of elements is not increased. Embodiments of the present invention will be described below with reference to the drawings. FIG.
It is a figure which shows the amplifier circuit of this invention. A differential pair composed of transistors T1 and T2 for inputting a differential input signal to the gates, a current source I1 for supplying a bias current to a common source of the differential pair, and a bias for the drains of the differential pair, respectively. Current sources I2 and I3 for supplying a current, transistors T3 and T4 connected in cascade to input the output currents of the differential pair to the sources, and a transistor T3.
And an active load composed of transistors T5 and T6 for converting the output current from the drain of T4 into a voltage,
The transistor T4 includes an amplifying means for inverting and amplifying the converted voltage, and a phase compensation capacitance CF provided between the source of the transistor T4 and the output terminal of the amplifying means.
3 and T4 are biased by the common source voltage of the differential pair.

The gates of the transistors T3 and T4 connected in cascade in FIG. 1 are biased by the voltage of the common source of the differential pair, that is, the input common-mode voltage, and the power supply is the same as in the conventional example shown in FIG. Since it is not biased with a constant voltage based on the voltage, the noise of the power supply voltage is not added to the gate of the transistor T4, and the noise of the power supply is not transmitted to the output through the phase compensation capacitor. The PSRR can be increased.
Further, according to this configuration, the bias circuit of the transistors T3 and T4 is unnecessary, so that the circuit scale can be reduced as compared with the conventional example of FIG.

The inverting amplification means can be composed of, for example, a transistor T7 and a current source I4 as shown in FIG. Above, M
Although the description has been made using the OS transistor, a bipolar transistor can be used in the same manner as shown in FIG.

[0013]

According to the amplifier circuit of the present invention, PSRR is eliminated without using a voltage source with less noise from the outside which was conventionally required.
Can be increased. In addition, since the common emitter or common source voltage of the differential pair is used as the voltage corresponding to the common mode voltage of the differential input signals, the number of elements is not increased, and therefore PSRR is improved without increasing the circuit scale. can do.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration of an amplifier circuit of the present invention.

FIG. 2 is a diagram showing a specific configuration of an amplifier circuit of the present invention.

FIG. 3 is a diagram in which an amplifier circuit of the present invention is configured using bipolar transistors.

FIG. 4 is a diagram showing a first conventional example.

FIG. 5 is a diagram showing a second conventional example.

[Explanation of symbols]

 T1 to T7: Transistor CF: Phase compensation capacitance I1 to I4: Current source V1: Biasing means

Claims (3)

[Claims] 1. A differential pair composed of first and second transistors for inputting a differential input signal, a current source for supplying an operating current to the differential pair, and a difference between the differential pair. Third and fourth transistors for inputting a dynamic output current, and the third transistor
And a load for converting the output current of the fourth transistor into a voltage, and an amplification means for inverting and amplifying the converted voltage,
An amplifier circuit comprising: a phase compensation means provided between the current input terminal of the fourth transistor and the output terminal of the amplification means. 2. The amplifier circuit according to claim 1, wherein the third and fourth transistors are biased with a voltage corresponding to a common mode voltage of a differential input signal. 3. The amplifier circuit according to claim 1, wherein a voltage of a common emitter or a common source of the differential pair is used as a voltage according to a common mode voltage of the differential input signals.