JPH0973403A - Divided recording device for trace storage memory of in-circuit emulator device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To analyze program execution states at a plurality of places by a single trial run. SOLUTION: This device consists of the trace storage memory 15 in the in-circuit emulator device and a peripheral control circuit which controls the trace storage memory 15, and the recording method of the trace storage memory 15 of the in-circuit emulator device is recorded while divided into 1, its half, or 1 over a multiple of 1 or 2 (1/X: X is a multiple of 2). Further, the trace storage memory 15 is divided into 1, its half, or 1 over a multiple of 2 (1/X: X is a multiple of 2), 1 or >=2 divided areas are optionally selected as one recording area, and recording to and storaging in the selected areas are performed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION In order to analyze whether an internal circuit of a device for operating a computer device or its program is operating normally, a microprocessor development support device (hereinafter referred to as a general name "in-circuit") is used. (Described as "emulator device") is used to analyze the internal circuit of the computer device and the content / execution state of its program. However, a computer device (a computer device to which an in-circuit emulator device is connected is generally referred to as a “target computer device”, but in the present invention and the present specification, a “target device” to which the “in-circuit emulator device” is connected. The "computer device" is simply referred to as "computer device") is stored and recorded in the trace storage memory inside the in-circuit emulator device, because of the problem of the memory and its control-related circuit, the device address starts from a certain program address. It was possible to store only once for the frame up to the storage allowable range of the prepared memory. In the present invention, the recordable storage capacity of the trace storage memory is set to 1
It is possible to divide (not divide), or half (1/2), or a multiple of 2 (1 / X: X is a multiple of 2) for division recording, and a plurality of divided areas can be recorded. It is to provide an in-circuit emulator device capable of storing the execution status of a program execution point.

[0002]

2. Description of the Related Art Conventionally, in executing / analyzing a program of a computer device, provisional data is given to the program so that the program can be tried while confirming whether or not the initial target data or result is obtained. It was executing / analyzing. Furthermore, in recent years, an in-circuit emulator device has been widely used for analyzing the program. When a program is executed / analyzed by using the conventional in-circuit emulator device, it is difficult to divide the trace storage memory of the in-circuit emulator device because of the relationship between the memory and its control circuit as described above. The present invention, which has not been made, is to provide a division storage device (method) to a new trace storage memory.

[0003]

As described above, in the present invention, a method of dividing the storage capacity per time of the trace storage memory in the in-circuit emulator device for analyzing the program executed by the CPU of the computer device, and the division method. By providing a method for variably designating the size of the recording capacity per location within a limited range,
The memory to be stored in the trace of the in-circuit emulator device, which was able to analyze only one part of the conventional program execution status, was divided into arbitrary integer fractions, and the program execution status of another part was divided into each divided part. Is stored in the trace storage memory. In addition, one or two or more of which the storage capacity is divided once can be stored continuously, and so on. Once the computer device is run as a test, the program execution status at multiple locations and the recording capacity at the problem location are large. It is an object of the present invention to provide an in-circuit emulator device that can solve the above problems by variably designing the height.

[0004]

In order to solve the above problems, according to the present invention, a computer device for executing / analyzing the execution status of a program, and an in-circuit emulator device for executing / analyzing the execution status of the program of the computer device are provided. A record storage memory size state counter per time of the trace storage memory for determining the size of the storage capacity of the trace storage memory installed in the in-circuit emulator device at one time, and the number of divisions of the trace storage memory. Division status code for determining, frame number status code for determining the size of the number of frames, address counter for controlling (determining) the address address of the trace storage memory, and number of frames to be stored after the end transfer Delay counter to control (determine) and start recording storage of trace storage memory The above problem is achieved by including an event circuit block for detecting such as the above and its peripheral circuit, and enabling the operator to record and store the (desired) trace result by the operation of the event circuit block and the delay counter. There is a solution.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a trace / trace showing an embodiment of the present invention.
It is a block diagram which shows the function of an event part. FIG. 2 is a block diagram showing a main circuit of a trace / event unit showing an embodiment of the present invention. Please note that the connections in this figure show only the main connections, so some parts may not necessarily match in detail. FIG. 3 is a block diagram showing an event circuit showing an embodiment of the present invention. FIG. 4 is a circuit block diagram showing a part of the address counter / delay counter portion of the embodiment of the present invention.
FIG. 5 is a chart showing the operation statuses of the address counter and the delay counter from event detection. FIG. 6 is a block diagram showing the main functions of both devices in a state where an in-circuit emulator device and a computer device are connected via a conventional probe I / F block. Table 1 is a table showing the states of the state codes that determine the frame size of the trace storage memory. Table 2 is a table showing the state of the state code that determines the number of frame divisions of the frame of the trace storage memory. Table 3 is a table showing the relationship between the size of the number of frames in the trace storage memory and the status code that determines the number of frame divisions to be recorded once.

In FIG. 6, the CPU 7 of the computer device
The record storage of the trace storage memory 15 for recording the execution status of the program executed by 0 is generally processed in the following procedure. That is, the signal of the program being executed (processed) by the CPU 70 of the computer device is transmitted to the sampling bus 89 via the ICE bus 82 and the sampling / decoding circuit 85. The "trace start address data or condition" such as "where to start storing the trace result" or "trace start condition" of the program input by the operator from the host computer device 94 is the host computer interface (I / F) 93. , Is stored in the event circuit block 14 in advance via the main CPU 90 and the mother bus 88. On the other hand, the trace controller 103 monitors the address of the program being executed by the CPU 70 of the computer device, and the event circuit block 1
C based on the trace start address information recorded in 4
The program execution status of the CPU 70 of the computer device of the PU bus 82 is gated (passed) and sent to the trace storage memory 15 together with the actual processing time signal (time measure signal) for recording and other signals to be recorded and stored. The recording allowable range (the number of frame ranges) of the memory 15 or the number of designated recording frames or the number of frames until interrupted by a command such as interrupt is the trace storage memory 1
5 is recorded and stored.

On the other hand, the program execution result of the CPU 70 of the computer device recorded and stored as described above is transmitted and displayed to the host computer device 94 from the trace storage memory 14 via the trace controller 103 based on an instruction from the host computer device 94. By checking / confirming the display result, the operator solves the difference / problem between the execution result of the program executed by the CPU 70 of the computer device and the designed program, thereby executing / analyzing the program of the computer device. (Debugging) is performed. The above is the outline of the operation of the conventional in-circuit emulator device. In the conventional operation, "from what address" of the execution of the program to be recorded is executed.
Or, "from what address to how many lines (frames)", it was possible to record only one place from a certain specified address. The reason is that the recording address division management method of the memory to be stored in the trace storage memory, the multiple recording management method of the event circuit block that executes the instruction to store the trace address, and the software / hardware problem corresponding to the above. There was not realized. However, as the computer device technology has advanced, the programming technique of the computer device and the usage method of the in-circuit emulator device have been diversified, and it is required to record and store a plurality of program problem points by executing the program of the computer device once. Has been done. The present invention has been made to meet the above demands.

An embodiment of the present invention will be described with reference to FIG. First, each block will be described. The trace storage memory 15 is a main memory for storing the data of the execution status of the program in which the CPU 70 of the target computer device operates, and the storage item for storing the data is ( As an example, 256 bits are formed per frame. Further, the main data recording area of the above (C) is composed of 256 bits up to the following, and the bit arrangement is as follows. Symbol Description recording bits located SA: Address Data 0 31 Number SD: main data 32 63〃 SC: control signal 64 95〃 SB: other sample data area 96 127〃 MEAS: measured timing signal (major Signal) 128-143 〃 TAG: Status signal 144-159 〃 EMEA: Extended measurement time signal 160-175 〃 ETAG: Extended status signal 176-191 〃 (spare): – 192-255 〃

When the trace storage memory 15 is to be divided and recorded, the following two conditions can be considered. (A) The maximum number of recordable frames in the trace storage memory is 128K frames as described above (a recording frame is approximately one line of a program of a computer device that has been created, but actually it is one line of execution of the CPU 70. If the number of frames is 2-4 / 5 lines even if one line in the above), then one line of the execution status of the program is considered as one frame, and as a divided recording method, half of that is used. A method of dividing into a multiple (multiplier) of 1/4, ... (B) When storing the trace result of a program,
There may be a case where it is desired to change the number of frames to be recorded according to the content of a desired analysis program, such as 4K frames at one time, 8K frames at another time, or 32K or 128K frames at another time. Therefore, in the present invention, the size of the frame that can be recorded by executing the program once is 4K, 8K, 32K, 1 as shown in Table 1.
It is possible to select from 4 types of 28K. Therefore, since the status code representing these is also 4 conditions, it can be configured with 2 bits and can be represented by 0-0-1 (when the number of divisions is 4 or more, the number of bits representing this status code also changes accordingly. Therefore, it goes without saying that it will be increased to 3 (electrically difficult) bits (up to 8) -4 bits (up to 16)). Next, the number of frame divisions is 1 as shown in Table 2.
(No division), 4 divisions (1/4), 32 divisions (1/3)
2), if it is divided into 128 (1/128) divisions, since it is divided into 4 states, it can be represented by 2 bits as described above, and therefore the state code can also be represented by 0-0-1-1 ( Needless to say, if the number of divisions is four or more, as in Table 1, the number of bits representing this status code must be increased accordingly to 3 bits to 4 bits).

As described above, when determining the number of divisions, it is assumed that the size of the number of frames to be divided and the status code are set as follows. That is, when the maximum number of frames is 128K frames and the number of frame divisions is 4, Further, in the present invention, an extended bank address (hereinafter referred to as "EBA address") is added to manage the address of the 128K frame trace storage memory. Since the EBA address consists of 4 bits, the decimal number is 0-15, so the 128K frame trace storage memory 15 is divided by 16 to configure 8K frames per 1 EBA address, and the trace storage memory 15 Decided to manage. That is, EBA address (binary number) : trace storage memory address (decimal number) 0000 (decimal number 0): 8K (001-008K frame) 0001 (〃 1): 8K (009-016K 〃) 0010 (〃 2): 8K (017-024K〃) ・ ・ ・ ・ ・ ・ ・ 1111 (〃15) ： 8K (121-128K〃)

Therefore, the total capacity of the trace storage memory 15 is 1
32K obtained by dividing 28K by 4 is 32K / 8K = 4, that is, each 32K frame is recorded at addresses 0-3 (decimal number) of the EBA address. Therefore, the relationship between the status counter and the EBA address is Each EBA address (actually, four digits in binary number) is added. Next, the memory arrangement of the address counter 21 is address: 01-12 ... Address code 18
16 bits below the bit are allocated EBA address: 13-16 ... 4 bits of extended address code (EBA address) are the address and is the extended address (EBA address).

From the above, the present invention proposes a method in which both the size of the frame to be used and the number of divisions are taken into consideration. When the size of the storage area is 128K frames at maximum, the number of divisions is 1, 4 , 16 and 64 can be set in 10 ways as shown in Table 3. That is, Table 3
In the case of the present embodiment, when the size of the storage area of the trace storage memory 15 is 4K frames at the maximum in (a), the size of each divided area becomes 1K frames and 2K or less. Since it cannot be divided, the maximum size of one frame is 4K. Also, (d)
Since the maximum is 128K frames, the total capacity is 4
This means that when divided into pieces, 128K / 4 = 32K frames can be divided and recorded into 4 pieces. Hereinafter, the operation of each block will be described assuming that 128 K frames are divided into 32 K frames per 4 divisions as described above. Now, the maximum size of a frame input by the operator from the host computer is 128K.
And the number of frame divisions is 4 = 1 in Table 1
28K [1,1], status code [0,1] of four divisions in (B) of Table 2, (hereinafter: when simply referred to as “status code”,
Table 1 ..., Table 2 (A) (B) ..., Table 3
(A) (b) ... Recording start address = X1, X2
... means the generic name of etc.) is a trace MO
It is input and held in the address counter 21, the sequence RAM block 29, and the like via the DE block 13.

Next, when the computer device and the in-circuit emulator device start operating, a start signal (TON) for the entire device is issued, and the divided frame of the address counter 21 is 32K / 1 (trace divided into 32K by 4). The address counter (in the first frame of the storage memory) starts counting. This address counter 21 counts from 0 (decimal) to (32K) 32767 (decimal) because the number of frames is specified as 32K, but after 32767, it returns to 0 and counts up again in sequence. And trace storage memory 1
It becomes the trace storage address of 5. Therefore, it is sequentially recorded in the trace storage memory 15, but when the counter returns to 0, the address of the trace storage memory 15 also returns to 0, and the recorded data is overwritten (obviously, it is overwritten). If the previous record does not remain). If the previous status code is 16 divisions and 8K frames is specified, it is 0.
It counts up from 0121 and then returns to 0 at 8121. When divided into 1 (not divided) with 128K frames, 0-131071 (128 × 1024-1)
And then the next returns to 0 as before (these numbers are written in decimal for convenience, but they are actually numbers in hexadecimal).

Now, when the program of the computer device reaches the first address X1 to be recorded, the event comparator 27 compares the bus address in the trace input from the sampling bus 89 and the previously stored value. After comparison, a signal indicating that recording should be started is sent to the event selector 28, and in this case, the event selector 28 sends the signal to the sequence RAM 29. When the above signal is input, the sequence RAM 29 sends a recording start signal ACEN to the address counter 21, and the counter of the address counter 22 starts counting up. The delay counter 22 receives the status code signal of 32K, which is the number of counts of the previous four frame divisions, and sets the count-up limit setting (setting) of the counter in the delay counter 22 to 32K (actually 128K-
[Minus] 32K = 96K 96000 (decimal / actually hexadecimal) is set, and when the count start signal (DCEN) of the delay counter 22 is received, the count is incremented upward from 96000.
000 (decimal / actually hexadecimal), 96000, 9
6001, 96002, 96003 ... 128K
128000 (actually, in hexadecimal, "FF ... F
F ”), a count full signal (DCF) is transmitted to the address counter 21 and the sequence RAM 29. The count-up setting of the delay counter 22 is set to 00000 when the counter is divided into 1 in 128K frames.
128K-4K when 8K ÷ 32 division = 4K frame
= 124K, which is a numerical value of 124K, is set (setting), and all 128000 (hexadecimal "FF ... F
The method is such that the count ends when it becomes "F").

The address counter 21 receiving the count full signal (DCF) from the delay counter 22 is
Stop counting up the address counter. Therefore, the count-up of the address counter is rotating from the count start signal until the count full (DCF) signal is received, during which the trace result of the program is actually recorded and stored in the trace storage memory 15 and left. Will be there. The chart of these operations is shown in FIG.
When the event signal (recording start signal: corresponding to event-event in FIG. 5) is input, the delay counter 22 starts counting, counts up to count full, and when the count full (DCF) is reached, The second address counter which is to be recorded is moved to the divided second address counter 22 and the counter is initialized to be in a standby state for the next event signal. Hereinafter, this state continues for the number of divisions (four divisions in the case of the present description). Since the maximum number of recording frames of the trace storage memory 15 is 128K frames, the address is managed by adding 4 bits of the extended address bus (EBA address) in this embodiment. That is, the above-mentioned address code: 18 bits Extended address code (EBA address): 4 bits Data recording area: 256 bits 4 bits of the extended address code (EBA address) is 16 (decimal number),
Addresses are assigned every 128K / 16 = 8K.

The trace MODE block 13 is a block for relaying / storing the input information from the operator input from the host computer device 94 via the mother bus 82, and the division status code (DVTRC) and the size of the frame. .. are sent to the address counter 21, the sequence RAM 29 and the like, the two signals of the status code (TRCMEMO), X1 address, X2 address, ... The sequence RAM 29 is composed of a programmable RAM memory / 16 bits and controls the entire tracer board section shown in FIG. First, the sequence RAM 29 receives the following signals. MA1-23: Main address signal (consisting of 24 bits) MD0-15: Main data signal (consisting of 16 bits) LSTDV: Count signal from the address counter 21 repeatedly records one of the divisions of the trace storage memory 15 (overlap) Write) or jump to the next divided frame (1 bit) DCF: Count full signal (1 bit) from delay counter 22 EV: Trace from event selector 28 to sequence RAM 29 Storage start X1 Event information signal (8)
Bit) ECF: Carry output signal from event counter 30 Count-up signal when tracing is desired to be interrupted at an arbitrary position Next, the sequence RAM 29 sends the following signals to each block for operation / control of the tracer board section. Output to. ACEN: Address counter (AC) count start instruction signal DCEN: Delay counter 22 count start instruction signal The delay counter 22 starts counting when this signal Hi is reached by the form signal. BRK: Event form count, which is a signal for interrupting / not interrupting the operation of the CPU 70 depending on the emulation form. ECEN: Event form counter. Counts the number of events DCREN: When the trace storage memory 15 is divided, a signal indicating whether to go to the next part or repeat.

The address counter 21 is a counter for setting the address of the trace storage memory 15 in order to store various data in the trace storage memory 15, and has two status signals (DVTRC, TRCME) input by the operator.
MO) and an address to be stored in the trace storage memory 15 based on the EBA address, and has a memory capacity as follows. Address counter: Counter for setting the address of the trace storage memory. It consists of 13 bits of 0-12. EBA address counter: 1 for the address counter.
Counter composed of 4 bits managed in blocks (8K frame units) ACR08: Counter memory (composed of 1 bit) that holds the signal when the address counter reaches 8K ACR04: The signal when the address counter reaches 4K Counter memory (composed of 1 bit) DCF: counter memory (composed of 1 bit) that holds a delay counter full instruction signal, which will be described later Reserve: address counter 32 bits remaining 12 bits

The delay counter 22 is a counter for setting (counting) the number of frames to be stored in the trace storage memory 15 as described above, and has two status signals (DVTRC, TRCME) from the trace MODE block 13.
Based on MO), the number of storage frames, that is, 128K−32K = 9 in the case of one storage block 32K in this embodiment.
6K (expressed in decimal notation for easy understanding)
(Actually configured by hexadecimal number) When the counter is initialized to 96000 and the count start signal (DCEN) arrives from the sequence RAM, 960
01, 96002, 96003, ... Counted up to 128000 (actually, in hexadecimal, "FF ... F
When it becomes "F"), a count full signal (DCF) is output to the address counter 21 and the sequence RAM 25. (For reference: When the maximum number of frame divisions in Table 3 is 64, 128 ÷ 64 = 2K, and one storage frame is 2
In this case, 128K-2K = 126K, so the initial value is set to 126000, and the count is sequentially incremented to 128000 [actually, in hexadecimal, "FF ... F
F ”], the count full signal (DCF)
Will be emitted).

The trace CPU connector 26 inputs signals required for recording in the trace storage memory 15 from the sampling bus 82 = computer device CPU bus, and from the trace MODE block 13 and the sequential RAM.
From the block 29, the address count signal from the address counter, the signal from the delay counter, and the main address and main data signals from the CPU bus are received.
The main address / main data signal to be stored in the trace storage memory is separately generated into SA, SB, SC and SD, and the signal is transmitted to the event comparator 27. The event comparator 27 is a trace CPU connector 26
Input SA signal, SB signal, SC signal, SD signal from the operator and start / not start the trace input by the operator X1
The address and the like of the address X4 are compared, and a signal is sent to the trace storage memory 15 via the data transmission path 34. At the same time, when the address coincides with the address X1, the signal is sent to CA, CB, CC, CD. The data indicating that is transmitted and encoded as the signal of (1) to the event selector 28 of the next stage and transferred. Further, the event selector 28 uses the signals (CA, CB, CC, C from the event comparator).
D) is detected, and a signal indicating that the trace should start is transmitted to the sequence RAM 29 as a signal for transmitting a trace start signal and as a signal for recording and storing in the trace storing memory 15. When the trace is interrupted / not suspended for some reason, the event counter 30 starts counting up based on the output signal to the sequence RAM 29, that is, the ECEN signal, and becomes "FF ... FF" of count full. When the ECN signal is input to the sequence RAM 29, the sequence RAM 29 sends a break signal (BRK) for interrupting the trace to each required block.

The outline of the operation of each functional block has been described above. Next, an example of storage in the trace storage memory 15 will be described. Now, in order to explain the operation example, it is assumed that the operator sets the conditions as follows, that is, the maximum number of frames to be recorded is 128K frames ...
... (from Table 1) Status signal 1-1 Set the number of divisions of the trace storage memory to 4 (DVTR
C) ... (from Table 2) Status signal 0-1 From the above, the storage frame capacity per trace storage memory is from Table 3 to 32K frames (TRCME).
MO) Trace start address for each of the four divided states
... It is assumed that the addresses X1, X2, X3, and X4 are set.

From the above conditions, the operator (a) first inputs the above conditions from the host computer device 94 connected to the in-circuit emulator device to the trace MODE block 13 via the mother bus 88. (B) When a trace start signal (TON) is input from the host computer device 94, C of the computer device is input.
The PU 70 starts executing the program. (C) When the trace start signal (TON) from the host computer device 94 is also input to the trace MODE block 13, the trace start signal is sent to the sequence RAM 2
9, the sequence RAM 29 transmits the trace start signal (TON) to each related block, and the address counter of the address counter 21 starts counting up based on the trace start signal.
When the address counter reaches a predetermined number (in this case, since one storage frame is 32K, 0000 to 32000), the counter returns to 00000, and 00001, 0 again.
0002 and count-up are repeated any number of times (until a count-up stop signal described later arrives) (see FIG. 4). Therefore, since the address signal is input to the trace storage memory 15 to store the trace, the storage is executed, but since the counter returns to the same address when the counter makes one cycle, the signal input later is repeatedly stored. Will be done.

(D) On the other hand, the trace CPU connector 26 (see FIG. 3 below) receives the trace start signal (TON) from the sequence RAM 29, and receives the trace data from the CPU bus as SA (address) and SB (other data). , S
The signals are separated into C (control) and SD (Data) signals, gated (passed), and sent to the event comparator 27. (E) The event comparator 27 receives the address signal (SA) input from the trace CPU connector 26,
First, the address "X1" that is inputted by the operator and instructed to start the storage is compared, and if the addresses match, the storage is started. Therefore, a signal indicating the match is sent to the sequence RAM 29 via the event selector 28. . (F) The event selector 28 converts the signal into an event signal (EV), sends it to the sequence RAM 29, and sends it to the trace storage memory 15 for recording. (G) When the trace start signal (EV) is input to the sequence RAM 29 (see FIG. 4 below), the delay counter 22 starts counting up (DCE).
N) is issued to the delay counter 22.

(H) When the DCEN signal arrives, the counter of the delay counter 22 starts counting up. The delay counter 22 has the first counter as described above.
In the case of 32K which is the number of recording frames in the recording block,
The initial setting value of the counter is 128-32 = 96K: 960
Since it is set to 00, the counters are 96001, 9
Counted up to 6002 ... 12800
When it reaches 0 (“FF ... FF” in hexadecimal number), a count full signal (DCF) is output to the address counter 21 and the sequence RAM 29. (I) On the other hand, when the count full signal (DCF) is input, the address counter 21 stops counting up the address counter. That is, since the counter of the address counter of the trace storage memory 15 is stopped, the past (last) 32K which has been incremented
Frames will be stored. Therefore, the count-up of 32K frames set by the delay counter is left and stored in the trace storage memory 15. (J) When the count of the first block = storing in the trace storage memory 15 is completed, the address counter 21 changes from the address of the first block to the second block based on the count full signal (DCF) of the delay counter 22. To count up the two status code counters, and the upper digit of the address counter is increased to prepare for the address cant up in the next second block (event at address X2). (K) When it is desired to make one of the divided frames which is one of the present invention continuous, for example, two 32K continuous recording frames, the two status codes and the initial setting value of the delay counter 22 are set. It is easy to achieve the purpose by changing the number and setting the upper digit of the address counter.

[0024]

As described above, the in-circuit emulator device using the present invention records the execution status of the program executed by the CPU 70 of the computer device in the trace storage memory 15 inside the in-circuit emulator device. Since the area to be stored can be divided and recorded, the execution status of a plurality of places (maximum 64 places in the example of the present invention) can be recorded and stored by executing the program of the computer once. Recording storage area (maximum of 64 locations in the present invention)
One or two or more can be arbitrarily used continuously at a plurality of locations, so that the program of the computer device can be debugged quickly, and the time required for debugging can be greatly saved.

[Brief description of drawings]

FIG. 1 is a diagram showing a functional block of a trace / event unit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a trace / event section main circuit block showing an embodiment of the present invention.

FIG. 3 is a diagram showing an event circuit block showing an embodiment of the present invention.

FIG. 4 is a circuit block diagram showing an address counter / delay counter showing a part of an embodiment of the present invention.

FIG. 5 is a chart showing the operation statuses of an address counter and a delay counter from event detection.

FIG. 6 is a main block diagram of both functions in a state where the in-circuit emulator device and the computer device are connected via a probe I / F block.

[Table 1] 6 is a table showing the states of state codes that determine the frame size of the trace storage memory.

[Table 2] 9 is a table showing the states of state codes that determine the number of frame divisions of a frame in the trace storage memory.

[Table 3] 9 is a table showing the relationship between the size of the number of frames in the trace storage memory and a status code that determines the number of frame divisions to be recorded once.

[Explanation of symbols]

13 Trace MODE Block 15 Trace Storage Memory 21 Address Counter 22 Delay Counter 23 Clock Generator 24 Memory Counter 26 Trace CPU Connector 27 Event Comparator 28 Event Selector 29 Sequence RAM 70 Target Computer Device 82 Computer CPU Bus 88 In Main CPU of circuit emulator device
Bus 90 Main CP in in-circuit emulator device
U 93 Host computer device

Claims (4)

[Claims] 1. A central processing control unit (C) of a computer device.
In the in-circuit emulator device for analyzing the execution status of the (PU), the trace storage memory in the in-circuit emulator device and the peripheral control circuit for controlling the trace storage memory are provided. In-circuit emulator device characterized in that the recording method of the memory is divided into 1 or 1/2 (1/2) or 1 / X (1 / X: X is a multiplier of 2) . 2. A central processing controller (C) of a computer device.
In the in-circuit emulator device for analyzing the execution status of the (PU), the trace storage memory in the in-circuit emulator device and the peripheral control circuit for controlling the trace storage memory are provided. 1 or half of the memory (1/2), or a power of 2 (1 /
X: X is a power of 2), and one or two or more of the divided areas are arbitrarily selected as one recording area, and are stored in the arbitrarily selected recording area. Circuit emulator device. 3. A central processing control unit (C) of a computer device.
In the in-circuit emulator device for analyzing the execution status of the (PU), the trace storage memory inside the in-circuit emulator device and its peripheral control circuit for controlling the trace storage memory are configured to control the trace storage memory. A peripheral control circuit, and the trace storage memory of the in-circuit emulator device is 1 or 1/2 (1/2) or a multiplier of 2 (1 / X: X is a multiplier of 2). The divided trace storage memory is provided with a bank address for additional address management, and the bank address is used as an address for dividing the trace storage memory into blocks, and the number of recording frames of the divided memory. An in-circuit emulator device characterized by managing 4. A central processing control unit (C) of a computer system.
In the in-circuit emulator device for analyzing the execution status of the (PU), the trace storage memory in the in-circuit emulator device and the peripheral control circuit for controlling the trace storage memory are provided. The recording method of the memory is divided into 1 or 1/2 (1/2) or 1 / X (1 / X: X is a multiplier of 2) division recording, and division recording is performed. An in-circuit emulator device characterized by managing the address and the number of recording frames so that the address / recording frame number can be recorded by a state counter and a delay counter, and recording and storing them in a divided trace storage memory. 4. A central processing control unit (C) of a computer system.
In the in-circuit emulator device for analyzing the execution status of the (PU), the trace storage memory in the in-circuit emulator device and the peripheral control circuit for controlling the trace storage memory are provided. The recording method of the memory is dividedly recorded into 1 or 1/2 (1/2) or 1 / X (where X is a multiplier of 2), and one of the divided and recorded data is recorded. The in-circuit emulator device is characterized in that the number of frames stored in the storage area depends on the number of counts set under the delay counter and is stored in the trace storage memory.