JPH097375A - Sense amplifier - Google Patents

Abstract

PURPOSE: To let a pair of bit lines hold respective potentials independently by providing the pair of bit lines with circuits for holding the potentials respectively. CONSTITUTION: When a current I flows to a memory cell, a current flowing to a data line, the inverse of DL is decreased. When the current to the line DL is decreased, a potential of the line, the inverse of DL is lowered. A level of the line, the inverse of DL is input to a gate of a transistor T5 through an inverter 1A, and a current of the transistor T5 is consequently decreased. After a memory is selected, the current flowing in the transistor T5 is reduced by I to i0I, whereby the current is detected and a potential of the inverse of OUT is reduced. Bit lines can accordingly hold potentials independently of each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sense amplifier of a semiconductor memory device, and more particularly to a current detection type sense amplifier.

[0002]

2. Description of the Related Art Conventionally, as a current detection type sense amplifier of this type, IEEE JOURNAL OF SOLID STATE CIRCUIT VOL2
6, No4 APRIL 1991 The ones shown on pages 525-535 have been proposed. In the current detection type sense amplifier disclosed in this document, transistors whose gates are connected to the other bit line are connected to the transistors of the column switch section. With such a configuration, the potential of the bit line pair is always kept constant. Therefore, the same amount of current is supplied to each bit line from the power supplies connected to the bit line pair. In such a sense amplifier, when a memory cell is selected and a current flows from one bit line to the memory cell, the current flowing from the bit line to the data line is reduced by the current flowing in the memory cell. Also, the current flowing from the other bit line to the data line does not change. Therefore, a current difference occurs in each data line by the amount of the current flowing in the memory cell. At this time, a current flows through the transistors connected to the respective data lines, and is detected as a potential difference between the data lines.

[0003]

However, in the conventional method, the column switch transistor 2 of the column switch is arranged at the same pitch as the memory cell in the column switch part where the bar YSEL enters.
Four transistors, including one, must be inserted, which significantly increases the chip area. In addition, since it is a method of detecting by the difference in current flowing between bit lines, there is a problem that it is easily affected by the imbalance of resistance between bit lines.

[0004]

In order to solve the above-mentioned problems, in the sense amplifier of the present invention, a bit line pair is held independently of each other's bit line, and the potential of the bit line is held and a memory cell is selected. A circuit that outputs a current reduced by the amount of current flowing through the memory cell is provided.

[0005]

By providing each bit line pair with a circuit for holding the potential of the bit line, each bit line independently holds the potential of the bit line when the memory cell is selected. Further, a high gain can be obtained without latching the output by the cross-coupled transistor and the load transistor added to the data line.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a circuit diagram showing an embodiment of the present invention, in which all the transistors are enhancement type MOS type transistors, and the one with the arrow pointing to the gate side represents the N type and the outside. Those pointing to represent the P type.

In FIG. 1, a pull-up transistor T1 having a gate connected to the bar BL is connected between the inverted bit line (hereinafter referred to as bar BL) and the power supply Vcc, and the bit line (hereinafter referred to as BL) and the power supply Vcc are connected to each other. A pull-up transistor T2 whose gate is connected to BL is connected between them. Further, memory cells are connected between the bit line pair BL and BL. A transistor T3 whose gate is connected to the column selection signal YSEL is connected between the bar BL and the inverted data line (hereinafter referred to as DL), and a gate is connected between the BL and the data line (hereinafter referred to as DL). The transistor T4 connected to YSEL is connected. The input of the inverter 1A is connected to the bar DL, and its output is connected to the gate of the transistor T5 connected between the bar DL and the bar OUT. The input of the inverter 2A is connected to DL,
Its output is a transistor T connected between DL and OUT.
Connected to the gate of 6. Transistors T7 and T8 are connected between the bar OUT and ground, and T is connected between OUT and ground.
9, T10 is connected. The gates of the transistors T7 and T9 are connected to OUT, and the gates of the transistors T8 and T10 are connected to OUT.

Next, the operation of the sense amplifier thus constructed will be described. When the column selection signal bar YSEL becomes "L" level, the transistors T3 and T4 are turned on, and the sense amplifier becomes operable. At this time, the current i flows from the load transistors T1 and T2 into the bars DL and DL through T3 and T4. Further, the current i flowing into the bars DL and DL flows into T7, T8, T9 and T10 through the transistors T5 and T6. Since the bars OUT and OUT operate close to the ground level, the transistors T5, T6, T7, T8, T9 and T10 operate in the saturation region.

When a memory cell is selected and a current I flows through the memory cell as shown in FIG. 1, the current flowing through the data line bar DL decreases. When the current flowing through the bar DL decreases, the potential of the bar DL decreases, but since the level of the bar DL is input to the gate of the transistor T5 through the inverter 1A, when the potential of the bar DL decreases, the transistor T5 decreases.
The potential on the gate of the transistor rises, reducing the current through transistor T5. That is, the feedback is applied by the transistor T5 so that the potential of the bar DL becomes the same as that before the memory cell is selected. Therefore, the level of the bar DL is the same before and after the memory cell is selected. bar
The fact that the level of DL is the same before and after the memory cell is selected means that the current flowing from the pull-up transistor T1 to the bar BL is always kept constant. That is, as the current flowing through the transistor T5, the current i flows before the memory cell is selected, and after the memory cell is selected, the current decreases by I to i-I. In this way, the change in the memory cell current appears at the bar OUT, and the current is detected. The memory cell current I thus detected appears as a decrease in the potential of the bar OUT when the current flowing through the load transistors T7 and T8 decreases from i to i−I by I. The transistors T7 and T8 are
Since it operates in the saturation region, even a slight decrease in the current flowing through the transistors T7 and T8 appears as a larger decrease in potential. Further, since the transistors T8 and T9 are subjected to the positive feedback by the cross couple, the potential of the bar OUT is further lowered. On the contrary, when a current flows to the right side of the memory cell, the same operation is performed. In this case, the current flowing through the transistors T6, T9, T10 decreases, and the potential of OUT decreases. The potential difference thus detected becomes an output to the next stage circuit.

[0010]

As described in detail above, the sense amplifier according to the present invention has a structure for detecting the current flowing through the bit line on one side. For this reason, it is difficult to be affected by the imbalance of the resistance between the bit line and the data line, so that it is possible to provide a sense amplifier in the peripheral circuit. As a result, only two transistors are required to be inserted in the column switch section at the same pitch as the memory cells, and the increase in chip area due to the sense amplifier is small. Further, since a cross-coupled transistor and a load transistor are added in parallel with the transistor, a high gain output can be obtained without latching the output.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a sense amplifier showing an embodiment of the present invention.

[Explanation of symbols]

 T1, T2: PMOS pull-up transistor T3, T4: PMOS 1A, 2A: Inverter T5, T6: PMOS T7, T10: NMOS load transistor T8, T9: NMOS cross-coupled transistor

Claims (4)

[Claims] 1. A first and second bit line, a first node, a power supply for applying a first potential to the first and second bit lines, and a portion between the first and second bit lines. A memory cell connected to the first bit line and a control circuit connected between the first bit line and the first node, wherein the memory cell is selected, and the memory cell is selected from the first bit line. When a current flows through the first bit line and the first bit line changes from the first potential to the second potential, the change is detected and the current value flowing to the first node is controlled. The control circuit for holding the potential of the first bit line substantially at the first potential; and amplifying a third potential generated at the first node by the current flowing to the first node. And an amplification circuit connected to the amplification circuit A sense amplifier having an output terminal for outputting the generated potential. 2. The sense amplifier according to claim 1, wherein the detection circuit is a circuit that changes a resistance value between the first bit line and the output. 3. The sensing circuit comprises a first node and a first node.
3. The sense amplifier according to claim 2, wherein the transistor is connected to the bit line of, and an inverted signal of the first bit line is connected to the gate of the transistor. 4. The first transistor, wherein the amplifier circuit is connected between the first node and a ground power supply, and the gate of which is connected to the second bit line, and the second bit line. And the ground power source,
The gate is configured by a second transistor connected to the first node, and a load transistor connected between the second bit line and the first node and a ground power source, respectively. The sense amplifier according to claim 3, wherein