JPH0974207A - Method for manufacturing thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a thin film transistor without using a high temperature heat treatment process, and to stabilize and make uniform the threshold voltage of the thin film transistor. SOLUTION: A gate electrode 41 and a gate insulating film 42 are formed on a substrate 50, a heaving doped impurity polycrystalline silicon thin film 10 is formed in a manner that it is insulated to the gate electrode 41. Ions, with which the impurity element in silicon is inactivated, are implanted on a part of the section opposing to the gate electrode 41 of the polycrystalline silicon thin film 10. As a result, the carrier concentration of the above-mentioned part becomes low, a channel region 1 is formed, and the remaining part becomes a source and drain region 2. Accordingly, a thin film transistor, on which the carrier concentration of the channel region 1 is controlled in a highly precise manner, is manufactured without performing a high temperature heat treatment process.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used as, for example, a switching element of an active matrix type display device, and more specifically, a threshold voltage of each thin film transistor can be stably and uniformly obtained in multiple gradations. The present invention relates to a method of manufacturing a thin film transistor, which is capable of manufacturing an operable element in a simple process without causing thermal damage to a substrate.

[0002]

2. Description of the Related Art Conventionally, in an active matrix type display device using a display material such as liquid crystal, a thin film transistor is used as a switching element of each pixel. Such a thin film transistor is described in, for example, JP-A-63-224258.

A conventional method of manufacturing a thin film transistor is to manufacture the thin film transistor shown in FIG. 8 according to a flow generally shown in FIG. That is, first, the gate electrode 51 having a predetermined shape is formed on the transparent glass substrate 50 (a). The gate electrode 51 is a metal such as molybdenum (Mo) or polycrystalline silicon (Si). Then, CVD is performed on the glass substrate 50 including the gate electrode 51.
A gate insulating film 52 is formed by (chemical vapor deposition) (b), and a channel layer 53 is formed on the gate electrode 51 and the gate insulating film 52 (c). This channel layer 53
Is amorphous silicon or polycrystalline silicon doped with a low concentration of impurities. The impurity concentration of the channel layer 53 determines the threshold voltage V _th for operating the thin film transistor.

Next, a silicon nitride (SiN _x ) channel stopper layer 54 is formed on the channel layer 53 by plasma C.
Formed by VD (d). This channel stopper layer 5
Reference numeral 4 serves as an etching stopper in the subsequent source / drain processing. Then, the channel layer 53 is etched into a predetermined shape (e), a source / drain layer 55 having a predetermined shape is formed thereon (f), and a source / drain electrode 56 having a predetermined shape is further formed thereon. (G). When the source / drain layer 55 and the source / drain electrode 56 are processed into a predetermined shape, the channel stopper layer 54 prevents the channel layer 53 from being etched. Source / drain layer 55
Is amorphous silicon or polycrystalline silicon doped with a high concentration of impurities (having the same pn polarity as the impurities of the channel layer 53). The source / drain electrodes 56 are metals such as aluminum (Al).
Finally, when a silicon nitride protective film (not shown) is applied by plasma CVD (h), a thin film transistor element is completed.

In the thin film transistor thus manufactured, since the channel layer 53 has a low impurity concentration and thus has a high resistance, the conduction between the source layer 55 and the drain layer 55 is normally off. However, when the voltage V _g is applied to the gate electrode 51, the electric field effect increases the carrier concentration in the channel layer 53, so that the resistance value decreases, and finally the conduction between the source layer 55 and the drain layer 55 is turned on. The gate voltage V _{g at} which this ON inversion occurs is the threshold voltage V _th .

In the above manufacturing method, a transparent glass substrate 50 is used as a substrate for use in a display device. Since the glass substrate 50 is weak against high temperature, a high temperature heat treatment such as ion implantation + thermal diffusion is performed. Instead, the thin film transistor is manufactured. Therefore, in the formation of the channel layer 53 (c) and the formation of the source / drain layer 55 (f), a non-doped film containing no impurities is formed and then impurities are introduced and diffused into the non-doped film from the beginning. It was decided to form a doped film containing impurities.

[0007]

However, the thin film transistor manufactured by the above-mentioned conventional method has a problem that the threshold voltage V _th has a large variation. The cause is the variation in the impurity concentration of the channel layer 53.

In order to clarify the reason, first, the relationship between the impurity concentration of the channel layer 53 and the threshold voltage V _th will be described. In this type of thin film transistor, the carrier concentration in the channel layer 53 is changed by the electric field effect of the gate voltage V _g .
When the source layer 55 and the drain layer 55 are electrically connected to each other, the ON operation is performed by increasing the voltage to a value sufficient for electrical conduction. The gate voltage V _g required for this is the threshold voltage V _th . Since the impurity concentration of the channel layer 53 determines the original value of the carrier concentration, if the impurity concentration changes, the threshold voltage V _th
Will also fluctuate. For example, when the impurity concentration is higher than the normal value, the original carrier concentration of the channel layer 53 is high, so that the thin film transistor is turned on at a lower gate voltage V _g . That is, the threshold voltage V _th becomes lower than the normal value. On the other hand, when the impurity concentration is lower than the normal value, the threshold voltage V _th becomes higher than the normal value. Therefore, in order to obtain the accurate threshold voltage V _th , it is necessary to make the impurity concentration of the channel layer 53 uniform.

In the above manufacturing method, the channel layer 53 is formed by forming a doped film containing impurities. However, in the region where the impurity concentration is low, it is difficult to control the concentration, so that the variation becomes large. In this respect, the ion implantation differs from the fact that the number of ions to be implanted can be controlled with high accuracy. And, this concentration variation exists not only between the substrates but also between the thin film transistors on one substrate. For this reason, the threshold voltage V _th of each thin film transistor varies on one substrate. As a result, the number of display gray scales when used as a display device is limited to about 64 and cannot be further increased.

The present invention has been made in order to solve the above problems of the prior art, and an object of the present invention is to provide a thin film transistor in which the threshold voltage V _{th of the} thin film transistor is stable and uniform with good reproducibility. It is to provide a manufacturing method without using a high temperature heat treatment process.

[0011]

In order to achieve the above-mentioned object, a method of manufacturing a thin film transistor according to the present invention comprises a step of forming a gate electrode and a gate insulating film, and a step of forming a semiconductor thin film having a high impurity concentration in the gate. A film forming step of forming an insulating film from an electrode, and a channel forming step of ion-implanting a part of a portion of the semiconductor thin film facing the gate electrode to form a channel region and the rest as a source region and a drain region. And the ions implanted by the ion implantation are ions that inactivate the impurity element in the semiconductor thin film.

In this manufacturing method, after the gate electrode and the gate insulating film are formed in the gate structure forming step, a semiconductor thin film having a high impurity concentration is formed in the film forming step. This semiconductor thin film is formed with an impurity concentration having an appropriate resistance value as a source region and a drain region of a thin film transistor. This concentration is at a level that allows highly precise concentration control in the film forming apparatus, and therefore the precision of the impurity concentration of the semiconductor thin film is high. The semiconductor thin film is insulated from the gate electrode by the gate insulating film. Then, ion implantation is performed on a part of the semiconductor thin film in the channel forming step. This ion implantation is performed on a further part of the portion of the semiconductor thin film facing the gate electrode. Then, the ions implanted here are ions that inactivate the impurity element in the semiconductor thin film and prevent it from contributing to carrier addition. Therefore, in the portion where the ion implantation is performed, even if the impurity concentration is high, the carrier concentration is reduced and the resistance value is increased, and it becomes the channel region of the thin film transistor. The portions of the semiconductor thin film that have not been subjected to ion implantation become the source region and the drain region of the thin film transistor. In addition,
Since this ion implantation does not undergo a heat diffusion treatment after that, there is no risk of thermal damage.

The thin film transistor thus manufactured is
A channel region, which is a part of a semiconductor thin film having a high impurity concentration and has been implanted with ions for deactivating the impurity element,
A source region and a drain region which are the rest of the semiconductor thin film; a gate electrode facing the channel region and wider than that; and a gate insulating film insulating the channel region, the source region, and the drain region from the gate electrode. have.

In this thin film transistor, since the impurity element is inactivated in the channel region by ion implantation and the carrier concentration is lowered, the resistance value of this region is high. Therefore, in the normal state, the conduction between the source region and the drain region is turned off by this channel region. Then, when a voltage V _g is applied to the gate electrode, an electric field due to the voltage V _g acts on the entire channel region through the gate insulating film, and the electric field effect increases the carrier concentration of the channel region, so that the resistance of the channel region decreases. To do. Then, when the voltage V _g reaches the threshold voltage V _th , the conduction between the source region and the drain region is turned on.

Here, the gate voltage V _g required to turn on the thin film transistor, that is, the threshold voltage V _th depends on the carrier concentration in the channel region when the gate voltage V _g is zero. This carrier concentration is the concentration of an active impurity element in the channel region. This is the impurity concentration when a semiconductor thin film having a high impurity concentration is formed in the film formation process, and is deactivated by ion implantation in the channel formation process. It is the one after subtracting the amount. Further, the impurity concentration during film formation is at a level that allows highly accurate concentration control in the film forming apparatus, and since the number of implanted ions can be controlled with high accuracy in ion implantation,
The concentration of the active impurity element in the channel region can be controlled with high accuracy and has high reproducibility. Therefore, even if a large number of thin film transistors are formed on one substrate, the threshold voltage V _th of each thin film transistor is highly uniform.

Further, in this thin film transistor, since the channel region, the source region and the drain region are formed as a semiconductor thin film having a higher impurity concentration, the contact resistance between the channel region and the source and drain regions is very high. It can be made small and the channel length can be made small. Therefore, the on-resistance is small and high-speed operation is possible.

Hereinafter, preferred embodiments for achieving the above object more favorably will be described.

[Aspect 1] In the method of manufacturing a thin film transistor according to claim 1, ion implantation in the channel forming step is performed by patterning with a photoresist mask, and a source region and a source region formed in the semiconductor thin film in the channel forming step. A method of manufacturing a thin film transistor, comprising an electrode forming step of forming a source electrode and a drain electrode on a drain region.

[Aspect 2] In the method of manufacturing a thin film transistor according to claim 1, an electrode for forming a source electrode and a drain electrode on a portion to be a source region and a drain region of the semiconductor thin film formed in the film forming step. A method of manufacturing a thin film transistor, comprising a forming step, and performing ion implantation in the channel forming step using the source electrode and the drain electrode as a pattern mask.

In the manufacturing method of Mode 1 or Mode 2, since the source electrode and the drain electrode for the source region and the drain region are formed in the electrode forming step, the source region and the drain electrode form the source region and the drain region and the wiring. Ohmic contact is made. In particular, in the manufacturing method of aspect 2, since the source electrode and the drain electrode are used as the pattern mask at the time of ion implantation, it is not necessary to perform photolithography for only ion implantation,
The number of photos can be reduced.

[Aspect 3] In the method of manufacturing a thin film transistor of aspect 1 or aspect 2, the semiconductor thin film is formed on a portion of the semiconductor thin film formed in the film forming step to be a channel region or in the channel forming step. A method of manufacturing a thin film transistor, comprising: a stopper forming step of forming an etching stopper layer on the channel region formed in.

In this manufacturing method, the etching stopper layer formed in the stopper forming step is a portion to be the channel region of the semiconductor thin film or the channel region formed in the semiconductor thin film when the electrode layer is etched in the electrode forming step. This is to prevent it from being etched. Because under the condition of etching the electrode layer,
Since the semiconductor thin film is often etched,
This is because it is necessary to prevent this. Therefore, the timing of performing this stopper forming step may be before the electrode forming step, and may be before or after forming the channel region in the semiconductor thin film in the channel forming step.

[Aspect 4] A method of manufacturing a thin film transistor according to claim 1 or aspect 1 or aspect 2 or aspect 3,
The semiconductor thin film formed in the film forming step is an amorphous silicon thin film or a polycrystalline silicon thin film, and the ions implanted in the channel forming step are selected from the group consisting of Si, F (fluorine) and Ar (argon). A method for manufacturing a thin film transistor, wherein the thin film transistor is an ion of one or more elements.

According to this manufacturing method, an amorphous silicon thin film or a polycrystalline silicon thin film having a high impurity concentration can be formed by an ordinary film forming apparatus while controlling the impurity concentration with high accuracy. When Si, F, and Ar are ionized and injected into the amorphous silicon thin film or the polycrystalline silicon thin film, they have the effect of deactivating the impurity element, and are suitable for forming the channel region.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail with reference to the drawings. In the method of manufacturing a thin film transistor according to each embodiment described below, a large number of thin film transistors are manufactured in a matrix on a transparent glass substrate because the thin film transistor is used as a switching element of a liquid crystal display device. However, for convenience, only one thin film transistor is shown in the drawing.

First embodiment. This embodiment corresponds to claim 1, aspect 1, aspect 3 according to aspect 1, and aspect 4 according to aspect 1.

In this embodiment, basically, as shown in FIG. 3, a gate electrode is formed on a glass substrate (S1), a gate insulating film is formed (S2), and a polycrystalline silicon film is formed with a high impurity concentration. As a doped film (S3), and a part of this polycrystalline silicon film is ion-implanted to form a channel region, and the rest is not used as a source / drain region (S4), and a channel stopper film covering this channel region is formed. Is formed (S5), excess portions of the source / drain regions are removed (S6), and source / drain electrodes are formed (S5).
7) Finally, the whole is covered with a protective film (S8).
Hereinafter, a detailed description will be given with reference to FIGS. 1 and 2.

FIG. 1A is a sectional view showing a state in which a gate electrode 41, a gate insulating film 42, and a polycrystalline silicon film 10 having a high impurity concentration are formed on a glass substrate 50. Of these, the formation of the gate electrode 41 and the gate insulating film 42 is the gate structure forming step described in claim 1, and the formation of the polycrystalline silicon film 10 having a high impurity concentration is the film forming step described in claim 1.

First, the gate electrode 41 is formed of a metal such as molybdenum or polycrystalline silicon on the glass substrate 50 (S1 in FIG. 3). The gate electrode 41 is formed by forming a solid film of metal or polycrystalline silicon on the glass substrate 50 by sputtering or CVD and processing it into a predetermined shape by photolithography and etching. When polycrystalline silicon is used, impurities are contained to secure conductivity.

Next, a gate insulating film 42 is formed on the glass substrate 50 including the gate electrode 41 (S in FIG. 3).
2). The material of the gate insulating film 42 is not particularly limited as long as it has excellent insulating properties, but silicon oxide (SiO _x )
Alternatively, it is general to form silicon nitride or the like by CVD. Although the gate insulating film 42 exists on the entire surface of the glass substrate 50 within the range shown in FIG. 1A, it is not necessary for a place other than the thin film transistor, for example, a place where a liquid crystal element is formed, and therefore, the gate insulating film 42 is not formed by photolithography and etching. Remove the necessary parts.

Then, a polycrystalline silicon film 10 having a high impurity concentration is formed on the gate insulating film 42 by CVD as a solid film (S3 in FIG. 3). This polycrystalline silicon film 10
Serves as a channel region and a source / drain region in the thin film transistor, and is insulated from the gate electrode 41 by the gate insulating film 42. Then, the polycrystalline silicon film 10 is made to contain an impurity of a predetermined concentration at the time of film formation. The impurities are phosphorus (P),
It is an element that imparts conductivity to silicon, such as boron (B). The concentration of this impurity is
The concentration is high enough to obtain appropriate conductivity for the drain region. Specifically, as a CVD atmosphere gas, an impurity supply gas such as phosphine (PH ₃ ) or diborane (B ₂ H ₆ ) is mixed at a predetermined ratio to form the polycrystalline silicon film 10 having a high impurity concentration. To film. Here, the reason for including this impurity element at the time of film formation is that since the substrate is the glass substrate 50 which is weak against high temperature, it cannot be contained by solid phase diffusion or the like after film formation. Although the polycrystalline silicon film 10 is used here, an amorphous silicon film may be used as long as it has a high impurity concentration.

FIG. 1 (a) shows a state in which the process up to S3 is performed. The subsequent FIG. 1B shows the ion implantation in the channel forming step.

In order to perform this ion implantation, first, the resist mask 61 is patterned by photolithography. The resist mask 61 covers the portions of the polycrystalline silicon film 10 that are to be the source / drain regions, and the portions that are to be the channel regions are open. This opening is located above the gate electrode 41 and is narrower than this. Then, ion implantation is performed with the resist mask 61 present (S4 in FIG. 3). The ions implanted here are S
An ion of any one of i, F, and Ar. These ions have a function of deactivating the impurity element contained in the polycrystalline silicon film 10 so that it does not contribute to carrier addition.

When this ion implantation is performed, the ions enter the portion of the polycrystalline silicon film 10 where the resist mask 61 is open, and the portion becomes the channel region 1. In this channel region 1, the impurity element is inactivated due to the implanted ions, the carrier concentration is reduced, and the conductivity is reduced. On the other hand, since the ions are shielded in the portion covered by the resist mask 61, the carrier concentration of the polycrystalline silicon film 10 is maintained at the high value at the time of film formation. This portion is used as a source / drain region. After the ion implantation is completed, the resist mask 61 is removed. Since thermal diffusion is not performed after this ion implantation, the glass substrate 50 is not thermally damaged.

Next, as shown in FIG. 1C, a silicon nitride channel stopper 43 is formed on the polycrystalline silicon film 10 by CVD (S5 in FIG. 3). The channel stopper 43 is an etching stopper for preventing the channel region 1 from being etched during the etching process of the source / drain electrodes, which will be described later, and is formed so as to cover the channel region 1 and slightly protrude to the outside thereof. To be done.
The formation of the channel stopper 43 is the stopper forming step according to the third aspect.

Subsequently, as shown in FIG. 2A, unnecessary portions of the polycrystalline silicon film 10 are removed by photolithography and etching. As a result, the source / drain region 2 is processed (S6 in FIG. 3). Note that FIG. 1 (c)
The formation of the channel stopper 43 and the processing of the source / drain region 2 may be interchanged.

Next, as shown in FIG.
A source / drain electrode 44 is formed of a metal such as aluminum on the drain region 2 (S7 in FIG. 3). The source / drain electrodes 44 are formed by sputtering or CV.
A solid film of the metal is formed by D, and this is processed by photolithography and etching.
During this etching process, the source / drain electrodes 44
Since the polycrystalline silicon film 10 is also etched under these etching conditions, the channel region 1 may be damaged, and a countermeasure is required to prevent this. Here, the channel stopper 43 prevents the channel region 1 from being protected. Plays a function. The source / drain electrode 44 thus formed covers the upper surface of the source / drain region 2 and makes ohmic contact with them. This source / drain electrode 44 is formed in the first aspect.
This is the electrode forming step.

Then, after forming the necessary wiring,
As shown in FIG. 3C, when a protective film 45 of silicon nitride or silicon oxide is formed by CVD and the whole is covered (S in FIG. 3).
8) The thin film transistor element is completed.

The thin film transistor thus manufactured is
S that is a part of the polycrystalline silicon film 10 having a high impurity concentration
A channel region 1 in which an impurity element is inactivated by ion implantation of any one of i, F, and Ar, a source / drain region 2 that is the remaining portion of the polycrystalline silicon film 10, and a channel region 1 A gate electrode 41 wider than the gate electrode 41, a gate insulating film 42 that insulates the gate electrode 41 from the channel region 1 and the source / drain region 2, and a source that makes ohmic contact with the source / drain region 2. It has a drain electrode 44.
A large number of such thin film transistors are arranged in a matrix on the glass substrate 50 and act as switching elements of the liquid crystal display device.

In such a thin film transistor, the resistance value of the channel region 1 is high. This is because the impurity element is inactivated by ion implantation and the carrier concentration is lowered in this region. Therefore, in the normal state, even if a voltage is applied between the source / drain regions 2 using the source / drain electrodes 44, these do not conduct. However, the gate electrode 41
When a voltage is applied to the channel region 1, an electric field due to the voltage V _g acts on the entire channel region 1 through the gate insulating film 42, and the electric field effect increases the carrier concentration of the channel region 1 and decreases its resistance. Then, when the gate voltage V _g reaches the threshold voltage V _th , conduction is established between the source / drain regions 2. That is, the thin film transistor is turned on.

Here, the gate voltage V _g required to turn on the thin film transistor, that is, the threshold voltage V _th, is the channel region 1 when the gate voltage V _g is zero.
Carrier concentration (hereinafter referred to as the original carrier concentration). The original carrier concentration is the concentration of the active impurity element in the channel region 1. This is because the impurity concentration when the polycrystalline silicon film 10 having a high impurity concentration is formed (S3 in FIG. 3) is ion-implanted (see FIG. This is obtained by subtracting the amount inactivated by S4) of 3). Here, since the polycrystalline silicon film 10 is formed with a high impurity concentration, CV
The D device can control the concentration with high accuracy, and the impurity concentration of the polycrystalline silicon film 10 has high accuracy. In the ion implantation, the number of implanted ions can be controlled with high accuracy. Therefore, the accuracy of the original carrier concentration in the channel region 1 is high.
Therefore, the threshold voltage V _th of each thin film transistor formed on one substrate is highly uniform.

This means that the liquid crystal display device can operate in multiple gradations. With this thin film transistor, the number of gradations of the display operation of the liquid crystal display device can be set to 128 or more.

Further, in this thin film transistor, the channel region 1 and the source / drain regions 2 are formed as a polycrystalline silicon film 10 having a high impurity concentration, which is ion-implanted to form the channel region 1 and the source / drain regions 2.
Since it is divided into, the contact resistance between the channel region 1 and the source / drain region 2 can be almost ignored.
Also, the channel length can be reduced. Therefore, the resistance at the time of on-reversal is small and high-speed operation is possible. Especially,
When n-type phosphorus or the like is used as the impurity element of the polycrystalline silicon film 10, since the mobility of electrons is higher than the mobility of holes, a higher speed operation is possible.

In addition, since the channel region 1 and the source / drain regions 2 are formed as a single-layer polycrystalline silicon film 10 in this thin film transistor, the number of photolithography operations is reduced by one and the number of photomasks is increased. Since the amount can be reduced by that amount, the manufacturing process is not complicated and is advantageous in terms of manufacturing cost.

Further, since high temperature heat treatment such as thermal diffusion is not used, a thin film transistor can be formed on the substrate without causing thermal damage to the substrate. Therefore, it is suitable for forming a thin film transistor as a switching element of a liquid crystal display device on a glass substrate which is weak against high temperature.

As described in detail above, according to the first embodiment, the polycrystalline silicon film 10 having a high impurity concentration is formed, and a part of this is subjected to ion implantation to inactivate the impurity element. Since the channel region 1 is used as the channel region and the rest is used as the source / drain region 2, a large number of thin film transistors are formed on the glass substrate 50 without heating the glass substrate 50 to an excessively high temperature, and the threshold voltages V _th thereof are uniform. Therefore, it can be manufactured by a simple manufacturing process. Further, the thin film transistor thus manufactured has low on-resistance and can operate at high speed. Therefore, the multi-gradation operation and the high speed operation of the liquid crystal display element are possible.

Second embodiment. This embodiment corresponds to claim 1, aspect 2, aspect 3 according to aspect 2, and aspect 4 according to aspect 2.

In this embodiment, basically, as shown in FIG. 6, a gate electrode is formed on a glass substrate (S11),
A gate insulating film is formed (S12), a polycrystalline silicon film is formed as a high impurity concentration doped film (S13), and a channel stopper film is formed to cover a portion to be a channel region (S14). Is removed (S1
5), source / drain electrodes are formed (S16), a channel region is formed in a part of the polycrystalline silicon film by ion implantation, and the rest is left as a source / drain region (S).
17) Finally, the whole is covered with a protective film (S18). The parts common to the first embodiment will be described in detail below with reference to FIGS. 4 and 5, focusing on the differences while citing the above description.

Formation of the gate electrode 41 (S11 in FIG. 6) and formation of the gate insulating film 42 on the glass substrate 50 (FIG. 6).
S12), and a high impurity concentration polycrystalline silicon film 1
Regarding the formation of 0 (which may be an amorphous silicon film) (S13 of FIG. 6), the first embodiment (S1 of FIG. 3).
There is no difference from S3). FIG. 4A shows this S13.
FIG. 1A shows the same structure as that of FIG. 1A.

Next, as shown in FIG. 4B, a silicon nitride channel stopper 43 is formed on the polycrystalline silicon film 10 by CVD (S14 in FIG. 6). The channel stopper 43 is an etching stopper for preventing a portion of the polycrystalline silicon film 10 to be a channel region by ion implantation described later from being etched during the etching process of the source / drain electrodes described later. , It is formed so as to cover the part and protrude a little to the outside. The channel stopper 43 and its formation are those described in S5 of FIG. 3 of the first embodiment (see FIG. 1).
It is the same as (c)). However, in this embodiment, it is necessary to make the total film thickness of the channel stopper 43 and the polycrystalline silicon film 10 thinner than the film thickness of the gate insulating film 42. This is to prevent ions from entering the glass substrate 50 during the ion implantation described later.

Subsequently, as shown in FIG. 4C, the polycrystalline silicon film 10 is processed by photolithography and etching to remove unnecessary portions (S15 in FIG. 6). By this etching, only the portions of the polycrystalline silicon film 10 that should be the channel region and the source / drain regions of the thin film transistor are left. This etching corresponds to S6 in FIGS. 2A and 3 in the first embodiment. The order of forming the channel stopper 43 shown in FIG. 4B and the etching process may be interchanged.

Then, as shown in FIG. 5A, the source / drain electrodes 44 are formed of a metal such as aluminum on the portions of the polycrystalline silicon film 10 to be the source / drain regions (see FIG. 6). S16). The source / drain electrodes 44 are formed by forming a solid film of the metal by sputtering or CVD, forming a resist mask 62 thereon by photolithography, and processing the solid film by etching. During this etching process, the polycrystalline silicon film 10 is also etched under the etching conditions of the source / drain electrodes 44, so that the portion that should become the channel region may be damaged, and a countermeasure is required to prevent this. Here, the channel stopper 43 fulfills the protective function for its protection. The source / drain electrodes 44 thus formed cover the upper surfaces of the portions to be the source / drain regions and make ohmic contact with them. The formation of the source / drain electrodes 44 is the electrode forming step according to the second aspect, and corresponds to S7 in FIG. 2B and FIG. 3 in the first embodiment.

Next, the channel region 1 is formed by ion implantation (S17 in FIG. 6, FIG. 5B). This ion implantation corresponds to step S4 in FIGS. 1B and 3 in the first embodiment, and is the channel forming step according to the second aspect. Therefore, the implanted ions are ions of any one of Si, F, and Ar. At this time, the resist mask 62 formed when the source / drain electrode 44 was formed immediately before acts as a stopper for ions to shield the ions, and thus should be the source / drain regions of the polycrystalline silicon film 10. Ions are not implanted into the portion, and ions are implanted only into the portion that should become the channel region. Then, in that portion, the impurity element is inactivated due to the implanted ions, the carrier concentration is reduced, and the conductivity is lowered, and this portion becomes the channel region 1. On the other hand, in the portion covered with the resist mask 62 and the source / drain electrodes 44, the ions are shielded, so that the carrier concentration is maintained at a high value during film formation. This portion becomes the source / drain region 2. Since the thermal diffusion is not performed after this ion implantation, the glass substrate 50 is not damaged by heat.

At this time, the acceleration energy of the implanted ions is low enough to prevent the ions from passing through the gate insulating film 42 in the regions outside the resist mask 62 and the source / drain electrodes 44 in FIG. 5B. Since the glass substrate 50 in this part is covered only by the gate insulating film 42, if implanted with too high energy, ions will enter the glass substrate 50 through the gate insulating film 42, which is preferable for a display device such as clouding of glass. This is because it causes a phenomenon that does not occur. On the other hand, a certain amount of energy is required so that the implanted ions are distributed throughout the thickness of the polycrystalline silicon film 10. This is because if the acceleration energy is too low, a portion where the carrier concentration remains high remains in the portion of the thickness of the polycrystalline silicon film 10 that is closer to the gate insulating film 42, which impairs the function of the thin film transistor. Here, as described above, since the total film thickness of the channel stopper 43 and the polycrystalline silicon film 10 is smaller than the film thickness of the gate insulating film 42, the ions do not enter the glass substrate 50, and the ions do not enter the glass substrate 50. The acceleration energy can be selected so that it is distributed over the entire thickness of the polycrystalline silicon film 10.

Further, in FIG. 5B, the resist mask 62 is used.
Although the ion implantation is performed with the above remaining, the ion implantation may be performed after removing the resist mask 62. This is because the self-alignment action of the source / drain electrodes 44 having the same pattern as that of the resist mask 62 prevents the ion implantation into portions other than the portions to be the channel regions.

Then, after forming the necessary wiring,
As shown in FIG. 6C, when a protective film 45 of silicon nitride or silicon oxide is formed by CVD and the whole is covered (S1 in FIG. 6).
8), a thin film transistor element is completed.

The thin film transistor thus manufactured is
It has the same configuration as that of the first embodiment. That is, the channel region 1 which is a part of the polycrystalline silicon film 10 having a high impurity concentration and in which the impurity element is inactivated by the ion implantation of any one of Si, F, and Ar, and the polycrystalline silicon The source / drain region 2 which is the rest of the film 10, the gate electrode 41 which is provided wider than the source / drain region facing the channel region 1, and the gate insulation which insulates the channel region 1 and the source / drain region 2 from the gate electrode 41. It has a film 42 and a source / drain electrode 44 which makes ohmic contact with the source / drain region 2. Then, such a thin film transistor is used as the glass substrate 5.
A large number of them are present in a matrix on the LCD and serve as switching elements of the liquid crystal display device.

Therefore, as in the case of the first embodiment, the thin film transistors are characterized in that the threshold voltage V _th of each thin film transistor is highly uniform, which allows the liquid crystal display device to operate in multiple gradations. is there. In addition, the channel region 1 and the source
The contact resistance with the drain region 2 can be almost ignored and the channel length can be shortened, so that the ON resistance is small and high-speed operation is possible, which is also the same as that of the first embodiment. Further, the source / drain electrode 4 is of course formed by forming the channel region 1 and the source / drain region 2 as a single-layer polycrystalline silicon film 10.
Since the resist mask 62 for processing 4 or the source / drain electrode 44 itself is used as a pattern mask for ion implantation and photolithography for only ion implantation is not performed, the manufacturing process is greatly simplified. In addition, since high temperature heat treatment is not performed, a thin film transistor can be formed over a glass substrate which is weak against high temperature and can be used for a switching element of a liquid crystal display device.

As described above in detail, according to the second embodiment, the polycrystalline silicon film 10 having a high impurity concentration is formed, and the source / drain electrodes are formed on the portions to be the source / drain regions 2. 44 is formed, and the portion of the polycrystalline silicon film 10 which is not covered by the source / drain electrodes 44 is ion-implanted to inactivate the impurity element to form the channel region 1 and the rest is used as the source / drain region 2. Therefore, it is possible to manufacture a large number of thin film transistors on the glass substrate 50 without heating the glass substrate 50 to an excessively high temperature so that the threshold voltages V _th of the thin film transistors become uniform and by a simple manufacturing process. . Further, the thin film transistor thus manufactured has low on-resistance and can operate at high speed. Therefore, the multi-gradation operation and the high speed operation of the liquid crystal display element are possible.

Although the above description has been made in accordance with the first and second embodiments, the present invention is not limited to the above-described embodiments, and various designs are possible without departing from the spirit of the present invention. It goes without saying that changes can be made. For example, the specific components of various thin films such as the insulating film and the metal film described in each of the above embodiments may be replaced with other components having the same function.

In addition, in each of the above-described embodiments, an example in which a thin film transistor is formed on a glass substrate for use as a switching element of a liquid crystal display device is shown. The present invention can be applied to the case of forming. For example, it can be considered to be applied to the formation of transistors in the second and subsequent stages of a three-dimensional integrated circuit. This is because the aluminum wiring or the like for the first-stage transistor that has already been manufactured dislikes high-temperature heat treatment.

[0062]

According to the method of manufacturing a thin film transistor of the present invention, a semiconductor thin film having a high impurity concentration is formed, and a part of the thin film is inactivated by impurity implantation to form a channel region and the remaining portion. Are used as the source region and the drain region, the threshold voltage V _{th of the} thin film transistor to be manufactured can be stably and uniformly obtained. Further, since a high temperature heat treatment process is not used, such a substrate is susceptible to high temperature. A thin film transistor can be formed.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a method of manufacturing a thin film transistor according to a first embodiment.

FIG. 2 is a diagram illustrating a method of manufacturing the thin film transistor according to the first embodiment.

FIG. 3 is a diagram showing a flow of a method of manufacturing the thin film transistor shown in FIGS. 1 and 2.

FIG. 4 is a diagram illustrating a method of manufacturing the thin film transistor according to the second embodiment.

FIG. 5 is a diagram illustrating a method of manufacturing the thin film transistor according to the second embodiment.

6 is a diagram showing a flow of a method of manufacturing the thin film transistor shown in FIGS. 4 and 5. FIG.

FIG. 7 is a diagram showing a flow of a conventional method of manufacturing a thin film transistor.

FIG. 8 is a diagram illustrating a conventional method of manufacturing a thin film transistor.

[Explanation of symbols]

 1 channel region 2 source / drain region 10 polycrystalline silicon thin film 41 gate electrode 42 gate insulating film

Claims (1)

[Claims] 1. A gate structure forming step of forming a gate electrode and a gate insulating film; a film forming step of forming a semiconductor thin film having a high impurity concentration so as to be insulated from the gate electrode; and a gate electrode of the semiconductor thin film. A step of forming a channel region by ion-implanting a part of the facing portion and making the rest a source region and a drain region, wherein the ions implanted by the ion implantation are impurity elements in the semiconductor thin film. A method for manufacturing a thin film transistor, wherein the thin film transistor is an ion that inactivates.