JPH097809A - Thin film resistor and its manufacturing method - Google Patents
Thin film resistor and its manufacturing methodInfo
- Publication number
- JPH097809A JPH097809A JP7154430A JP15443095A JPH097809A JP H097809 A JPH097809 A JP H097809A JP 7154430 A JP7154430 A JP 7154430A JP 15443095 A JP15443095 A JP 15443095A JP H097809 A JPH097809 A JP H097809A
- Authority
- JP
- Japan
- Prior art keywords
- electrodes
- resistance value
- substrate
- resistor
- target
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 238000000034 method Methods 0.000 claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 claims abstract description 7
- 238000007740 vapor deposition Methods 0.000 claims description 12
- 238000009966 trimming Methods 0.000 claims description 10
- 239000010409 thin film Substances 0.000 claims description 9
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 238000005259 measurement Methods 0.000 claims description 5
- 239000002245 particle Substances 0.000 abstract description 5
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 230000008020 evaporation Effects 0.000 abstract description 3
- 238000001704 evaporation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 30
- 239000010408 film Substances 0.000 description 9
- 239000011521 glass Substances 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000010304 firing Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 2
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 2
- 238000005488 sandblasting Methods 0.000 description 2
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000005562 fading Methods 0.000 description 1
- 230000009191 jumping Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Landscapes
- Apparatuses And Processes For Manufacturing Resistors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、チップ状の薄膜抵抗器
およびその製造方法の改良に関わる。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to improvements in a chip-shaped thin film resistor and a manufacturing method thereof.
【0002】[0002]
【従来の技術】従来から一般的なチップ抵抗器は、厚み
0.5mm程度のセラミック基板の表面に厚膜法(印刷
・焼成)により一対の電極を形成し、この両電極間に厚
膜法または薄膜法(蒸着)により抵抗体を膜状に形成す
るのであるが、前記厚膜法や薄膜法では例えばその印刷
条件や蒸着時間などをいかに精度良く行っても所定の抵
抗値を得ることが困難であるため、前記抵抗体を形成し
た後、その抵抗値を測定しながらレーザトリミングまた
はサンドブラストでその一部分を切り欠くことにより抵
抗値を許容差内に調整するのが一般的であった。2. Description of the Related Art Conventionally, a general chip resistor has a pair of electrodes formed on the surface of a ceramic substrate having a thickness of about 0.5 mm by a thick film method (printing and firing), and a thick film method is provided between both electrodes. Alternatively, the resistor is formed in a film shape by a thin film method (evaporation). In the thick film method and the thin film method, however, a predetermined resistance value can be obtained no matter how accurately the printing conditions and the evaporation time are performed. Since it is difficult, after forming the resistor, it is common to adjust the resistance within a tolerance by notching a part of it by laser trimming or sandblasting while measuring the resistance.
【0003】[0003]
【発明が解決しようとする問題点】ところが、上述した
ような抵抗値の調整をおこなう場合には下述するうな様
々な問題が発生するのである。すなわち、近年上述した
チップ抵抗器の生産効率の向上や小型化(最小のもので
縦1mm、横0.5mm)の要求から、大型のセラミッ
ク基板の表面に縦横のスリットで区画された複数の領域
に、上述した一対の電極と抵抗体をそれぞれ膜状形成し
た後、前記スリットで分割前の基板状態のままでトリミ
ングする必要がある。しかしながら、このように基板状
態のままでトリミングしようとすると、前記分割用のス
リットの毛細管現象により電気的に分離しているはずの
電極同士が短絡することがあり、このように短絡した時
には目標の抵抗体の抵抗値が測定できない結果、精度良
く目標抵抗値にトリミングできないといった問題が生じ
ることがある。また、前述したようなレーザやサンドブ
ラストにより切り欠き状に抵抗体形状を変形させてトリ
ミングを行う場合、その切り欠きを含む抵抗体の膜をガ
ラスや樹脂で覆った後も表面に凹凸が残ることがあり、
このような凹凸により、その表面に抵抗値等を標印時に
かすれが生じたり、コレットで吸着して回路基板に実装
する場合に抵抗器がコレットから脱落したりする問題も
生じる恐れがあった。However, when the resistance value is adjusted as described above, various problems as described below occur. That is, in recent years, in order to improve the production efficiency and miniaturize the chip resistors described above (minimum size is 1 mm in length and 0.5 mm in width), a plurality of regions divided by vertical and horizontal slits on the surface of a large ceramic substrate. In addition, it is necessary to form the above-mentioned pair of electrodes and the resistor in the form of films, respectively, and then trim by the slit in the state of the substrate before the division. However, when attempting to trim the substrate in such a state, the electrodes that should be electrically separated from each other may be short-circuited due to the capillary phenomenon of the slit for division. As a result of being unable to measure the resistance value of the resistor, there may occur a problem that the target resistance value cannot be trimmed accurately. Also, when trimming is performed by deforming the resistor shape into a notch shape by laser or sandblasting as described above, unevenness may remain on the surface even after covering the resistor film including the notch with glass or resin. There is
Due to such unevenness, there may be a problem that a resistance value or the like may be fainted on the surface at the time of marking, or the resistor may fall off from the collet when it is sucked by the collet and mounted on the circuit board.
【0004】また、上述したような抵抗体の膜を切り欠
くなどの形状変形を伴わないトリミングとして、過去に
はパルス電圧やパルス電流を抵抗体の膜に印加して抵抗
値を下げることにより所定の抵抗値を得るようにする方
法が提案されたことがある(特公昭51−4253号参
照)。しかしながら、この方法では前記1回のパルスで
どの程度の抵抗値が下がるのか概ね予想がつくものの、
所望の抵抗値を精度良く得るためには複数回のパルスを
印加して徐々に抵抗値を下げるような面倒なトリミング
作業を行う必要があるばかりか、これを制御するために
複雑な制御プログラムを組むなどの必要性があった。こ
のような方法では抵抗値の調整(トリミング)にコスト
がかかり、単価が1円を割っているようなチップ抵抗器
の製造には効率が悪く不向きであった。Further, as trimming that does not involve shape deformation such as notching the resistor film as described above, in the past, a predetermined value was obtained by applying a pulse voltage or pulse current to the resistor film to reduce the resistance value. There has been proposed a method for obtaining the resistance value of (see Japanese Patent Publication No. 51-4253). However, with this method, it is possible to predict how much the resistance value will decrease with one pulse, but
In order to obtain a desired resistance value with high accuracy, it is necessary to apply a pulse multiple times to gradually reduce the resistance value and perform a troublesome trimming work, and to control this, a complicated control program is required. There was a need to assemble. In such a method, it takes a high cost to adjust (trim) the resistance value, and the efficiency is poor and unsuitable for manufacturing a chip resistor whose unit price is less than one yen.
【0005】本発明は、このような面倒なトリミング作
業をなくした抵抗器の製造方法および表面に凹凸の少な
い抵抗器を提供することを目的とするものである。It is an object of the present invention to provide a method of manufacturing a resistor which eliminates such troublesome trimming work, and a resistor having less surface irregularities.
【0006】[0006]
【課題を解決するための手段】本発明者は、上記技術的
課題を達成するため、本願発明では以下のような技術的
手段を講じている。請求項1では、基板の表面に離間さ
れた一対の電極を設け、この電極の間の抵抗値を測定し
つつ当該両電極に跨るように抵抗層の蒸着を開始し、前
記両電極間の抵抗値が所定値になるように前記蒸着を終
了することを特徴としている。The present inventor has taken the following technical means in the present invention in order to achieve the above technical objects. According to claim 1, a pair of electrodes is provided on the surface of the substrate, the resistance layer between the electrodes is vapor-deposited so that the resistance value between the electrodes is measured while measuring the resistance value between the electrodes. It is characterized in that the vapor deposition is terminated so that the value becomes a predetermined value.
【0007】また、請求項2では、前記請求項1が抵抗
層を設ける前から測定を開始しているのに対し、所定の
時間経過後に測定を開始するようにしたものである。す
なわち、基板の表面に離間した一対の電極を設け、この
両電極に跨るように抵抗層の蒸着を開始後、所定時間後
に前記両電極間の抵抗値の測定を始め、前記両電極間の
抵抗値が所定値になるように前記蒸着を終了することを
特徴としている。Further, in the second aspect, the measurement is started before the resistance layer is provided in the first aspect, whereas the measurement is started after a predetermined time has elapsed. That is, a pair of electrodes that are spaced apart from each other is provided on the surface of the substrate, and after the vapor deposition of the resistance layer is started across both electrodes, measurement of the resistance value between both electrodes is started after a predetermined time, and the resistance between both electrodes is It is characterized in that the vapor deposition is terminated so that the value becomes a predetermined value.
【0008】さらに、請求項3では、基板の表面に一対
の電極を設け、この電極間に薄膜法により抵抗体を設け
てなる抵抗器であって、前記電極間に設けた抵抗体を切
り欠き状のトリミングまたはパルストリミングを施すこ
となく所定の抵抗値に設定することを特徴としている。According to a third aspect of the present invention, there is provided a resistor having a pair of electrodes provided on the surface of a substrate and a resistor provided between the electrodes by a thin film method, wherein the resistor provided between the electrodes is cut out. It is characterized in that the resistance value is set to a predetermined value without performing the strip-shaped trimming or the pulse trimming.
【0009】[0009]
【発明の作用および効果】以上のようになされた本発明
では以下のような作用および効果を奏する。すなわち、
基板の表面に離間した一対の電極を設け、この電極間の
抵抗値を測定しながら電極間に跨るように抵抗層を蒸着
し層厚を漸次厚くすることにより、その抵抗層の断面積
が増大しそれに比例して抵抗値が小さくなる。そして、
所定の抵抗値になるように蒸着を終了する。The functions and effects of the present invention as described above have the following functions and effects. That is,
By providing a pair of spaced electrodes on the surface of the substrate, measuring the resistance value between the electrodes, and vapor-depositing the resistance layer across the electrodes to gradually increase the layer thickness, the cross-sectional area of the resistance layer increases. However, the resistance value decreases in proportion to it. And
The vapor deposition is completed so that the resistance becomes a predetermined value.
【0010】このようにして製造された抵抗器は、切り
欠き状のトリミングまたはパルストリミングを施すこと
ない抵抗器を得ることが可能となる。そして、前述した
抵抗器は、切り欠き状に抵抗層を変形させていないか
ら、抵抗層の上に被覆用のガラスや樹脂を設けても表面
に凹凸は生じ難くなる結果、例えば表印を施す場合には
そのかすれの恐れを低減できるし、コレットによって回
路基板に実装する場合には脱落の恐れを少なくすること
ができる。With the resistor manufactured in this way, it is possible to obtain a resistor which is not subjected to notch-shaped trimming or pulse trimming. Further, in the above-mentioned resistor, since the resistance layer is not deformed in a notch shape, even if glass or resin for coating is provided on the resistance layer, it is difficult to cause unevenness on the surface. In that case, the risk of fading can be reduced, and in the case where the collet is mounted on the circuit board, the risk of dropping can be reduced.
【0011】[0011]
【実施例】本発明を図1に基づいて以下に説明する。図
において1はアルミナ素材からなる基板であって、この
基板1の表面には縦と横の溝2、3が形成され、その縦
溝2と横溝3によって複数の領域4・・4に区画されて
いる。この区画された領域4のそれぞれの表面に離間さ
れた一対の電極5、5を印刷焼成により設け、この電極
5、5の間に跨るように抵抗層6をスパッタリングによ
り形成してある。この実施例では、抵抗層6をスパッタ
リングにより形成するようにしたがこれに限らず、蒸着
により形成することもできる。前述したスパッタリング
や蒸着により抵抗層6を形成した抵抗器を一般的に薄膜
抵抗器と呼び、他の種類として抵抗層6を印刷/焼成に
より形成する厚膜抵抗器が存在する。The present invention will be described below with reference to FIG. In the figure, 1 is a substrate made of an alumina material. Vertical and horizontal grooves 2 and 3 are formed on the surface of the substrate 1, and the vertical and horizontal grooves 2 and 3 divide the substrate into a plurality of regions 4 ... ing. A pair of separated electrodes 5 and 5 are provided on each surface of the partitioned region 4 by printing and firing, and a resistance layer 6 is formed by sputtering so as to extend between the electrodes 5 and 5. In this embodiment, the resistance layer 6 is formed by sputtering, but the present invention is not limited to this, and it may be formed by vapor deposition. The resistor in which the resistance layer 6 is formed by the above-mentioned sputtering or vapor deposition is generally called a thin film resistor, and as another type, there is a thick film resistor in which the resistance layer 6 is formed by printing / baking.
【0012】次に、前述した抵抗層6を形成する方法を
図2に基づいて詳述する。この図2は、前述した一つの
領域4に抵抗層6を形成する状態を示す模式図であり、
実際には、図1に示すように各電極5に形成されたスル
ーホール7を介して基板1の裏面1A側に測定装置8を
配置し、この測定装置8から図示しないプローブをスル
ーホール7に電気的に接続することによって、基板1上
に一列に並ぶ抵抗層6・・6を前記測定装置8で測定し
つつ目標抵抗値に形成するようにしている。Next, a method for forming the above-mentioned resistance layer 6 will be described in detail with reference to FIG. FIG. 2 is a schematic view showing a state in which the resistance layer 6 is formed in the one region 4 described above,
Actually, as shown in FIG. 1, a measuring device 8 is arranged on the back surface 1A side of the substrate 1 through the through holes 7 formed in each electrode 5, and a probe (not shown) is inserted from the measuring device 8 into the through hole 7. By electrically connecting, the resistance layers 6, 6 arranged in a line on the substrate 1 are formed to have a target resistance value while being measured by the measuring device 8.
【0013】図2に示す9は、抵抗層6を形成する基材
としてのターゲットであって、その成分は含有量が酸化
ルテニュウム7〜14%、他をガラスを含む金属酸化物
から構成されている。他のターゲット9の材料として
は、上述した成分のものに限らず酸化ルテニュウム46
〜17%、銀0〜31%、Pd0〜13%、ガラス54
〜39%の含有率のものを採用することもできる。Reference numeral 9 shown in FIG. 2 is a target as a base material for forming the resistance layer 6, the component of which is composed of a ruthenium oxide of 7 to 14% and a metal oxide containing glass other than the above. There is. The material of the other target 9 is not limited to the above-mentioned components, but ruthenium oxide 46.
-17%, silver 0-31%, Pd 0-13%, glass 54
It is also possible to employ a content rate of up to 39%.
【0014】前記ターゲット9と基板1との間には、基
板1側からマスク10とシャッタ11を順次配置してお
り、ターゲット9に例えばアルゴン原子をぶつけてター
ゲット9から飛び出した抵抗層6の形成粒子を前記基板
1の表面にマスク10によって抵抗層6の形成領域を制
限しつつ付着させる。そして、測定装置8により電極
5、5の間の抵抗値を連続的に測定し、測定装置8が目
標抵抗値になった時または目標抵抗値の許容差内に入っ
た時に前記シャッタ11によってターゲット9から飛び
出した前記形成粒子が基板1表面に到達しないように遮
断する。図2においてマスク10と基板1は離間した状
態で図示されているが、マスク10にレジストを使用す
れば基板1と密着した状態として、照射される前記形成
粒子か抵抗層6を形成すべき領域外に付着することを防
止できる。また、前述したようにこの実施例では、シャ
ッタ11を抵抗層6を形成する基板1とターゲット9と
の間に設ける構成を採用してあるから、測定装置8で前
記抵抗層6が所定抵抗値になった段階で、瞬時にそれ以
上抵抗値が変化することを阻止することが可能となり、
目標抵抗値を精度良く得ることができる。仮に、前述し
たようなシャッタ11を採用しなかった場合には、スパ
ッタリングや蒸着を停止してからの抵抗値変化量を予測
し、この抵抗値変化量を目標抵抗値に加えた仮想の目標
抵抗値に達した時または目標抵抗値の許容差範囲内に入
った時に、前述したスパッタリングや蒸着による抵抗層
6の形成を停止することもできる。A mask 10 and a shutter 11 are sequentially arranged between the target 9 and the substrate 1 from the side of the substrate 1 to form a resistance layer 6 protruding from the target 9 by hitting the target 9 with, for example, argon atoms. The particles are attached to the surface of the substrate 1 by the mask 10 while limiting the formation region of the resistance layer 6. Then, the resistance value between the electrodes 5 and 5 is continuously measured by the measuring device 8, and when the measuring device 8 reaches the target resistance value or is within the tolerance of the target resistance value, the shutter 11 targets the target. The formed particles jumping out of 9 are blocked so as not to reach the surface of the substrate 1. In FIG. 2, the mask 10 and the substrate 1 are illustrated as being separated from each other, but if a resist is used for the mask 10, it is in a state in which the mask 10 and the substrate 1 are in close contact with each other and a region where the forming particles to be irradiated or the resistance layer 6 is to be formed It can be prevented from adhering to the outside. Further, as described above, in this embodiment, since the shutter 11 is provided between the substrate 1 on which the resistance layer 6 is formed and the target 9, the resistance layer 6 of the measuring device 8 has a predetermined resistance value. When it becomes, it becomes possible to prevent the resistance value from changing further in an instant.
The target resistance value can be obtained accurately. If the shutter 11 as described above is not adopted, the resistance value change amount after the sputtering or vapor deposition is stopped is predicted, and the virtual target resistance value obtained by adding the resistance value change amount to the target resistance value is predicted. It is also possible to stop the formation of the resistance layer 6 by the above-described sputtering or vapor deposition when the value is reached or when it falls within the tolerance range of the target resistance value.
【0015】このようにして所定抵抗値の抵抗層6を電
極5、5間に形成した後、抵抗層6の表面をガラスまた
は樹脂からなる絶縁性の保護層12で被覆するととも
に、電極5、5と裏面電極13、13とに跨るように側
面電極14を形成し、前記電極5と裏面電極13および
側面電極14を覆うニッケルメッキ15およびハンダメ
ッキ16とを形成してチップ抵抗器を完成する。After the resistance layer 6 having a predetermined resistance value is thus formed between the electrodes 5 and 5, the surface of the resistance layer 6 is covered with an insulating protective layer 12 made of glass or resin, and the electrodes 5 and 5 are formed. 5, the side electrode 14 is formed so as to extend over the back electrode 13 and the back electrode 13, and the nickel plating 15 and the solder plating 16 that cover the electrode 5, the back electrode 13 and the side electrode 14 are formed to complete the chip resistor. .
【0016】図3に示すのは、本発明の他の実施例を示
す。前述した実施例では、基板1の表面に全く抵抗層6
を形成していない状態から測定装置8によって測定を開
始するものであったが、この他の実施例では、予め電極
5、5間に目標抵抗値に近い抵抗層6を形成しておき、
その抵抗層6の上に電極間5、5の抵抗値を測定しつつ
更成なる抵抗層17を形成し、前述した実施例と同じよ
うに目標抵抗値となったときに図示しないシャッタを閉
じて目標抵抗値を得るようにしてある。FIG. 3 shows another embodiment of the present invention. In the above-described embodiment, the resistance layer 6 is not formed on the surface of the substrate 1.
The measurement was started by the measuring device 8 from the state in which the resistance layer 6 was not formed, but in this other embodiment, the resistance layer 6 close to the target resistance value was previously formed between the electrodes 5 and 5,
A further resistance layer 17 is formed on the resistance layer 6 while measuring the resistance values between the electrodes 5 and 5, and a shutter (not shown) is closed when the target resistance value is reached as in the above-described embodiment. The target resistance value is obtained.
【図1】実施例を示す斜視図である。FIG. 1 is a perspective view showing an embodiment.
【図2】抵抗層の形成状態を示す模式図である。FIG. 2 is a schematic view showing a formation state of a resistance layer.
【図3】抵抗器の完成状態を示す断面図である。FIG. 3 is a cross-sectional view showing a completed state of the resistor.
【図4】他の実施例を示す模式図である。FIG. 4 is a schematic view showing another embodiment.
1 基板 5 電極 1 substrate 5 electrodes
Claims (3)
け、この電極の間の抵抗値を測定しつつ当該両電極に跨
るように抵抗層を蒸着またはスパッタリングによる形成
を開始し、前記両電極間の抵抗値が所定値になるように
前記蒸着を終了することを特徴とする薄膜抵抗器の製造
方法。1. A pair of electrodes separated from each other is provided on the surface of a substrate, and a resistance layer is formed by vapor deposition or sputtering so as to extend over both electrodes while measuring a resistance value between the electrodes. A method of manufacturing a thin film resistor, characterized in that the vapor deposition is terminated so that a resistance value between electrodes becomes a predetermined value.
け、この両電極に跨るように抵抗層を蒸着またはスパッ
タリングによる形成を開始後、所定時間後に前記両電極
間の抵抗値の測定を始め、前記両電極間の抵抗値が所定
値になるように前記蒸着を終了することを特徴とする薄
膜抵抗器の製造方法。2. A pair of electrodes separated from each other is provided on the surface of a substrate, and after a resistance layer is formed by vapor deposition or sputtering so as to extend over both electrodes, measurement of a resistance value between the electrodes is started after a predetermined time. The method for manufacturing a thin film resistor, wherein the vapor deposition is terminated so that the resistance value between the electrodes becomes a predetermined value.
極間に薄膜法により抵抗体を設けてなる抵抗器であっ
て、前記電極間に設けた抵抗体を切り欠き状のトリミン
グまたはパルストリミングを施すことなく所定の抵抗値
に設定することを特徴とする薄膜抵抗器。3. A resistor comprising a pair of electrodes provided on a surface of a substrate, and a resistor provided between the electrodes by a thin film method, wherein the resistor provided between the electrodes is notched or trimmed or pulsed. A thin film resistor, which is set to a predetermined resistance value without trimming.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154430A JPH097809A (en) | 1995-06-21 | 1995-06-21 | Thin film resistor and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7154430A JPH097809A (en) | 1995-06-21 | 1995-06-21 | Thin film resistor and its manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH097809A true JPH097809A (en) | 1997-01-10 |
Family
ID=15584017
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7154430A Pending JPH097809A (en) | 1995-06-21 | 1995-06-21 | Thin film resistor and its manufacturing method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH097809A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006165117A (en) * | 2004-12-03 | 2006-06-22 | Toppan Printing Co Ltd | Resistance element built-in substrate and manufacturing method thereof |
| EP3451352A1 (en) * | 2017-08-28 | 2019-03-06 | Hochschule Für Angewandte Wissenschaften München | High-precision additive formation of electrical resistors |
| CN116419661A (en) * | 2021-12-29 | 2023-07-11 | 苏州能讯高能半导体有限公司 | A kind of semiconductor device and its preparation method |
-
1995
- 1995-06-21 JP JP7154430A patent/JPH097809A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006165117A (en) * | 2004-12-03 | 2006-06-22 | Toppan Printing Co Ltd | Resistance element built-in substrate and manufacturing method thereof |
| EP3451352A1 (en) * | 2017-08-28 | 2019-03-06 | Hochschule Für Angewandte Wissenschaften München | High-precision additive formation of electrical resistors |
| US10366813B2 (en) | 2017-08-28 | 2019-07-30 | Hochschule für angewandte Wissenschaften München | High-precision additive formation of electrical resistors |
| CN116419661A (en) * | 2021-12-29 | 2023-07-11 | 苏州能讯高能半导体有限公司 | A kind of semiconductor device and its preparation method |
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