JPH098006A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] By etching the polysilicon provided with the dummy region, the polysilicon is processed accurately according to the resist pattern, and the non-defective rate is improved. [Structure] Polysilicon 3 is deposited on a semiconductor substrate 1 with an oxide film 2 interposed therebetween, leaving polysilicon 3a in an active region and polysilicon 3b to be a dummy region 5 and etching polysilicon in other portions. Next, the resist 4 is removed, the resist is entirely covered again, and then the dummy region 5 is formed.
The resist 6 for etching only the polysilicon 3b of FIG. 2 is patterned (FIG. 2A), and the polysilicon 3b of the dummy region 5 is etched and removed (FIG. 2A).
(B)) Finally, the resist is removed, and the processing of the polysilicon 3 is completed (FIG. 2 (c)).

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device such as a MOS type integrated circuit element using polysilicon for a gate electrode and wiring.

[0002]

2. Description of the Related Art A MOS type integrated circuit element using polysilicon for a gate electrode, a wiring, a resistor, etc. of a MOS device is required to have a narrow and constant width of polysilicon as miniaturization progresses. FIG. 3 is a conventional manufacturing method of a MOS type integrated circuit device, and FIGS. 3A to 3C are process diagrams showing the order of manufacturing processes. An oxide film 2 is coated on a semiconductor substrate 1 having an integrated circuit built therein, polysilicon 3 is deposited on the oxide film 2 by a chemical deposition method (CVD method) or the like, and then a resist is coated to form a photomask. A patterning step of transferring the pattern to the resist 4 (the same figure (a)), and an etching step of removing the polysilicon 3 by RIE or plasma etching using the transferred resist 4 as a mask (the same figure (b)). , A step of removing the resist 4 (FIG. 7C).

[0003]

FIG. 4 shows the relationship between the polysilicon size after etching and the ratio of the polysilicon pattern area (area in resist size) to the chip area by the conventional manufacturing method. The vertical axis of the figure shows the polysilicon size after etching. In this example, the resist size is 2 μm. As can be seen from the figure, in the conventional manufacturing method, the ratio of the area where polysilicon is left is 15%.
In the following cases, the polysilicon after etching becomes thinner than the resist size, and when it becomes about 3%, the polysilicon size becomes about 1 μm, and side etching is performed up to half of the resist size. Further, the dimensions vary depending on the location, which causes a problem that the design performance of the integrated circuit cannot be obtained. Therefore, CMs for driver LSIs (LSI: Highly Integrated ICs) and operational amplifiers (commonly called operational amplifiers) that integrate a large number of identical circuits in a chip
It is difficult to manufacture an analog CMOS LSI composed of an OS device (complementary MOS device) with a high yield rate.

In order to solve the above-mentioned problems, an object of the present invention is to provide a dummy region to reduce the area for etching polysilicon, and to reduce the area of polysilicon in the active region such as the gate electrode as the entire chip (or wafer). It is another object of the present invention to provide a method for manufacturing a semiconductor device which is a MOS type integrated circuit element capable of suppressing the reduction of the dimension (line width etc.) with respect to a resist pattern and processing polysilicon evenly and accurately even if the number is small.

[0005]

In order to achieve the above object, a first resist coating step of coating a resist on polysilicon and a polysilicon of a dummy area together with polysilicon of an active area such as a gate area and a wiring area. The first patterning step of removing the resist other than these areas while leaving the resist coated on the silicon, the first etching step of removing the polysilicon using the resist as a mask, and the resist on the dummy area only. The second patterning step includes a second etching step of removing polysilicon in the dummy area and a step of removing the remaining resist.

Reactive ion etching (RIE) or plasma etching may be used for the first etching step and the second etching step. The area of polysilicon in the dummy region may be adjusted so that the area of polysilicon not etched in the first etching step is 10% or more of the area of the chip or wafer.

[0007]

[Function] In RIE and plasma etching, for example, CHF
A gas such as ₃ or CClF ₃ is ionized, and the ions are accelerated to collide with polysilicon to perform etching. At this time, the substance dissociated in the plasma forms a layer for suppressing the reaction on the polysilicon surface. Therefore, lateral etching due to radicals is prevented. On the other hand, the etching surface on which the ions collide prevents the formation of this inhibition layer (sidewall). Therefore, etching proceeds in the vertical direction. However, if the amount of polysilicon to be etched is large, the lateral component due to radicals increases, the formation of the inhibition layer is suppressed, and the amount of side etching increases. Therefore, in the present invention, a dummy region is provided in order to reduce the amount of polysilicon to be etched, and the formation of the inhibition layer is facilitated to suppress the side etch amount.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 and FIG. 2 show an embodiment, and FIGS. 1 (a) to 1 (c) and subsequent FIGS. 2 (a) to 2
(C) is a process diagram showing the order of manufacturing processes. On the semiconductor substrate 1 containing the integrated circuit, the polysilicon 3 is deposited with a thickness of about 400 nm by the low pressure CVD method or the like through the oxide film 2 to form a film. Next, a resist 4 is coated on the entire surface of the polysilicon 3 by a first patterning step, the pattern of the photomask is transferred to the resist 4 and patterned (FIG. 1).
(A)). Next, by the first etching step, in addition to the polysilicon 3a of the active region of the gate electrode, the wiring and the resistor of the MOS device, the polysilicon 3b of the dummy region 5 is left and the polysilicon of the other region is left. The silicon is etched using the resist 4 as a mask. in this case,
In order to prevent side etching, the area of the polysilicon 3b in the dummy region 5 is adjusted so that the area of the polysilicon not etched is 10% to 15% or more of the chip area or the wafer area (see FIG. 4). ) (Fig. 1 (b)). By doing so, the sidewalls are sufficiently formed at the time of etching, the side etching of the polysilicon is suppressed, and the polysilicon is etched with a dimension according to the resist pattern. After that, the resist is removed ((c) in the figure). After covering the entire surface with the resist, a resist 6 for etching only the polysilicon 3b in the dummy region 5 is patterned by a second patterning process. At this time, the resist pattern is designed so as to sufficiently cover the polysilicon 3a in the active region serving as the gate electrode, the wiring, and the resistor and not to cover the polysilicon 3b in the dummy region 5 (FIG. 2A). Using the resist 6 as a mask, the polysilicon 3b in the dummy region 5 is etched and removed in the second etching step (FIG. 2B). Finally, the resist is removed, and the processing of polysilicon is completed (FIG. 2C). Incidentally, the polysilicon 3 may be doped with impurities such as phosphorus and boron for adjusting the resistance value before etching. The etching of polysilicon in the first etching step and the second etching step is performed by reactive ion etching (RIE) or plasma etching.

[0009]

As described above, according to the present invention, it is possible to provide a polysilicon pattern having a small amount of side-etching and a small dimensional variation even in a chip having a small area ratio of polysilicon finally left. As a result, an analog CMOSLS in which a driver LSI, an operational amplifier, etc., in which a large number of the same circuits are integrated on one chip, is composed of CMOS devices
I can be manufactured with a high yield rate.

[Brief description of drawings]

1A to 1C are process diagrams showing the order of manufacturing processes in an embodiment of the present invention.

FIG. 2 is a process subsequent to FIG. 1 (c), in which (a) to (c)
Is a process diagram showing the order of manufacturing processes

FIG. 3 is a conventional manufacturing method of a MOS integrated circuit device,
(A) thru | or (c) are process drawings shown in order of manufacturing process.

FIG. 4 is a diagram showing a relationship between a polysilicon size after etching and a ratio of a polysilicon pattern area to a chip area by a conventional manufacturing method.

[Explanation of symbols]

 1 Semiconductor Substrate 2 Oxide Film 3 Polysilicon 3a Polysilicon in Active Region 3b Polysilicon in Dummy Region 4 Resist 5 Dummy Region 6 Resist

Claims (3)

[Claims] 1. A first resist coating step of coating a resist on polysilicon, and a first pattern for leaving the resist coated on the polysilicon of the active region and the dummy region and removing the resist except for these regions. Step, a first etching step of removing polysilicon using the resist as a mask, a second patterning step of removing only the resist on the dummy area, and a second etching step of removing the polysilicon in the dummy area, A method of manufacturing a semiconductor device, comprising the step of removing the remaining resist. 2. The reactive ion etching (RIE) or plasma etching is used in the first etching step and the second etching step.
The manufacturing method of the semiconductor device described in the above. 3. The area of polysilicon in the dummy region is adjusted so that the area of polysilicon not etched in the first etching step is 10% or more of the chip or wafer area. Manufacturing method of semiconductor device.