JPH098092A - MIS type transistor monitor - Google Patents

Abstract

PURPOSE: To provide an MIS transistor monitor capable of accurately reflecting the characteristics of an MIS transistor which constitute a product. CONSTITUTION: In order to measure the characteristics of a plurality of MIS transistors formed in the greater part of a region on the surface of a semiconductor substrate composed of silicon and the like, an MIS transistor monitor 1 is formed in a very small region on the surface of the semiconductor substrate. In the very small region of the semiconductor substrate, a gate electrode is formed via an insulating layer, and a wiring 6 for making electric charges flowing toward the insulating layer 4' from the outside via the gate electrode 4 escape is connected with the gate electrode.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MIS transistor monitor provided at a predetermined position on the same semiconductor substrate for measuring the characteristics of a plurality of MIS transistors provided on a semiconductor substrate.

[0002]

2. Description of the Related Art Conventionally, when a device such as a transistor is manufactured using a semiconductor substrate, a transistor monitor is manufactured in the same process, and the potential is controlled by the transistor monitor to judge the quality of the product. Is going.

For example, MOS type transistors and MNOS
In the case of manufacturing a MIS type transistor including a type transistor, etc., a MIS type transistor monitor is manufactured on the same semiconductor substrate in the same process as these MIS type transistors, and the threshold value of this MIS type transistor monitor is manufactured. By measuring the voltage, the characteristics of the MIS type transistor, which is the product, are evaluated. For this reason, a plurality of MIS type transistors, which are products, are manufactured in most of the area on the surface of the semiconductor substrate, and the MIS type transistor monitors are provided in the minute area on the same semiconductor substrate surface in the required number for measurement. .

[0004]

However, in the MIS transistor monitor using such a semiconductor substrate, charges are accumulated on the surface of the film forming the gate electrode or the surface of the gate electrode due to static electricity or various damages. (Charge up), and the potential shift occurs due to the injection into the insulating layer.

Particularly, in the MIS type transistor monitor, the area of the electrode pad made of aluminum or the like connected to the gate electrode is much larger than the area of the gate wiring made of polysilicon or the like. Is likely to be charged up. On the other hand, in the MIS transistor that is a product, since it is formed on most of the semiconductor substrate, the area ratio between the electrode pad and the gate wiring is much smaller than that of the MIS transistor monitor, so that the gate electrode is charged. Up is unlikely to occur.

As described above, even in the MIS type transistor and the MIS type transistor monitor manufactured through the same process, the state of charge-up to the gate electrode and charge injection to the insulating layer are caused by the difference in structure. Will be different. That is, when an attempt is made to perform characteristic evaluation using a MIS type transistor monitor, the potential shift caused by the charge-up causes characteristic mismatch with the product MIS type transistor, which makes accurate measurement difficult, and Type transistor will be adversely affected.

Therefore, an object of the present invention is to provide a MIS transistor monitor capable of faithfully reflecting the characteristics of the MIS transistor as a product.

[0008]

SUMMARY OF THE INVENTION The present invention is a MIS type transistor monitor made to achieve the above object. That is, the present invention is a MIS transistor monitor provided in a small area on the surface of a semiconductor substrate for measuring the characteristics of a plurality of MIS transistors provided on most of the surface of the semiconductor substrate. A wiring for releasing charges from the outside to the insulating layer via the gate electrode is connected to the gate electrode provided via the insulating layer in a minute region of the semiconductor substrate.

[0009]

In the MIS type transistor monitor of the present invention,
Since the wiring for releasing the charge from the outside to the insulating layer via the gate electrode is connected to the gate electrode provided via the insulating layer in a minute area of the semiconductor substrate, the static electricity generated during manufacturing or Even if charge-up occurs in the gate electrode due to damage or the like, before the charge due to this charge-up is injected into the insulating layer, this charge escapes to the outside through the connected wiring.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the MIS type transistor monitor of the present invention will be described below with reference to the drawings. FIG.
It is a conceptual diagram explaining the MIS type | mold transistor monitor of this invention. This MIS type transistor monitor 1 is manufactured by the same process as a plurality of MIS type transistors, which are products provided in most regions on the surface of a semiconductor substrate made of silicon or the like. Properly provided in the area.

In this MIS type transistor monitor 1, for example, the wiring 6 connected to the gate electrode 4 is connected to the electrode pad and is also in contact with the semiconductor substrate made of silicon or the like. In this state, in order for the charge-up charges (see the arrow in the figure) due to charge-up to flow into the insulating layer via the gate electrode 4, it is necessary to have energy enough to exceed the potential barrier of the insulating layer 4 ′. (Refer to the arrow in the figure).

On the other hand, in the charge-up charges (see the arrow in the figure) from the gate electrode 4 to the semiconductor substrate via the wiring 6 and the contact provided on the semiconductor substrate, the potential barrier due to the insulating layer 4'as described above is generated. Since it does not exist, it can easily flow into the semiconductor substrate (see the arrow in the figure).

That is, in the MIS transistor monitor 1 of the present invention, even if the charge-up charges flow from the electrode pad to the gate electrode 4 due to the occurrence of charge-up, most of them are not injected into the insulating layer 4 '. It will escape to the semiconductor substrate side via the wiring 6.

As described above, since the product MIS transistor is formed in most of the region of the semiconductor substrate, the area ratio between the electrode pad and the gate wiring is M.
It is much smaller than the IS-type transistor monitor 1 and is less likely to cause charge-up to the gate electrode. Therefore, by configuring the MIS transistor monitor 1 as in the present invention, the charge-up charges are not injected into any of the insulating layers, and the potential shift caused by this can be suppressed. That is, the MIS transistor monitor 1 of the present invention
In the above, the structure is such that the characteristics of the MIS type transistor as a product can be sufficiently reflected, and accurate product evaluation can be realized.

Next, a specific example of the MIS type transistor monitor of the present invention will be described. FIG. 2 shows the MI of the present invention.
It is a schematic cross section (the 1) explaining a specific example of an S type transistor monitor.

That is, the MIS type transistor monitor 1 in this specific example (No. 1) is of an N channel type formed on a semiconductor substrate 10 of mainly N type. This MIS type transistor monitor 1 includes a source electrode 2 connected to a high concentration N type diffusion layer 2 ′ provided on a semiconductor substrate 10 and a drain electrode 3 connected to a high concentration N type diffusion layer 3 ′. And a gate electrode 4 connected between the high-concentration N-type diffusion layers 2 ′ and 3 ′ through an insulating layer 4 ′ such as a silicon oxide film formed on the semiconductor substrate 10, and the gate electrode 4 The wiring 6 is connected from 4 to the P type diffusion layer 5 provided on the semiconductor substrate 10.

In order to release the charge-up charges shown in FIG. 1 to the semiconductor substrate 10 as soon as possible, the wiring 6 is made of a metal material such as aluminum having a smaller propagation delay than polycrystalline silicon.

The MIS type transistor monitor 1 is in a state in which charge-up is more likely to occur than the MIS type transistor as a product due to the so-called antenna effect. With such a structure, the MIS type transistor monitor 1 has On the other hand, even if charge up occurs,
Before the charge-up charge is injected into the insulating layer 4 ′, the charge-up charge escapes to the semiconductor substrate 10 via the wiring 6. That is, it becomes possible to prevent charge-up charges from being injected into the insulating layer 4 ′, and it is possible to match the characteristics with the MIS type transistor as a product.

When the characteristics are measured using this MIS type transistor monitor 1, for example, the semiconductor substrate 10 is used.
Voltage of −15 (V) is applied to the gate electrode 4, a voltage of −15 to +15 (V) is applied to the gate electrode 4, and current and voltage characteristics between the source electrode 2 and the drain electrode 3 at this time To measure.

When the characteristics are measured, a voltage of −15 to +15 (V) is applied to the wiring 6, but a P-type junction of the diffusion layer 5 and the N-type of the semiconductor substrate 10 causes a PN junction. Since it is configured, it is the input of the P-type diffusion layer 5 −15
In the range of up to +15 (V), the reverse bias is always applied, and no current flows. As a result, even if such a wiring 6 is connected to the MIS type transistor monitor 1, it does not affect the characteristic measurement. In the PN junction between the diffusion layer 5 and the semiconductor substrate 10,
In order to keep the breakdown voltage at 30 (V) or higher, it is necessary to consider the P-type impurity concentration of the diffusion layer 5.

Next, based on the schematic sectional view of FIG. 3, a specific example of the MIS type transistor monitor of the present invention (part 2).
Will be explained. That is, MI in the specific example (part 2)
The S-type transistor monitor 1 is of a P-channel type formed on a semiconductor substrate 10 of mainly N-type.

This MIS type transistor monitor 1 is
High-concentration P-type diffusion layer 2 ″ provided on the semiconductor substrate 10
Source electrode 2 connected to and high-concentration P-type diffusion layer 3 ″
A drain electrode 3 connected to the gate and a gate connected via an insulating layer 4 ′ such as a silicon oxide film formed on the semiconductor substrate 10 between the high-concentration P-type diffusion layers 2 ″ and 3 ″. In addition to the electrode 4, the wiring 6 for connecting the N-type diffusion layer 5 in the P-type well 5 ′ provided in the semiconductor substrate 10 and the gate electrode 4 is provided.

Further, in the same manner as the specific example (No. 1), in the wiring 6, in order to let the charge-up charges shown in FIG. 1 escape to the semiconductor substrate 10 as soon as possible, a metal material made of aluminum or the like having a smaller propagation delay than polycrystalline silicon. To use.

With such a structure, even if a charge-up occurs in the MIS type transistor monitor 1, the charge-up charge is injected into the insulating layer 4 ', and before the charge-up charge is injected into the insulating layer 4', the semiconductor substrate is provided via the wiring 6. It becomes a state of escaping to 10, and it becomes possible to prevent injection of charge-up charges to the insulating layer 4 ′. That is, it is possible to prevent the potential shift in the MIS type transistor monitor 1 which is apt to be charged up due to the so-called antenna effect, and it is possible to match the characteristics of the MIS type transistor monitor 1 and the MIS type transistor as a product.

When the characteristics are measured using this MIS type transistor monitor 1, the semiconductor substrate 10 is grounded (GND) and the gate electrode 4 is, for example, -1.
With a voltage of 5 to +15 (V) applied, the current and voltage characteristics between the source electrode 2 and the drain electrode 3 are measured.

When the characteristics are measured, the voltage of −15 to +15 (V) is applied to the wiring 6 as well. But,
In the contact portion of the wiring 6 with the semiconductor substrate 10, the N-type diffusion layer 5, the P-type well 5 ′ and the P-type well 5 ′ in the PNP structure of the N-type semiconductor substrate 10 have a floating structure. -1 in N type diffusion layer 5
Even if a voltage of 5 to +15 (V) is applied, a built-in voltage (0.5) between the N type diffusion layer 5 and the P type well 5 '.
(About V), this NP junction is always reverse biased. As a result, no current flows from the wiring 6 to the semiconductor substrate 10, and the MIS transistor monitor 1
Even if such a wiring 6 is connected to, the characteristic measurement can be normally performed.

In the present embodiment, an example in which the wiring 6 mainly connected to the gate electrode 4 is brought into contact with the diffusion layer 5 provided on the semiconductor substrate 10 has been described, but the present invention is not limited to this. May be contacted to the connection. For example, the wiring 6 may be connected to the gate wiring of the MIS type transistor as a product to release the charge-up charge.

Further, in this embodiment, the N type semiconductor substrate 10 is used.
Although the example in which the N-channel type and the P-channel type MIS transistor monitor 1 is configured by using is shown, the same applies to the case where the P-type semiconductor substrate 10 is used. In this case, the conductivity type of each diffusion layer may be reversed. Further, although the case where the silicon oxide film is used as the insulating layer 4 ′ is shown as an example in the present embodiment, other insulating materials are used such as a case where a silicon nitride film or both a silicon oxide film and a silicon nitride film is used. Is also the same.

[0029]

As described above, the MIS type transistor monitor of the present invention has the following effects.
That is, in the present invention, the gate electrode of the MIS type transistor monitor is connected to the wiring for releasing the charge from the outside to the insulating layer via the gate electrode. Injection can be suppressed, and the potential shift due to this charge can be prevented. This will be the product MIS
It is possible to match the characteristics of the MIS transistor and the MIS transistor monitor, and it is possible to perform product evaluation that faithfully reflects the characteristics of the MIS transistor.

[Brief description of drawings]

FIG. 1 is a conceptual diagram illustrating a MIS type transistor monitor of the present invention.

FIG. 2 is a schematic cross-sectional view (No. 1) for explaining a specific example of the MIS type transistor monitor of the present invention.

FIG. 3 is a schematic cross-sectional view (No. 2) for explaining a specific example of the MIS type transistor monitor of the present invention.

[Explanation of symbols]

 1 MIS type transistor monitor 2 source electrode 3 drain electrode 4 gate electrode 4'insulating layer 5 diffusion layer 5'well 6 wiring 10 semiconductor substrate

Claims (2)

[Claims] 1. A MIS-type transistor monitor provided in a minute area on the surface of a semiconductor substrate for measuring the characteristics of a plurality of MIS-type transistors provided in the most area on the surface of the semiconductor substrate. A wiring for discharging an electric charge from the outside to the insulating layer via the gate electrode is connected to the gate electrode provided through the insulating layer in a minute region of the semiconductor substrate. MIS type transistor monitor. 2. The MIS type transistor monitor according to claim 1, wherein the wiring connected to the gate electrode is made of a metal material.