JPH098122A - Method for manufacturing semiconductor device - Google Patents

Abstract

(57) [Abstract] [Purpose] In a method of manufacturing a semiconductor device in which a field shield element is separated, etching damage received on a semiconductor substrate is reduced, and an etching residue of a polycrystalline silicon film is prevented from occurring when a gate electrode is patterned. . [Structure] A polycrystalline silicon film 3 and a silicon dioxide film 4 are patterned, and sidewalls 8 of this pattern are formed.
To form The central polycrystalline silicon film 3 pattern portion where the transistor is formed is removed by etching until the semiconductor substrate 1 is exposed, and the concave portion 3 surrounded by the sidewall 8 is formed.
0 is formed, and the gate oxide film 12 of the transistor is formed in the recess 30. The semiconductor substrate 1 need only be etched once when forming the sidewalls, and the polycrystal silicon film is buried in the recesses 30 to form the gate electrode, so that no etching residue of the polycrystal silicon film occurs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device in which element isolation is performed by a field shield element isolation structure.

[0002]

2. Description of the Related Art In recent years, an element isolation technique called a field shield method has been adopted as "Fully planarized 0.5 μm technolo".
gies for 16Mb DRAM "(IEDM-88, pp246-) etc. This field shield element isolation technology is
In this technique, a shield electrode is formed in the field region via an insulating film and the potential of the shield electrode is fixed to cut off the potential of the parasitic MOS transistor.

A method of manufacturing an N-type MOS transistor using the conventional field shield element isolation technique will be described below with reference to FIGS. 4 and 5 which are sectional views showing the manufacturing process.

First, as shown in FIG. 4A, in order to adjust the threshold voltage of the MOS transistor formed in the active region (active region) and the threshold voltage of the parasitic MOS transistor in the field region, Boron ions are dosed 1 × to the P-type semiconductor substrate (silicon substrate) 101.
About 10 ¹² ions / cm ^{2 is} ion-implanted to form the impurity diffusion layer 102.
To form Then, a film having a thickness of 50 n is formed on the semiconductor substrate 101 having the impurity diffusion layer 102 formed thereon by a thermal oxidation method.
A shield gate oxide film 103 of about m is formed. Further, a phosphorus-doped film thickness of 200 n to serve as a shield electrode
After a polycrystalline silicon film (shield electrode) 104 having a thickness of about m is formed, a film thickness of 30 is formed on the polycrystalline silicon film 104.
A silicon dioxide film (silicon oxide film) 105 having a thickness of 0 to 400 nm is formed by the CVD method. Then, a photoresist 106 is applied on the entire surface and patterned so that it remains only in the field region. Thereafter, the silicon dioxide film 105 and the polycrystalline silicon film 104 are selectively removed by dry etching using the patterned photoresist 106 as a mask.

Next, as shown in FIG. 4B, a silicon dioxide film having a film thickness of about 100 to 300 nm is formed on the entire surface by the CVD method, and the silicon dioxide film is etched back by dry etching. Shield electrode 1
Sidewalls 119 are formed on both sides of 04. This etch back removes the shield gate oxide film 103 in the active region. Then, thermal oxidation is performed to form the gate oxide film 107 on the semiconductor substrate 101 in the active region. Then, phosphorus-doped polycrystalline silicon film (gate electrode) 10 having a thickness of about 200 nm
8 is formed, and a silicon dioxide film 109 having a film thickness of about 300 to 400 nm is formed on the polycrystalline silicon film 108 by the CVD method. After that, the pattern of the polycrystalline silicon film 108 and the silicon dioxide film 109 is left only in the active region by dry etching using a photoresist (not shown), and the gate electrode 108 is formed. After that, the gate electrode 108 and the sidewall 1
With the 19 and the shield electrode 104 as a mask, the phosphorus ion dose is about 1 × 10 ¹³ ions / cm ^{2 of the} semiconductor substrate 101.
Then, the LDD diffusion layer 111 is formed by ion implantation.

Next, as shown in FIG.
After forming a silicon dioxide film of about 0 to 300 nm by the CVD method, the silicon dioxide film is etched by dry etching to form sidewalls 112 on both sides of the gate electrode 108. By this etch back, the gate oxide film 107 between the two sidewalls 112 and 119 is removed.

Next, as shown in FIG.
Polycrystalline silicon film 1 serving as a conductive layer for drain extraction
13 is formed on the entire surface by a CVD method, and arsenic or phosphorus ions are ion-implanted into the semiconductor substrate 101 using the gate electrode 108, the side wall 119, the side wall 112 and the shield electrode 104 as a mask to form a high concentration source / drain diffusion layer 115. Form. This polycrystalline silicon film 113 is used to increase the alignment margin at the time of pattern formation of the source / drain diffusion layer 115 and the extraction contact and to reduce the depth of this contact.

Next, as shown in FIG. 5B, the polycrystalline silicon film 113 to be a conductive layer is patterned by anisotropic etching by photolithography using a photoresist (not shown).

Next, as shown in FIG.
After heat treatment of the drain diffusion layer 115, an interlayer insulating film 116 is formed, and a contact hole 117 reaching the polycrystalline silicon film 113 is formed in the interlayer insulating film 116.
Then, a metal wiring 118 connected to the polycrystalline silicon film 113 is patterned in the contact hole 117,
N-type MOS transistor is manufactured.

[0010]

However, the above method has the following problems. First, according to the above method, in order to completely remove the shield gate oxide film 103 and the gate oxide film 107 in each of the two steps of forming the sidewall described in FIGS. 4B and 4C, It is necessary to slightly overetch the semiconductor substrate 101. For this reason, the semiconductor substrate 101 is etched in each sidewall formation process, resulting in a total of two etching damages.

Further, according to the above method, since the step at the boundary between the element isolation region (field region) and the active region is high and steep, the gate electrode 108 is patterned at the time of patterning as shown in FIG. 4B. An etching residue 110 of the polycrystalline silicon film forming the electrode 108 may occur at the lower end portion of the sidewall 119. Such an etching residue 110 of the polycrystalline silicon film causes a short circuit defect.

That is, according to the conventional method, the semiconductor substrate 10 is
1 suffers relatively large etching damage,
There is a problem that the reliability of the semiconductor device is deteriorated because the etching residue 110 of the polycrystalline silicon film is generated.

Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device in which a field shield element is separated,
An object of the present invention is to obtain a highly-reliable and highly-integrated semiconductor device by reducing etching damage to a semiconductor substrate and preventing an etching residue of a polycrystalline silicon film when patterning a gate electrode.

[0014]

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention is such that a field shield structure formed in an element isolation region electrically connects between transistors formed in an active region. In a method of manufacturing a semiconductor device to be separated, a step of sequentially forming a first insulating film, a first conductive film, and a second insulating film on a semiconductor substrate of a first conductivity type; So that the pattern of the first conductive film remains in the element isolation region,
A step of selectively removing the second insulating film and the first conductive film; and a step of introducing a second conductivity type impurity into the semiconductor substrate using the remaining first conductive film as a mask, A step of forming an impurity diffusion layer, a step of forming a third insulating film on the entire surface, and a side of the second insulating film and the first conductive film which remain by etching back the third insulating film. Forming a wall, etching away the first insulating film exposed in the active region, forming a second conductive film over the entire surface, and leaving the second insulating film in the active region The second conductive film formed above, and the second insulating film, the first conductive film, and the first insulating film remaining in the active region are removed by etching, and the second conductive film in the active region is removed. Surrounded by sidewalls A portion of the semiconductor substrate exposed, and a step of forming a fourth insulating film to be a gate insulating film of the transistor on a portion of the semiconductor substrate surrounded by the sidewalls. In the third
And a step of etching back the third conductive film to form a gate electrode of the transistor made of the third conductive film in a portion of the active region surrounded by the sidewalls. Have and.

In one aspect of the present invention, the step of forming the impurity diffusion layer of the transistor is performed by an oblique ion implantation method.

In one aspect of the present invention, after the fourth insulating film is formed, impurities of the first conductivity type are ion-implanted into the semiconductor substrate, and the semiconductor substrate surface below the fourth insulating film is implanted. The method further includes the step of forming a channel region.

In one aspect of the present invention, after the sidewall is formed, a second conductivity type impurity is introduced into the semiconductor substrate by using the remaining first conductive film and the sidewall as a mask, and the transistor is formed. The method further includes the step of forming the high-concentration impurity diffusion layer.

In one aspect of the present invention, in the step of exposing the semiconductor substrate, the second conductive film formed on the second insulating film remaining in the active region is removed by etching, The second insulating film remaining in the active region is removed by etching using the remaining second conductive film as a mask.

[0019]

According to the present invention, since the sidewalls of the shield electrode and the gate electrode can be formed in one etch back step, the etching damage to the semiconductor substrate in the sidewall formation step can be reduced.
Further, since the gate electrode is formed by burying the polycrystalline silicon film in the portion surrounded by the sidewall of the active region,
It is possible to prevent a short circuit between the gate electrodes without causing an etching residue of the polycrystalline silicon film when the gate electrodes are formed. Therefore, a highly reliable semiconductor device can be obtained.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS.

First, as shown in FIG. 1A, the specific resistance 1
A film thickness of 50 to 100 is formed on the P-type semiconductor substrate (silicon substrate) 1 containing boron of about 12 Ωcm by a thermal oxidation method.
Shield gate oxide film (silicon dioxide film) of about nm
Form 2 Furthermore, phosphorus ions are added to 2 × 10 ^{20 to} 6 ×
Film thickness of 100-200 nm containing about 10 ²⁰ atoms / cm ³
After forming a polycrystal silicon film (shield electrode) 3 to a degree, a film thickness of 150 to 300 is formed on the polycrystal silicon film 3.
A silicon dioxide film (silicon oxide film) 4 having a thickness of about
It is formed by the VD method.

Then, a photoresist 5 is applied on the entire surface so that only a part of the field region and the active region is left, that is, only the part corresponding to the source / drain region of the MOS transistor formed later is removed. Patterning so that

Next, as shown in FIG. 1B, with the patterned photoresist 5 as a mask, the silicon dioxide film 4 is selectively removed by anisotropic etching, and then the photoresist 5 is removed. Then, using the silicon dioxide film 4 as a mask, the polycrystalline silicon film 3 is selectively removed by anisotropic etching. By using the silicon dioxide film 4 instead of the photoresist 5 as an etching mask for the polycrystalline silicon film 3 as described above, the selectivity of anisotropic dry etching is improved and a good shape is obtained. By this etching, the polycrystalline silicon film 3 is processed into a shield electrode shape.

After that, 4 is applied to the surface of the semiconductor substrate 1.
Phosphorus ions 6 are accelerated with an acceleration energy of 60 to 100 keV and a dose of 1 × 10 ^{13 to} 5 × 10 from a direction inclined by about 5 °.
Ions are implanted into the semiconductor substrate 1 under the condition of about ¹³ ions / cm ² . Then, the semiconductor substrate 1 is rotated by 180 ° and the same ion implantation is performed to form a low-concentration impurity diffusion layer 7 to be an LDD (Lightly Doped Drain) diffusion layer.

Next, as shown in FIG. 1C, a silicon dioxide film having a film thickness of about 150 to 200 nm is formed on the entire surface by the CVD method, and the silicon dioxide film is etched by anisotropic dry etching. Backing is performed to form sidewalls 8 on both sides of the polycrystalline silicon film 3 and the silicon dioxide film 4. By this etch back, the polycrystalline silicon film 3 in the active region and the shield gate oxide film 2 other than the lower part of the sidewall 8 are removed.

Thereafter, a polycrystalline silicon film 9 having a film thickness of about 150 to 200 nm to be a conductive layer for source / drain extraction is formed on the entire surface by a CVD method, and arsenic ions or phosphorus ions are accelerated at an energy of 60 to 100 keV and a dose amount. Ion implantation is performed under the conditions of 5 × 10 ^{15 to} 5 × 10 ¹⁶ ions / cm ² . By this ion implantation, the polycrystalline silicon film 9
Impurities are introduced into and the high-concentration impurity diffusion layer 10 serving as the source / drain of the MOS transistor is formed. The polycrystalline silicon film 9 is used to increase the alignment margin at the time of pattern formation of the impurity diffusion layer 10 serving as the source / drain and the lead-out contact to be formed later, and to reduce the depth of this contact.

After that, a photoresist 11 is applied on the entire surface, and then the photoresist 11 is processed into a pattern having an opening on the polycrystalline silicon film 3 in the active region. Then, the polycrystalline silicon film 9 is selectively removed by etching using the photoresist 11 as a mask.

Next, as shown in FIG. 2A, the polycrystalline silicon film 9 remaining after the photoresist 11 is removed.
Using the as a mask, the exposed silicon dioxide film 4 is removed by etching to form a recess 30 in the portion of the active region sandwiched by the sidewalls 8.

Next, as shown in FIG. 2B, the recess 30 is formed.
Etching is performed until the polycrystalline silicon film 3 therein is removed. By this etching, the upper portion of the polycrystalline silicon film 9 is also etched at the same time. Note that etching may be performed until the polycrystalline silicon film 9 is completely removed. Then, the silicon dioxide film 2 exposed in the recess 30 is removed by etching.

Next, as shown in FIG.
The recess 30 is formed by thermal oxidation at 850 ° C. for about 30 to 90 minutes.
A gate oxide film 12 having a film thickness of about 10 to 20 nm is formed on the semiconductor substrate 1 therein. By this thermal oxidation, the upper portion of the remaining polycrystalline silicon film 9 is also oxidized at the same time, and the silicon dioxide film 13 is formed on the surface thereof.

Then, the boron ions for adjusting the threshold voltage of the MOS transistor are accelerated with energy of 80 to 20.
Ions are implanted through the gate oxide film 12 under the conditions of 0 keV and a dose of about 1 × 10 ¹³ to 1 × 10 ¹⁴ ions / cm ² .
By this ion implantation, the channel region 15 is formed under the gate oxide film 12 by self-alignment.

Next, as shown in FIG. 3A, a polycrystalline silicon film having a film thickness of about 500 to 1000 nm containing about 2 × 10 ^{20 to} 6 × 10 ²⁰ atoms / cm ^{3 of} phosphorus or arsenic is formed by CVD. Then, the polycrystalline silicon film is etched back to form the gate electrode 16 of the MOS transistor in the recess 30.

Next, as shown in FIG. 3B, after the impurity diffusion layers 7 and 10 are activated by heat treatment, an interlayer insulating film 17 is formed and reaches the polycrystalline silicon film 9. Contact holes 18 are formed in this interlayer insulating film 17 and silicon dioxide film 13. Then, the metal wiring 19 connected to the polycrystalline silicon film 9 is patterned in the contact hole 18 to manufacture an N-type MOS transistor having a diffusion layer having an LDD structure.

Although one embodiment of the present invention has been described above, the present invention can be applied to the manufacture of all semiconductor devices having a field shield element isolation structure.

[0035]

According to the present invention, since the sidewalls of the shield electrode and the gate electrode can be formed by one etching back step, the etching damage of the semiconductor substrate in the sidewall forming step can be reduced. . Further, since the gate electrode is formed by burying the polycrystalline silicon film in the portion surrounded by the sidewalls of the active region, the polycrystalline silicon film is not left unetched when the gate electrode is formed, and the gate electrode is not formed. Short circuit can be prevented. Therefore, a highly reliable semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 2 is a cross-sectional view showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

3A to 3D are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps.

FIG. 5 is a cross-sectional view showing a conventional method for manufacturing a semiconductor device in the order of steps.

[Explanation of symbols]

1 semiconductor substrate 2 shield gate oxide film (silicon dioxide film) 3 polycrystalline silicon film (shield electrode) 4 silicon dioxide film (silicon oxide film) 7, 10 impurity diffusion layer 8 sidewall 9 polycrystalline silicon film (source / drain extraction) Conductive layer) 12 gate oxide film 15 channel region 16 gate electrode 30 recess

Claims (5)

[Claims] 1. A method of manufacturing a semiconductor device, wherein a transistor formed in an active region is electrically isolated by a field shield structure formed in an element isolation region, comprising: a first conductive type semiconductor substrate; A step of sequentially forming an insulating film, a first conductive film, and a second insulating film; and the first part of the active region and the element isolation region.
Selectively removing the second insulating film and the first conductive film so that the pattern of the conductive film is left, and using the remaining first conductive film as a mask, a second film is formed on the semiconductor substrate. A step of introducing a conductivity type impurity to form an impurity diffusion layer of the transistor; a step of forming a third insulating film on the entire surface; and a step of etching back the third insulating film to leave the remaining second
Forming an insulating film and a sidewall of the first conductive film, and removing the first insulating film exposed in the active region by etching; forming a second conductive film over the entire surface; The second conductive film formed on the second insulating film remaining in the active region, the second insulating film remaining in the active region, the first conductive film, and the first conductive film. Etching the insulating film to expose the semiconductor substrate in a portion of the active region surrounded by the sidewalls; and forming the transistor on the semiconductor substrate in a portion of the active region surrounded by the sidewalls. Forming a fourth insulating film to be a gate insulating film, forming a third conductive film on the entire surface, etching back the third conductive film, and forming the sidewall of the active region. The method of manufacturing a semiconductor device characterized by a step of forming a gate electrode of the transistor in a portion surrounded by comprising the third conductive film. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of forming the impurity diffusion layer of the transistor is performed by an oblique ion implantation method. 3. The first insulating film after forming the fourth insulating film
3. The method further comprising the step of ion-implanting a conductive type impurity into the semiconductor substrate to form a channel region on the surface of the semiconductor substrate below the fourth insulating film.
A method of manufacturing a semiconductor device according to item 1. 4. A high-concentration impurity diffusion layer of the transistor, wherein after the formation of the sidewall, a second conductivity type impurity is introduced into the semiconductor substrate using the remaining first conductive film and the sidewall as a mask. The method for manufacturing a semiconductor device according to claim 1, further comprising a step of forming. 5. In the step of exposing the semiconductor substrate, the second conductive film formed on the second insulating film remaining in the active region is removed by etching, and then the remaining second conductive film is removed. The method for manufacturing a semiconductor device according to claim 1, wherein the second insulating film remaining in the active region is removed by etching using the conductive film as a mask.