JPH0981501A - Digital processing device and DMA controller - Google Patents

Abstract

(57) [Abstract] [Purpose] To realize an automobile microcomputer MC capable of efficiently monitoring access to a built-in RAM in real time. As a result, functional tests of automobile microcomputers are made efficient and the product development period is shortened. [Structure] In an automobile microcomputer MC or the like having a built-in RAM and DMA controller DMAC,
A monitor address register MAR for designating an address to be monitored in RAM to the DMA controller DMAC,
A monitor start-up circuit MSTC for recognizing that writing has been performed to a designated address and starting a write data transfer operation is provided, and the DMA controller holds a transfer source address register SAR and transfer source address pointers SAP1 to SAPn. RAM based on contents
And a function of reloading the transfer source address or the initial value of the transfer source address pointer to the transfer source address register SAR when the transfer operation of a predetermined number of monitor data is completed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital processing device and a DMA controller (in this specification, a direct memory access controller is abbreviated as a DMA controller), for example, a RAM (in this specification, a random access memory is a RAM). (Hereinafter, abbreviated as ") and a DMA controller, and a technique particularly effective for use in improving the efficiency of the functional test thereof.

[0002]

2. Description of the Related Art A stored program type central processing unit and a ROM (in this specification, a read only memory is a RO
There is a single-chip type microcomputer for an automobile, which has a built-in analog signal from an analog signal from various sensors, a RAM, and various sensors, and a digital signal. Microcomputer
Further, for example, a DMA controller is built-in for efficiently realizing data exchange between an external device and a RAM without going through a central processing unit.

[0003]

In recent years, the automobile microcomputers have been remarkably increased in scale and multifunction, and in the development thereof, it is possible to efficiently and accurately write, for example, a sensor input to a built-in RAM in a normal operation state. It is an important factor to shorten the product development period. In the conventional automobile microcomputer, the monitor of access to the built-in RAM is
For example, a hardware method is used in which a dedicated device having a monitor function is connected to an external bus. For example, addresses to be monitored are input via a serial port of a microcomputer, and data written at these addresses is read by a program. , A so-called software method of outputting has been adopted. However, as the speed of automobile microcomputers increases, with the former hardware method, the operation of the dedicated monitor device cannot follow the machine cycle of the automobile microcomputer, making it difficult to monitor in a normal operating state. In the latter software method, it takes a relatively long time to output the monitor data, and the real-time property is lost. As a result, it becomes difficult to efficiently and accurately perform the functional test of the automobile microcomputer, which unnecessarily lengthens the product development period.

An object of the present invention is to realize an automobile microcomputer or the like which can efficiently monitor access to a built-in RAM in real time.
Another object of the present invention is to improve the efficiency of the function test of a microcomputer for automobiles or the like having a built-in RAM and to shorten the product development period.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in an automobile microcomputer or the like having a built-in RAM and a DMA controller, the DMA controller identifies a monitor address register for designating an address to be monitored in the RAM and write data by identifying that writing has been performed at the designated address. And a monitor start-up circuit for starting the transfer operation of the RAM, the DMA controller has a function of indirectly designating the RAM address based on the contents held in the transfer source address register, and a transfer operation of a predetermined number of monitor data. The transfer source address register is provided with a function of reloading the transfer source address or the initial value of the address pointer when the processing is completed.

[0007]

According to the above-mentioned means, access to the built-in RAM can be efficiently monitored in real time while designating an arbitrary address from a monitor tool coupled to a serial port of, for example, an automobile microcomputer. As a result, it is possible to streamline the functional test of a microcomputer for an automobile or the like having a built-in RAM and DMA controller and shorten the product development period.

[0008]

1 is a block diagram of an embodiment of an automobile microcomputer MC (digital processing device) to which the present invention is applied, and FIG. 2 is a block diagram of the automobile microcomputer MC of FIG. A block diagram of an embodiment of the DMA controller DMAC included in FIG. Based on these figures, first, an outline of the configuration and operation of the automobile microcomputer MC and its DMA controller of this embodiment will be described. FIG.
The circuit elements constituting each block of the known MOSFE
T (metal oxide semiconductor type field effect transistor. In this specification, a MOSFET is a general term for an insulated gate type field effect transistor).
It is formed over one semiconductor substrate such as single crystal silicon. The DMA controller DMAC also includes a transfer source address register SAR, a transfer destination address register DAR,
Although it has four channels each including a transfer count register TCR and a channel control register CHCR, these registers are illustrated only for one channel in FIG.

In FIG. 1, the automobile microcomputer MC of this embodiment has a central processing unit CPU of a stored program system as its basic constituent element. The central processing unit CPU is coupled with the clock generation circuit CPG and the interrupt controller INTC, and also coupled with the internal bus IBUS and the peripheral bus PBUS. Of these, a crystal oscillator XTAL having a predetermined natural frequency is coupled to the clock generation circuit CPG via a pair of external terminals, and a ROM, RAM, DMA are connected to the internal bus IBUS.
The controller DMAC as well as the bus state controller BSC are coupled. Also, for the peripheral bus PBUS,
The DMA controller DMAC and the bus state controller BSC are coupled, and the analog / digital conversion circuit A / D, the timer circuit TIM and the serial communication interface SCI are coupled. The automotive microcomputer MC is further
It has an input / output port IOP. This I / O port IOP
Is connected to the DMA controller DMAC, the bus state controller BSC, the analog-digital conversion circuit A / D, the timer circuit TIM and the serial communication interface SCI on one side, and the sensor input terminal, the actuator output terminal, and the serial port on the other side. It is connected to the input / output terminal and the input / output terminal for the external bus. When the automobile microcomputer MC is in the RAM writing monitor state, various sensors for measuring engine water temperature, air flow rate, etc. are coupled to the sensor input terminal, as will be described later. Further, a control device for adjusting a fuel injection amount or the like is connected to the actuator output terminal, and a predetermined monitor tool is connected to the serial port input / output terminal.

Here, the clock generation circuit CPG generates a clock signal having a frequency corresponding to the natural frequency of the crystal oscillator XTAL, and supplies it to each part of the automobile microcomputer MC centered on the central processing unit CPU. Also,
The central processing unit CPU operates synchronously in accordance with the clock signal supplied from the clock generation circuit CPG, performs step operation in accordance with the control program stored in the ROM, and executes predetermined logical operation processing, and at the same time, the microcomputer MC of the automobile. Controls and controls the operation of each part. Further, the ROM is composed of a mask ROM, a flash memory, or the like, and stores a control program or fixed data necessary for the operation of the central processing unit CPU. The RAM is composed of a high-speed rewritable memory such as a static RAM, and temporarily stores the calculation result of the central processing unit CPU, sensor data input from an external sensor, and the like. The interrupt controller INTC accepts an interrupt request output from each unit of the automobile microcomputer MC,
This is accepted according to a preset priority order and transmitted to the central processing unit CPU.

On the other hand, the DMA controller DMAC supports data exchange between, for example, a built-in RAM and a memory coupled to the outside of the automobile microcomputer MC without passing through the central processing unit CPU,
The bus state controller BSC supports access to memory and the like coupled to the external bus. The analog-to-digital conversion circuit A / D converts an analog signal input from various external sensors into a digital signal of a predetermined bit, and the serial communication interface SCI is connected to an externally connected asynchronous or clock synchronous type. Supports data transfer to and from serial I / O devices. Further, the timer circuit TIM measures time according to a clock signal, and selectively generates a control pulse for driving an external actuator, for example, under a predetermined timing condition.

The DMA controller DMAC of this embodiment, as shown in FIG. 2, has an internal bus IBU.
A bus interface unit BIF coupled to S and the peripheral bus PBUS, a monitor address register MAR and a transfer source address register SA coupled to the bus interface unit BIF via the DMAC internal bus DBUS.
R, transfer destination address register DAR, transfer count register TCR, channel control register CHC
R, DMAC operation register DMOR and activation request priority control circuit DRQC are provided. Further, a register control circuit REGC coupled to these registers via a signal path (not shown) is provided, and further a register control circuit REGC, a bus interface unit BIF, and an activation control circuit DSTC coupled to the activation request priority control circuit DRQC are provided. . Transfer source address register SA
R, the transfer destination address register DAR, and the transfer number count register TCR are coupled to the transfer control circuit DTRC in the other side, and are connected to the monitor address register MAR.
Is coupled to the monitor activation circuit MSTC on the other side. This monitor start-up circuit MSTC is connected to the internal bus IBUS at the other side, and further, the start-up control circuit D
Bound to STC.

Here, the bus interface unit BIF of the DMA controller DMAC has an address register AD.
Internal bus IBUS including R and data register DTR
And the interface between the peripheral bus PBUS and the DMAC internal bus DBUS. At this time, the address register ADR holds an address for the internal bus IBUS, that is, the RAM, and the data register DTR holds, for example, write data or read data for the RAM. On the other hand, the transfer source address register SAR is
The transfer destination address register DAR holds the address of the RAM in which the data to be transferred is stored, that is, the transfer source address or the address of its address pointer, and the transfer destination address register DAR is the transfer destination address of these data or its address pointer. Holds the address of. The transfer count register TCR holds the number of data to be transferred, that is, the transfer count, and the channel control register CHCR and the DMAC operation register DMOR manage the operation mode and operation condition of each channel of the DMA controller DMAC. The transfer source address register SAR and the transfer destination address register DA
The R and the transfer number count register TCR have a function as a counter, and the held contents are automatically counted up or down. The data transfer operation using these registers is performed by the transfer control circuit DTR.
Controlled by C, writing and reading of the held contents are controlled by the register control circuit REGC.

In this embodiment, the DMA controller DMAC has a function of monitoring writing to a specified address of the built-in RAM and outputting the writing data to an external monitor tool MONT connected to the serial port. Therefore, the DMA controller DMA
C includes the monitor address register MAR and the monitor start-up circuit MSTC, and the transfer control circuit DTRC has a so-called indirect addressing function that indirectly specifies the RAM address based on the contents held in the transfer source address register SAR. . RA by DMA controller DMAC
When the write monitor of M is performed, the activation request priority control circuit DRQC asserts the activation request signal DREQ (here, for example, the activation request signal DREQ is set to the valid level is referred to as assertion, and is set to the invalid level on the contrary). This is referred to as a negate. The same shall apply hereinafter), the DMAC activation request from the monitor tool MONT is identified, and the activation request acceptance signal DRAK is asserted to indicate to the monitor tool MONT that the activation request has been accepted. Inform. The RAM write monitor operation by the DMA controller DMAC will be described in detail later.

FIG. 3 shows a connection diagram of an embodiment of the automobile microcomputer MC of FIG. 1 at the time of RAM writing monitor. Further, FIG. 4 shows a processing flow chart of the first embodiment at the time of the RAM writing monitor of the automobile microcomputer MC of FIG. 1, and FIG. 5 shows the DMA.
The conceptual diagram of one embodiment for explaining the movement of data and address at the time of RAM write monitoring of the controller DMAC is shown. Based on these figures, a concrete method of the RAM write monitor of the automobile microcomputer MC of this embodiment and its features will be described.

First, referring to FIG. 3, when the RAM write monitor by the DMA controller DMAC is performed,
The n sensors SNS1 to SNSn are coupled to the sensor input terminal of the automobile microcomputer MC, and the monitor tool MONT including a predetermined host computer is coupled to its serial port. Monitor tool MO
The output path of NT is a microcomputer for automobile MC
Is internally coupled to the channel C1 of the serial communication interface SCI and its input path is coupled to the channel C2. Monitor tool MONT
Is further coupled to the DMA controller DMAC of the automobile microcomputer MC via the activation request signal DREQ and the activation request acceptance signal DRAK.

The analog signals output from the sensors SNS1 to SNSn are, as shown in FIG. 5, analog-digital conversion circuits A / A of the automobile microcomputer MC.
After being converted into a digital signal of a predetermined bit by D, that is, sensor data SDT1 to SDTn, the peripheral bus PBU
It is stored in the corresponding addresses SDA1 to SDAn of the RAM from S through the central processing unit CPU. These addresses SDA1 to SDAn are determined and designated by a control program stored in advance in the ROM.
Further, the addresses SDA1 to SDAn are transfer source address pointers SA provided at consecutive addresses in the RAM.
Written in P1 to SAPn and designated indirectly. As is well known, the sensor data SDT1 to SDTn input from the sensors SNS1 to SNSn are important elements for confirming the function of the automobile microcomputer MC, and the fact that these sensor data can be monitored in a function test is that. It has a relatively large effect on shortening the product development period.

Next, as shown in FIG. 4, the monitor tool MONT first starts the start request signal DREQ in step ST11 before starting the RAM write monitor.
To request monitor activation to the DMA controller DMAC, and the DMA controller DMAC asserts the activation request acceptance signal DRAK in step ST21 and accepts it. After receiving the activation request acceptance signal DRAK and negating the activation request signal DREQ, the monitor tool MONT determines the start address SAP1 of the transfer source address pointer of the RAM and the transfer count n in the serial communication interface S in step ST12.
DMA controller DMA via channel C1 of CI
Input to C. In step ST22, the DMA controller DMAC writes the start address SAP1 of the transfer source address pointer to the transfer source address register SAR and reads the sensor data storage address SDA1 stored in advance in the transfer source address pointer SAP1 of the RAM based on this. , Write to the monitor address register MAR as the target address of the write monitor. After writing the transfer count n to the transfer count register TCR, the RAM write monitor state is entered. In addition,
The transfer destination address register DAR stores the sensor data SD.
The device code of the channel C2 of the serial communication interface SCI which is the transfer destination of T1 to SDTn is written.

The central processing unit CPU of the automobile microcomputer MC periodically senses the sensor data SDT1 to SDTn input from the sensors SNS1 to SNSn at a cycle of, for example, about 10 mS (milliseconds), and these sensors are sensed. Driving / controlling various actuators is selectively performed based on the result of performing a predetermined arithmetic processing on the data. Therefore, the central processing unit CPU determines in step ST31 whether or not the sense time corresponding to the cycle has elapsed, and executes the loop processing of steps ST32 to ST34 to transfer the sensor data SDT1 to SDTn of the n sensors SNS1 to SNSn to the RAM address. SDA1-S
Write to DAn.

On the other hand, the DMA controller DMAC identifies in step ST23 that writing to the RAM has been executed, and in step ST24 identifies that the address is the start address SDA1 set in the monitor address register MAR as a monitor target. .
Then, in step ST25, first the address SDA1
After the sensor data SDT1 is read from the device and output to the monitor tool MONT via the channel C2 of the serial communication interface SCI, step S
The transfer source address register SAR is counted up by T26, and the transfer number count register TCR is counted down by step ST27. Hereinafter, such a sensor data read operation is performed n times, that is, step ST.
The sensor data SDT1 to SDTn are repeated until the value held in the transfer count register TCR becomes zero at 28.
A series of read operation regarding is ended.

In the reading operation of the sensor data SDT1 to SDTn by the DMA controller DMAC, the address is stored in the transfer source address register SAR, that is, the addresses SAP1 to S of the transfer source address pointer.
It is realized by indirectly designating based on APn. At this time, the DMA controller DMAC first receives the addresses SAP1 to SAPn of the transfer source address pointers in the transfer source address register SAR, accesses the corresponding transfer source address pointers, and reads the corresponding sensor data storage addresses SDA1 to SDAn. Then, these addresses are transferred to the bus interface BIF.
Internal bus I after setting in the address register ADR of
Access the RAM via BUS to access the sensor data SD
Read T1 to SDTn. By adopting such an indirect address method, the sensor data SDT1 to SDTn stored at the distributed addresses are transferred to the transfer source address register S.
Only by counting up the AR, it is possible to read efficiently and increase the degree of freedom in selecting the address.

As described above, the automobile microcomputer MC of this embodiment has the monitor address register MAR for holding the target address of the RAM write monitor,
A DMA controller D including a monitor start-up circuit MSTC for recognizing that writing has been performed to a designated address in the RAM and activating a sensor data read operation.
The monitor tool MONT, which is equipped with a MAC and is coupled to the serial port of the automobile microcomputer MC, only needs to specify the start address SAP1 of the transfer source address pointer and the transfer count n.
The sensor data SDT1 to SDTn input from Sn can be read from the RAM and monitored in real time immediately after being written. As a result, since it is possible to realize an automobile microcomputer or the like that can efficiently monitor access to the built-in RAM in real time, the functional test of the automobile microcomputer or the like can be made efficient,
The product development period can be shortened.

FIG. 6 shows a processing flow chart of the second embodiment at the time of the RAM write monitor of the automobile microcomputer MC of FIG. Since the processing flow of this embodiment basically follows the embodiment of FIG. 4, description will be added only to portions different from this.

In FIG. 6, in step ST28, n
The DMA controller DMAC that identifies that the read operation of the individual sensor data SDT1 to SDTn has ended
Returns to step ST22 and reloads the transfer source address register SAR and the transfer number count register TCR. That is, the DMA controller DMAC
Is the transfer source address register SA at that time.
The content held in R, that is, the address value obtained by subtracting n−1 from SAPn is written in the transfer source address register SAR,
Write n to the transfer count register TCR. As a result, the transfer source address register SAR and the transfer number count register TCR are set to the sensor data SDT1 to SDT.
The DMA controller DMAC can repeat the same read operation of the sensor data SDT1 to SDTn upon receiving the write to the target address of the RAM, after being reloaded to the state before the read operation of n is started. Such a reload process is performed by the sensors SNS1 to S
Sensor data SDT1 to SDTn input from NSn
This is effective when it is desired to repeatedly monitor, and the convenience of the function test by the monitor tool MONT can be further enhanced.

The functions and effects obtained from the above embodiment are as follows. That is, (1) In an automobile microcomputer or the like having a built-in RAM and a DMA controller, the DMA controller has been written to a monitor address register that specifies an address to be monitored in the RAM and to the specified address in the RAM. By providing a monitor start-up circuit that identifies and activates the write data transfer operation,
For example, the effect that the writing of the sensor data and the like to the built-in RAM can be efficiently monitored in real time from the monitor tool connected to the serial port of the automobile microcomputer is obtained.

(2) In the above item (1), the DMA controller is provided with a function of indirectly designating the read address of the RAM based on the content held in the transfer source address register, thereby writing to the distributed address. It is possible to effectively read out a plurality of acquired sensor data and the like by using the count-up function of the transfer source address register and output them to the monitor tool. (3) In the above items (1) and (2), the DMA controller is configured to transfer the transfer source address or the initial value of the address pointer to the transfer source address register when the transfer operation of the predetermined number of monitor data is completed. By providing the reloading function, it is possible to further enhance the convenience of the functional test of the automobile microcomputer by the monitor tool. (4) RAM and DM according to the above items (1) to (3)
It is possible to obtain an effect that the functional test of a microcomputer for an automobile having a built-in A controller can be made efficient and the product development period can be shortened.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the information transfer means for monitoring the write to the RAM and outputting the write data to the outside and the name thereof are not particularly limited to the DMA controller, and the block configuration and the bus configuration of the automobile microcomputer MC are various. Embodiments can be adopted. In FIG. 2, the activation of the RAM write monitor by the DMA controller DMAC can be performed by software from, for example, the central processing unit CPU, and the activation of the sensor data read operation is also performed by, for example, the end of the transmission operation by the serial communication interface SCI. It can be done regardless of the sense time. The address of the RAM monitored by the DMA controller DMAC is
It is not limited to an address for storing sensor data from the sensor. When the automobile microcomputer includes a dedicated user break controller, the function of the monitor start-up circuit MSTC may be substituted by this user break controller. In addition, the DMA controller D
The MAC can have any number of channels,
The block configuration and the register configuration are also arbitrary.

In FIG. 3, the method of starting the RAM write monitor operation by the monitor tool MONT is not restricted by this embodiment. Further, in this embodiment, the monitor address and the like are input through the channel C1 of the serial communication interface SCI, and the channel C2 is input.
Although the sensor data is output via the, it is possible to perform both of them with one channel. Monitor tool M
The ONT can be coupled to a parallel port or external bus instead of a serial port, and the sensors SNS1 to SNSn
The combining method of can also be set arbitrarily. 4 and 6, the specific processing flow of the automobile microcomputer MC at the time of RAM writing monitor can adopt various embodiments. In FIG. 5, sensors SNS1 to SNS
The sensor data SDT1 to SDTn input from n are
It can be written to RAM via the DMA controller DMAC. Further, in this embodiment, only the transfer source address is indirectly specified, but when the transfer destination address is a plurality of addresses in the RAM, for example, the transfer destination address can also be indirectly specified. The monitoring of the access to the RAM is not particularly limited to the write operation, and its addressing is not particularly required to be based on the indirect addressing.

In the above description, the case where the invention made by the present inventor is mainly applied to the automobile microcomputer and the DMA controller thereof which are the fields of application which are the background of the invention has been described, but the invention is not limited thereto. For example, the present invention can be applied to a single unit formed as a DMA controller and various digital integrated circuits having a built-in RAM. This invention is at least RA
The present invention can be widely applied to a digital processing device incorporating M and information transfer means thereof.

[0030]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a microcomputer for an automobile or the like having a built-in RAM and a DMA controller, the DMA controller is identified as a monitor address register for designating an address to be monitored in the RAM and that writing is performed at the designated address in the RAM. A monitor start-up circuit for starting a write data transfer operation is provided, and a function of indirectly specifying a RAM address to the DMA controller based on the contents held in the transfer source address register, and transfer of a predetermined number of monitor data By giving the transfer source address register the function of reloading the transfer source address or the initial value of the address pointer when the operation is completed, for example, an arbitrary address can be selected from a monitor tool connected to a serial port of an automobile microcomputer or the like. While specifying Access to internal RAM can be monitored efficiently and in real time. As a result, it is possible to streamline the functional test of a microcomputer for an automobile or the like having a built-in RAM and DMA controller and shorten the product development period.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of an automobile microcomputer to which the present invention is applied.

FIG. 2 is a block diagram showing an embodiment of a DMA controller included in the automobile microcomputer shown in FIG.

FIG. 3 is a RAM of the automobile microcomputer shown in FIG.
FIG. 9 is a connection diagram showing an example during writing monitoring.

4 is a RAM of the automobile microcomputer shown in FIG.
It is a processing flow figure which shows the 1st Example at the time of a write monitor.

5 is a RAM of the automobile microcomputer shown in FIG. 1;
It is a conceptual diagram which shows one Example for demonstrating the movement of the data and address at the time of write-monitoring.

FIG. 6 is a RAM of the automobile microcomputer shown in FIG.
It is a processing flow figure which shows the 2nd Example at the time of write-in monitoring.

[Explanation of symbols]

MC: Automotive microcomputer, CPU: Central processing unit, CPG: Clock generation circuit, XTAL ...
... Crystal oscillator, IBUS ... Internal bus, PBUS ... Peripheral bus, INTC ... Interrupt controller, ROM ...
... Read-only memory, RAM ... Random access memory, DMAC ... DMA (direct memory access) controller, BSC ... Bus state controller, A / D ... Analog-digital conversion circuit, TIM ...
Timer circuit, SCI ... serial communication interface, IOP ... input / output port. BIF ...
... bus interface, ADR ... address register, DTR ... data register, DBUS ... DMAC
Internal bus, MSTC ... Monitor activation circuit, MAR ... Monitor address register, SAR ... Transfer source address register, DAR ... Transfer destination address register, TCR ...
Transfer count register, CHCR ... Channel control register, DMOR ... DMAC operation register, DSTC ... Startup control circuit, DRQC ...
Start request priority control circuit, DTRC ... Transfer control circuit, R
EGC ... Register control circuit. C1 to C2 ... Channel of serial communication interface, SN
S1 to SNSn ... Sensor, MONT ... Monitor tool. ST11-ST34 ... Processing step, DREQ ...
... DMAC activation request signal, DRAK ... DMAC activation request acceptance signal, SAP1 ... transfer source address pointer initial value, n ... transfer count, SDA1 ... transfer source address initial value. SAP1 to SAPn ... Transfer source address pointer,
SDA1 to SDAn ... Sensor data storage address, S
DT1 to SDTn ... Sensor data, +1 ... Count up circuit, -1 ... Count down circuit.

Claims (8)

[Claims] 1. A digital processing apparatus comprising a RAM and information transfer means formed on the same substrate, wherein writing to the RAM can be monitored by the information transfer means and the write data can be output to the outside. . 2. The information transfer means includes a transfer source address register or a transfer destination address register that is automatically counted up or down, and based on the contents held in these transfer source address register or transfer destination address register. The digital processing device according to claim 1, wherein the digital processing device is a DMA controller having a function of indirectly designating an address of a transfer source or a transfer destination. 3. The DMA controller includes a transfer count register that automatically counts down or counts up, and the transfer source address register or the transfer source address register when the data transfer for the designated transfer count is completed. 3. The digital processing device according to claim 1, having a function of reloading a transfer source address, a transfer destination address, or an initial value of an address pointer thereof to a transfer destination address register. 4. The digital processing device comprises a monitor start-up circuit for recognizing that writing to a specified address of the RAM has been executed and activating a write data transfer process by the DMA controller. 4. The digital processing device according to claim 1, claim 2 or claim 3. 5. The digital processing device is an automobile microcomputer, and the write data to the RAM includes sensor data obtained by converting an analog signal input from the sensor into a digital signal. The digital processing device according to claim 1, claim 2, claim 3, or claim 4. 6. A transfer source address register or a transfer destination address register and a transfer number count register which are automatically counted up or down,
Further, it has a function of reloading the transfer source address or the transfer destination address or the initial value of the address pointer to the transfer source address register or the transfer destination address register when the data transfer for the designated transfer number is completed. Characteristic DMA controller. 7. A transfer source address register or a transfer destination address register that is automatically counted up or down, and indirectly specifies a transfer source or transfer destination address based on the contents held in these address registers. A DMA controller having a function to perform. 8. The DMA controller is formed on the same substrate as a RAM, and indirect addressing by the transfer source address register or the transfer destination address register is used when monitoring write data to the RAM. 7. The invention according to claim 7, characterized in that
DMA controller.