JPH098272A - Solid-state imaging device - Google Patents

Abstract

(57) [Summary] [Object] To provide a solid-state imaging device capable of preventing signal propagation delay and forming with a high yield. [Structure] First region 1 having a light receiving portion for photoelectric conversion
1 and a second region 12 formed around the first region 11, and the gate electrode 7 formed in the first region 11 is provided so as to extend to the second region 12. In addition, in the solid-state imaging device in which the Al wiring 20 is formed on the gate electrode 7 in the second region 12 via the flattening insulating film 19, the thickness of the gate electrode 7 in the second region 12 is Electrode 7 in region 11 of
Formed thinner than the thickness of.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device, and more particularly to a CCD type solid-state image pickup device.

[0002]

2. Description of the Related Art FIG. 8 shows a CCD type solid-state image pickup device (hereinafter,
9 is a plan view of a main part showing an example of a CCD solid-state image pickup device), and FIG. 9 is an enlarged sectional view taken along the line AA in FIG. As shown in the figure, the CCD solid-state imaging device has a first region 11 having a light receiving portion 13 that performs photoelectric conversion and a vertical register 14 that transfers the signal charges photoelectrically converted by the light receiving portion 13.
And a second region 12 such as a scanning circuit formed around the first region 11.

On the substrate 15 in the first area 11,
Polysilicon (Poly-Si) through the gate oxide film 16
Is formed, and the gate electrode 17 is formed so as to extend from the inside of the first region 11 to the second region 12. That is, in this CCD solid-state imaging device, the gate electrode 17 is roughly divided into a portion formed in the first region 11 and a bus line portion formed in the second region 12, and in which portion Is also formed with a uniform thickness. The second area 12
The gate electrode 17 is formed on the substrate 15 via the field oxide film 18, and the aluminum (Al) wiring 20 connected to the gate electrode 17 is planarized on the gate electrode 17. Is formed through.

By the way, in the CCD solid-state image pickup device in which the gate electrode 17 is formed as described above, the vertical register 14 is used.
The drive delay of the drive waveform is the narrowest part of the gate electrode 17 in the first region 11, that is, the so-called inter-pixel part 17
It is decided by the part called a. However, the width of the inter-pixel portion 17a cannot be made too large because it determines the area of the light receiving portion 13. Therefore, conventionally, by increasing the thickness of the gate electrode 17, it is possible to suppress the propagation delay of the signal in the first region 11. ing.

[0005]

However, in the CCD solid-state imaging device described above, when the film thickness of the gate electrode is increased, as shown in the sectional view taken along the line BB in FIG. Since the step difference of the gate electrode 17 in the region 12 increases, the coverage of the Al wiring 20 is deteriorated at the step portion, and the portion a where the thickness of the Al wiring 20 is thin locally occurs, and the resistance of the Al wiring 20 increases. There is an adverse effect that the cost becomes high.

[0006] Usually, the gate electrode is the first Poly-S.
Although it is composed of an i pattern and a second Poly-Si pattern, when the film thickness of the gate electrode is increased, a film for forming a second Poly-Si pattern formed on the first Poly-Si pattern and an Al film are formed. The film thickness of the Al film for forming the wiring to be etched is increased, and the reactive ion etching (RI
Due to E), an etching residue is likely to occur when patterning. This etching residue causes a short circuit between the gate electrodes and reduces the yield of the CCD solid-state imaging device. The present invention has been made to solve the above problems, and an object of the present invention is to provide a solid-state imaging device that can prevent signal propagation delay and can be formed with high yield.

[0007]

The present inventor has obtained the following findings as a result of extensive studies to achieve the above object. Normal,
Since the polysilicon film for forming the gate electrode formed in the solid-state imaging device is deposited by the CVD method, the film thickness is uniform, and thus the thickness of the gate electrode is also uniform, but from the viewpoint of the operation of the solid-state imaging device. Therefore, the thickness of the gate electrode does not necessarily have to be uniform. And based on such knowledge, the present invention was completed. That is, according to the present invention, the gate formed in the first region is composed of the first region having the light receiving portion for performing photoelectric conversion and the second region formed around the first region. In the solid-state imaging device in which the electrode is provided to extend to the second region and the wiring is formed on the gate electrode in the second region via the insulating film, the thickness of the gate electrode in the second region Is formed thinner than the thickness of the gate electrode in the first region.

[0008]

According to the solid-state image pickup device of the present invention, the thickness of the gate electrode in the second region is smaller than the thickness of the gate electrode in the first region. Even if the thickness of the gate electrode in the first region is increased to suppress the propagation delay, the increase in the step of the gate electrode in the second region can be suppressed. Further, since the increase in the step of the gate electrode in the second region is suppressed,
The gate electrode has a first Poly-Si pattern and a second Poly-Si pattern.
In the case of the Si pattern, the first in the second region
Since the increase in the step of the Poly-Si pattern of is suppressed,
An increase in the film thickness of the second Poly-Si pattern forming film or the wiring forming film formed on the upper layer to be etched is suppressed.

[0009]

Embodiments of the solid-state image pickup device of the present invention will be described below with reference to the drawings. In the CCD type solid-state image pickup device of the present embodiment (hereinafter referred to as CCD solid-state image pickup device), the gate electrode formed in this device has the same planar structure as in FIG. The structure of the A line arrow cross section is
This is different from the conventional one as shown in the side sectional view of the main part of FIG.
That is, the CCD solid-state image pickup device of the present embodiment is similar to the conventional one shown in FIG.
Vertical register 1 for transferring the signal charges photoelectrically converted in 3
4 and a second region 12 such as a bus line portion formed around the first region 11 and the like.

On the substrate 15 in the first area 11,
As shown in FIG. 1, a gate electrode 7 of polysilicon (Poly-Si), which is a feature of the present invention, is formed via a gate oxide film 16 having a film thickness of, for example, about 50 nm or less.
The gate electrode 7 is formed so as to extend from the inside of the first region 11 to the second region 12, and the second region 12 is formed.
The gate electrode 7 has a thickness smaller than that of the gate electrode 7 in the first region 11. In the present embodiment, the thickness of the gate electrode 7 in the first region 11 is formed to such an extent that the propagation delay of the drive waveform of the vertical register 14 is suppressed, for example, about 800 nm, and therefore the gate electrode in the second region 12 is formed. 7 is 800
The thickness is thinner than nm, for example, about 300 nm.

The gate electrode 7 in the second region 12 is formed on the substrate 15 via the field oxide film 18 having a thickness of about 600 m, and as shown in FIG. The aluminum (Al) wiring 2 connected to the gate electrode 7 in the second region 12 is connected to the gate electrode 7.
0 is formed via the planarization insulating film 19.

In the above CCD solid-state imaging device, when the gate electrode 7 is formed, the gate oxide film 16 is formed on the surface of the first region 11 and the field oxide film 18 is formed on the surface of the second region 12 in advance. First, as shown in FIG. 3, a first Poly-Si film 71 is formed on the entire surface of the substrate 15 by a CVD method, for example, as shown in FIG. Then, the second step shown in FIG. 4 is performed. That is,
By photolithography and etching, the first Po
The ly-Si film 71 is patterned into a desired shape to obtain a Poly-Si pattern 72 as shown in FIG.

Next, as a third step, a resist film is formed on the gate oxide film 16 and the field oxide film 18 in a state of covering the Poly-Si pattern 72, and the resist film is patterned by photolithography, as shown in FIG. As shown in, a thick film Poly-Si pattern 72 covers a necessary portion,
That is, in this embodiment, a resist pattern 73 that covers the Poly-Si pattern 72 in the first region 11 is formed. Then, as a fourth step, the Poly-Si pattern 72 in the second region 12 is etched back to a desired thickness by etching using the resist pattern 73 as a mask to obtain the gate electrode 7, as shown in FIG. Although not shown, an insulating film and a second Poly-Si film are formed so as to cover the subsequently obtained pattern, and photolithography,
The second Poly-Si film is patterned into a desired shape by etching, and then, as shown in FIG. 5, a thick Poly-Si film is formed.
The second poly-Si film is etched back to a desired thickness by etching, covering a required portion of the Si pattern.

CC in which the gate electrode 7 is formed in this way
In the D solid-state imaging device, since the thickness of the gate electrode 7 in the second region 12 is smaller than the thickness of the gate electrode 7 in the first region 11, the vertical register 1
Even if the thickness of the gate electrode 7 in the first region 11 is increased to suppress the propagation delay of the driving waveform of No. 4, the increase in the step of the gate electrode 7 in the second region 12 is suppressed as shown in FIG. . As a result, the Al wiring 20 has good coverage even in the step portion b of the gate electrode 7 in the second region 12, so that the resistance increase of the Al wiring 20 can be prevented.

Further, the gate electrode 7 in the first region 11
Since the increase in the step of the gate electrode 7 in the second region 12 is suppressed even if the thickness of the second Poly 12 is increased, the second Poly formed on the pattern of the first Poly-Si film in the second step. The increase in the film thickness of the Si film to be etched and the film thickness of the Al film for forming the Al wiring 20 to be etched is suppressed. Therefore, when patterning these, an etching residue is less likely to occur, and a short circuit between the gate electrodes 7 due to the etching residue is prevented, so that the yield can be improved. Therefore, the CCD of this embodiment
According to the solid-state imaging device, the yield can be improved without affecting the characteristics of the device, and the signal propagation speed can be increased.

In this embodiment, the side surface portion 7a of the gate electrode 7 in the second region 12 is formed substantially vertically as shown in FIG. 7A, but it is shown in FIG. 7B. As shown, the side surface portion 7a may be formed in a tapered shape that becomes lower toward the substrate 15 side. Such a gate electrode 7 is
For example, it can be formed by changing the etching conditions at the time of etching back the Poly-Si pattern 72 in the fourth step of the method of forming the gate electrode 7 described above.

The side surface portion 7 of the gate electrode 7 in the second region 12
When a is formed in a tapered shape, the side surface portion 7a of the gate electrode 7 is formed.
Is not formed in a taper shape (see FIG. 7A), the film thickness t of the Al film 20 to be etched and the second Poly-Si film to be etched (not shown) are to be etched. Since the film thickness is reduced, the Al film 20 and the second Poly-S
It is possible to further prevent the occurrence of etching residue when patterning the i film. Further, in the above embodiment, the second region in the present invention is the bus line portion, but it goes without saying that it may be a horizontal register portion or the like as long as it is a region formed around the first region. .

[0018]

As described above, according to the solid-state imaging device of the present invention, the thickness of the gate electrode in the second region is
Since the gate electrode is formed thinner than the thickness of the gate electrode in the first region and the increase in the step of the gate electrode in the second region is suppressed, the wiring with good coverage is formed even in the step of the gate electrode in the second region. It will be formed. Therefore, it is possible to prevent the increase in the resistance of the wiring while suppressing the signal propagation delay in the gate electrode in the first region. Further, since the step difference of the gate electrode in the second region is suppressed, when the gate electrode is composed of the first Poly-Si pattern and the second Poly-Si pattern, the second Poly-Si pattern forming Since it is possible to suppress an increase in the film thickness of the film or the wiring forming film to be etched, it is possible to prevent the occurrence of etching residue when patterning these. Therefore, according to the solid-state imaging device of the present invention, the yield can be improved without affecting the characteristics of the device, and the signal propagation speed can be increased.

[Brief description of drawings]

FIG. 1 is a side sectional view of an essential part showing an embodiment of a solid-state imaging device of the present invention.

FIG. 2 is a sectional view taken along line XX in FIG.

FIG. 3 is a perspective view of a main part for explaining a first step of a method for forming a gate electrode in an example.

FIG. 4 is a perspective view of a main part for explaining a second step of the method of forming the gate electrode in the example.

FIG. 5 is a perspective view of a main part for explaining a third step of the method for forming the gate electrode in the example.

FIG. 6 is a perspective view of a principal part for explaining a fourth step of the method of forming the gate electrode in the example.

FIG. 7 is a side sectional view of a main part for explaining a change in film thickness to be etched, where (a) shows a case where the side surface of the gate electrode is not tapered, and (b) shows a side surface part of the gate electrode. It shows the case where the taper is formed.

FIG. 8 is a main part plan view showing a schematic configuration of an example of a CCD solid-state imaging device.

9 is a cross-sectional view taken along the line AA in FIG.

10 is a cross-sectional view taken along the line BB in FIG.

[Explanation of symbols]

 7 Gate Electrode 7a Side Surface 11 First Region 12 Second Region 13 Photoreceptor 19 Flattening Insulating Film 20 Al Wiring

Claims (2)

[Claims] 1. A gate formed in the first region, which is composed of a first region having a light receiving portion for performing photoelectric conversion and a second region formed around the first region. In the solid-state imaging device, wherein an electrode is provided extending to the second region, and a wiring is formed on the gate electrode in the second region via an insulating film, in the second region. The thickness of the gate electrode is the first
The solid-state imaging device is formed to be thinner than the thickness of the gate electrode in the region. 2. The solid-state imaging device according to claim 1, wherein a side surface of the gate electrode in the second region is tapered.