JPH0982967A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor deviceInfo
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- JPH0982967A JPH0982967A JP23253795A JP23253795A JPH0982967A JP H0982967 A JPH0982967 A JP H0982967A JP 23253795 A JP23253795 A JP 23253795A JP 23253795 A JP23253795 A JP 23253795A JP H0982967 A JPH0982967 A JP H0982967A
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Abstract
(57)【要約】
【課題】 透明絶縁性基板の耐熱温度による、IV族半導
体膜成膜時のプロセス温度の上限制限を解消する。
【解決手段】 金属ホイール等の耐熱基板上に、a−S
i膜や多結晶Si膜等のIV族半導体膜や絶縁膜等の複数
の膜を形成し、この後、積層膜の上にガラス基板や樹脂
製透明基板等の透明絶縁性基板を貼り付け、上記積層膜
から耐熱基板を除去し、その除去面に各種加工を施して
半導体装置を製造する。即ち、本発明では、耐熱基板上
にて、IV族半導体膜や絶縁膜の形成で要求される比較的
高温による熱処理を完了させる。これにより透明絶縁性
基板の耐熱温度によるプロセス温度の上限制限が解消さ
れ、成膜方法の選択の自由度が拡大する。特に多結晶S
i膜を成膜する場合において、従来レーザーアニール法
を採用しなければならなかった工程が単純な熱CVD法
で済むようになる。
(57) Abstract: To solve the upper limit of the process temperature at the time of forming a group IV semiconductor film due to the heat resistant temperature of a transparent insulating substrate. SOLUTION: On a heat resistant substrate such as a metal wheel, aS
Forming a plurality of films such as an i film and a group IV semiconductor film such as a polycrystalline Si film and an insulating film, and then pasting a transparent insulating substrate such as a glass substrate or a resin transparent substrate on the laminated film, The heat resistant substrate is removed from the laminated film, and the removed surface is subjected to various processes to manufacture a semiconductor device. That is, in the present invention, the heat treatment at the relatively high temperature required for forming the group IV semiconductor film or the insulating film is completed on the heat resistant substrate. As a result, the upper limit of the process temperature due to the heat resistant temperature of the transparent insulating substrate is eliminated, and the degree of freedom in selecting the film forming method is expanded. Especially polycrystalline S
When the i film is formed, a simple thermal CVD method can be used for the process that conventionally requires the laser annealing method.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、例えば液晶表示装
置における画素部スイッチング素子や駆動回路部素子等
の、透明な絶縁性基板を用いてなる半導体装置の製造方
法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device using a transparent insulating substrate, such as a pixel switching element and a driving circuit element in a liquid crystal display device.
【0002】[0002]
【従来の技術】通常、液晶表示装置の画素部や駆動回路
部に組み込まれる半導体装置の基板にはガラスが用いら
れる。このため半導体装置は、製造上のプロセス温度の
上限ががガラスの耐熱温度により制限され、低温プロセ
スで製造することが要求される。また近年、液晶表示装
置の大画面化(ガラス基板の大面積化)により、低温プ
ロセスの要求はいっそう高まる傾向を呈している。2. Description of the Related Art Generally, glass is used for a substrate of a semiconductor device incorporated in a pixel portion or a drive circuit portion of a liquid crystal display device. Therefore, the semiconductor device is required to be manufactured by a low temperature process because the upper limit of the manufacturing process temperature is limited by the heat resistant temperature of glass. In recent years, the demand for low-temperature processes has tended to increase with the increase in screen size of liquid crystal display devices (increasing the area of glass substrates).
【0003】しかしながら、このようなプロセス温度の
制約は、液晶表示装置に搭載されるトランジスタの移動
度、信頼性の向上を阻む要素となるばかりか、ガラス基
板上に多結晶Si膜を形成するにあたり、単純な熱CV
D法に代えてレーザアニール法を用いねばならないな
ど、プロセスの複雑化を招く。However, such a restriction on the process temperature is not only an obstacle to the improvement of the mobility and reliability of the transistor mounted in the liquid crystal display device, but also the formation of the polycrystalline Si film on the glass substrate. , Simple thermal CV
The laser annealing method must be used instead of the D method, which causes the process to be complicated.
【0004】また、液晶表示装置の大型化に伴う重量的
な要求から、半導体装置の基板としてガラスよりもさら
に軽量な樹脂製基板を用いることが望まれている。しか
し、樹脂製基板はガラスよりも耐熱性が劣るため、プロ
セス温度はガラス基板以上に厳しく制限され、いっそう
複雑な製造プロセスが要求される。Further, from the weight requirement accompanying the increase in size of liquid crystal display devices, it is desired to use a resin substrate which is lighter than glass as a substrate of a semiconductor device. However, since the resin substrate is inferior in heat resistance to glass, the process temperature is more strictly limited than that of the glass substrate, and a more complicated manufacturing process is required.
【0005】[0005]
【発明が解決しようとする課題】このように、半導体装
置の透明絶縁性基板としてガラス基板や樹脂製透明基板
を用いると、そのガラス基板や樹脂製透明基板の耐熱温
度によりプロセス温度が制限され、この結果、半導体装
置の高性能化、プロセスの複雑化を招くと言う問題があ
った。Thus, when a glass substrate or a resin transparent substrate is used as the transparent insulating substrate of the semiconductor device, the process temperature is limited by the heat resistant temperature of the glass substrate or the resin transparent substrate, As a result, there is a problem that the performance of the semiconductor device is increased and the process is complicated.
【0006】本発明はこのような課題を解決するための
もので、半導体装置の絶縁性透明基板としてガラス基板
や樹脂製透明基板等の耐熱性に劣るものを用いても、IV
族半導体膜の成膜に際してプロセス温度の上限制限を受
けずに高性能な半導体装置を得ることのできる半導体装
置の製造方法の提供を目的としている。The present invention is intended to solve such problems, and even if an insulating transparent substrate of a semiconductor device, such as a glass substrate or a resin transparent substrate, having poor heat resistance is used, IV
An object of the present invention is to provide a method of manufacturing a semiconductor device, which can obtain a high-performance semiconductor device without being subject to an upper limit of a process temperature when forming a group semiconductor film.
【0007】[0007]
【課題を解決するための手段】本発明は上記目的を達成
するために、耐熱基板上に、IV族半導体膜を含む複数の
膜を形成し、この後、積層膜の上に透明絶縁性基板を貼
り付けると共に積層膜から耐熱基板を除去し、その基板
除去面に機能素子を形成するための各種加工を施して半
導体装置を製造するというものである。In order to achieve the above object, the present invention forms a plurality of films including a group IV semiconductor film on a heat resistant substrate, and thereafter forms a transparent insulating substrate on the laminated film. Is attached, the heat-resistant substrate is removed from the laminated film, and various processes for forming a functional element are performed on the substrate removal surface to manufacture a semiconductor device.
【0008】即ち、本発明においては、耐熱基板上に
て、IV族半導体膜や絶縁膜の形成で要求される比較的高
温による熱処理を完了させるので、透明絶縁性基板の耐
熱温度による、IV族半導体膜を含む各種成膜時のプロセ
ス温度の上限制限が解消される。よって、成膜方法の選
択の自由度が拡大し、特にIV族半導体膜として多結晶S
i膜を成膜する場合において、従来はレーザーアニール
法を採用しなければならなかった工程が単純な熱CVD
法で済むようになる。That is, in the present invention, since the heat treatment at a relatively high temperature required for the formation of the group IV semiconductor film or the insulating film is completed on the heat resistant substrate, the group IV heat resistance depending on the heat resistant temperature of the transparent insulating substrate is used. The upper limit of the process temperature at the time of various film formation including a semiconductor film is solved. Therefore, the degree of freedom in selecting the film forming method is expanded, and particularly, as a group IV semiconductor film, polycrystalline S
In the case of forming an i film, the conventional process that had to use the laser annealing method is simple thermal CVD.
The law will do.
【0009】また、透明絶縁性基板の耐熱温度による成
膜時のプロセス温度の上限制限が解消されたことで、半
導体装置の基板としてガラス基板よりもさらに耐熱温度
の低い樹脂製透明基板を用いることが可能になる。Since the upper limit of the process temperature at the time of film formation due to the heat resistant temperature of the transparent insulating substrate has been eliminated, a resin transparent substrate having a heat resistant temperature lower than that of the glass substrate is used as the substrate of the semiconductor device. Will be possible.
【0010】また、Alからなる耐熱基板を用いた場
合、該Al基板を部分的に除去(薄膜化して)すること
によって、残存するAlを配線層として利用することが
できる。 さらに、IV族半導体膜例えば多結晶Si膜の
成膜前に、Al2 O3 、MgO、CaF2 の中から選ば
れる少なくとも1つの材料からなる半導体下地膜を成膜
することで、多結晶Si膜を比較的低温で得ることが可
能になる。When a heat-resistant substrate made of Al is used, the remaining Al can be used as a wiring layer by partially removing (thinning) the Al substrate. Further, before forming the IV group semiconductor film, for example, the polycrystalline Si film, a semiconductor underlayer film made of at least one material selected from Al 2 O 3 , MgO, and CaF 2 is formed to form the polycrystalline Si film. It allows the membrane to be obtained at relatively low temperatures.
【0011】IV族半導体は、Si、Ge、C等の半導
体、或いはSiGe、SiC等の化合物半導体等であっ
てもよい。The group IV semiconductor may be a semiconductor such as Si, Ge or C, or a compound semiconductor such as SiGe or SiC.
【0012】[0012]
【発明の実施の形態】以下、本発明の実施の形態を図面
に基づいて説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0013】図1は本発明にかかる半導体装置の製造方
法の一部を説明するための工程順模式図である。FIG. 1 is a schematic diagram in order of steps for explaining a part of the method for manufacturing a semiconductor device according to the present invention.
【0014】同図において、1はロール状に巻き付けら
れた金属ホイールである。ロール部より引き出された金
属ホイール1は、該金属ホイール1の一主面に例えばS
iO2 、a(アモルファス)−Si、Al等の各種成膜
を行う複数の蒸着工程、及びこれら蒸着工程によって形
成された積層膜上に例えばガラス基板、有機透明基板等
の絶縁性透明基板2を圧着する工程を経て、図示しない
後段の例えば金属ホイール除去工程及びトランジスタ形
成工程に移される。ここで採られる蒸着法は化学蒸着
(CVD)、物理蒸着(PVD)など、目的とその成膜
材質に応じて選択される。なお、図1では絶縁性透明基
板2として有機透明基板ホイールを用いた場合を示して
いる。In the figure, 1 is a metal wheel wound in a roll shape. The metal wheel 1 pulled out from the roll portion has, for example, S
A plurality of vapor deposition steps for forming various films of iO 2 , a (amorphous) -Si, Al, etc., and an insulating transparent substrate 2 such as a glass substrate or an organic transparent substrate on the laminated film formed by these vapor deposition steps. After the pressure-bonding process, the process is transferred to a subsequent stage (not shown) such as a metal wheel removing process and a transistor forming process. The vapor deposition method adopted here is chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like, and is selected according to the purpose and the film forming material. Note that FIG. 1 shows a case where an organic transparent substrate wheel is used as the insulating transparent substrate 2.
【0015】次に図2及び図3を参照して、本発明に係
る第1の実施形態であるMOSトランジスタの製造方法
について説明する。Next, with reference to FIGS. 2 and 3, a method of manufacturing a MOS transistor according to the first embodiment of the present invention will be described.
【0016】本例では、金属ホイールとして厚さ25μm
のAlホイール11を用いた。まず、図2(a)に示す
ように、Alホイール11上に、厚さ 100nmのSiO
2 絶縁膜12、厚さ 200nmのSiN絶縁膜13、厚さ
100nmのSiO2 絶縁膜14、厚さ50nmのa−Si
膜15、厚さ 200nmのSiO2 絶縁膜16、そして厚
さ 200nmのAl膜17を順次蒸着した。蒸着法とし
て、Alについてはスパッタ法を、それ以外はブラズマ
CVD法を採用した。また、各蒸着工程におけるAlホ
イール11の加熱は、該Alホイール11の裏面に対向
配置したヒータ(加熱ランプ)を用いてすべて 250℃で
行った。この 250℃の温度は、従来よりガラス基板上に
トランジスタを形成する際の温度とほぼ同じである。続
いて、Al膜17の上にエポキシ系樹脂からなる接着剤
18を用いて厚さ O.8mmのアクリル基板19を貼り付
けた。In this example, the thickness of the metal wheel is 25 μm.
Al wheel 11 of was used. First, as shown in FIG. 2A, a 100 nm thick SiO film was formed on the Al wheel 11.
2 Insulating film 12, 200nm thick SiN insulating film 13, thickness
100 nm SiO 2 insulating film 14, 50 nm thick a-Si
A film 15, a 200 nm thick SiO 2 insulating film 16 and a 200 nm thick Al film 17 were sequentially deposited. As the vapor deposition method, a sputtering method was used for Al, and a plasma CVD method was used for other cases. In addition, the heating of the Al wheel 11 in each vapor deposition step was performed at 250 ° C. using a heater (heating lamp) arranged opposite to the back surface of the Al wheel 11. The temperature of 250 ° C. is almost the same as the temperature when forming a transistor on a glass substrate conventionally. Subsequently, an acrylic substrate 19 having a thickness of 0.8 mm was attached onto the Al film 17 by using an adhesive 18 made of epoxy resin.
【0017】その後、酢酸を主成分とする溶液を用いて
Alホイール11を全面エッチング除去し、そのAl除
去面に、再びAlを厚さ 800nmでスパッタ蒸着して、
MOSトランジスタのゲート電極となるべきAl膜20
を形成した(図2(b))。この際、Alホイール11
をそのまま薄膜化し、これを配線層として利用するよう
にしてもよい。After that, the Al wheel 11 is entirely removed by etching using a solution containing acetic acid as a main component, and Al is sputter-deposited again to a thickness of 800 nm on the Al-removed surface.
Al film 20 to be a gate electrode of a MOS transistor
Was formed (FIG. 2B). At this time, the Al wheel 11
May be thinned as it is and used as a wiring layer.
【0018】なお、図2(b〜d)及び図3において、
SiO2 絶縁膜12、SiN絶縁膜13及びSiO2 絶
縁膜14は表記上一つの層として符号12+13+14
で示し、また接着層18及びアクリル基板19も表記上
一つの層として符号18+19で示している。2 (b-d) and FIG.
The SiO 2 insulating film 12, the SiN insulating film 13, and the SiO 2 insulating film 14 are notated as one layer and are denoted by reference numerals 12 + 13 + 14
In addition, the adhesive layer 18 and the acrylic substrate 19 are also indicated by reference numeral 18 + 19 as one layer for description.
【0019】次いで、図2(c)に示すように、MOS
トランジスタのソース、ドレイン、ゲートの各領域を残
すように、写真食刻法によって上からAl膜20、三層
絶縁膜12+13+14、a−Si膜15、SiO2 絶
縁膜16、Al膜17を順次エッチング加工した。この
後、図2(d)に示すように、ゲート領域にレジストを
残してゲート領域以外のAl膜20を除去し、残ったA
l膜20、17の表面に化学的酸化によりアルミナ21
を形成した。Then, as shown in FIG.
The Al film 20, the three-layer insulating film 12 + 13 + 14, the a-Si film 15, the SiO 2 insulating film 16, and the Al film 17 are sequentially etched from above by photolithography so as to leave the source, drain, and gate regions of the transistor. processed. Thereafter, as shown in FIG. 2D, the Al film 20 other than the gate region is removed by leaving the resist in the gate region, and the remaining A
Alumina 21 is formed on the surface of the film 20, 17 by chemical oxidation
Was formed.
【0020】その後、残ったAl膜20をマスクとして
用いて三層絶縁膜12+13+14をa−Si膜15が
露出するようにRIE法でエッチングし(SiO2 及び
SiNのエッチング条件ではAl及びアルミナはほとん
どエッチングされない。)、エッチング後、全面に厚さ
200nmのn型a−Si膜22を 120℃のプラズマ蒸着
法により形成した(図2(e))。After that, the remaining Al film 20 is used as a mask to etch the three-layer insulating film 12 + 13 + 14 by RIE so that the a-Si film 15 is exposed (under the etching conditions of SiO 2 and SiN, Al and alumina are almost Not etched.), Thickness after etching
A 200 nm n-type a-Si film 22 was formed by a plasma deposition method at 120 ° C. (FIG. 2E).
【0021】次に、再び写真食刻法により、ソース・ド
レイン領域にn型a−Si膜22が残るようにn型a−
Si膜22をエッチングし、続いてスピンコート法でポ
リイミド系樹脂23及びスピンコートSiO2 (SO
G)膜24を順次厚さ 800nmで全面塗布形成し、さら
にレジストを塗布した。該レジストを写真加工した後、
フッ酸溶液でSOG膜24をエッチングする。このエッ
チングにおいてRIE法を用いても構わない。次にポリ
イミド樹脂23をエッチング加工した。そしてSF6 を
含むガスでゲート領域に露出したアルミナ21を除去し
た後、SOG膜24上のレジストを除去した(図2
(f))。この状態で、MOSトランジスタのゲート電
極となるAl膜20とn型a−Si膜22が、ポリイミ
ド樹脂23及びSOG膜24の開口部25より露出して
いる。Next, the n-type a-Si film 22 is left in the source / drain regions by photolithography again.
The Si film 22 is etched, and subsequently the polyimide resin 23 and the spin-coated SiO 2 (SO
G) A film 24 was sequentially coated on the entire surface to a thickness of 800 nm, and a resist was further coated. After photoprocessing the resist,
The SOG film 24 is etched with a hydrofluoric acid solution. The RIE method may be used in this etching. Next, the polyimide resin 23 was etched. Then, after removing the alumina 21 exposed in the gate region with a gas containing SF 6 , the resist on the SOG film 24 is removed (FIG. 2).
(F)). In this state, the Al film 20 and the n-type a-Si film 22 which will be the gate electrode of the MOS transistor are exposed through the openings 25 of the polyimide resin 23 and the SOG film 24.
【0022】続いて、SOG膜24をフッ酸溶液で全て
除去した後、厚さ50nmのTiN膜26をスパッタ蒸着
し、最後に厚さ 800nmのAl膜27を写真食刻法によ
り形成した(図2(g))。以上により、絶縁性透明基
板としてアクリル基板19を用いたMOSトランジスタ
を完成させた。Subsequently, the SOG film 24 is completely removed with a hydrofluoric acid solution, a TiN film 26 having a thickness of 50 nm is sputter-deposited, and finally an Al film 27 having a thickness of 800 nm is formed by a photolithography method (see FIG. 2 (g)). As described above, the MOS transistor using the acrylic substrate 19 as the insulating transparent substrate was completed.
【0023】この半導体装置において、素子特性に影響
するa−Si膜15とゲート絶緑膜14との界面は、ガ
ラス基板上に形成される場合と同じ温度条件の下で作ら
れているので、ガラス基板上に形成されたトランジスタ
と同じ素子特性及び信頼性が確保されたものとなる。ま
た、この完成したガラス基板を液晶表示装置のアレイ基
板として採用することで、コスト低減、1m角以上の大
面積液晶表示装置等を提供することができる。In this semiconductor device, the interface between the a-Si film 15 and the gate insulating film 14, which affects the element characteristics, is formed under the same temperature condition as when it is formed on the glass substrate. The element characteristics and reliability same as those of the transistor formed on the glass substrate are secured. Further, by using this completed glass substrate as an array substrate of a liquid crystal display device, it is possible to provide a large area liquid crystal display device of 1 m square or more with reduced cost.
【0024】次に、本発明に係る第2の実施形態である
MOSトランジスタの製造方法について図4及び図5を
用いて説明する。Next, a method of manufacturing a MOS transistor according to a second embodiment of the present invention will be described with reference to FIGS.
【0025】本例では、金属ホイールとして、両面に厚
さ50μmのクロムメッキ20が施された鉄ホイール31
を用いた。この鉄ホイール31の一面に厚さ 100nmの
SiO2 絶縁膜32をCVD法で成膜し、その上に厚さ
250nmのCaF2 膜33をΡVD法で蒸着した。続い
て、厚さ 100nmの多結晶Si膜34をCVD法で蒸着
した。この場合の温度は 450℃であり、CaF2 膜33
を多結晶Si膜34の下地として形成することによっ
て、SiO2 絶縁膜32上に直接同じ性質の多結晶Si
膜を得ようとした場合( 580℃)よりも低い温度で所要
の多結晶Si膜を得ることができる。もちろん、CaF
2 等の蒸着なしにより高温で多結晶Siを堆積しても本
発明の主旨を逸脱するものではない。また、CaF2 膜
の代わりにAl2 O3 膜、MgO膜を成膜しても同様の
効果が得られる。次に、多結晶Si膜34上に、厚さ 2
00nmのSiO2 絶縁膜35を蒸着し、さらにその上に
厚さ800nmのAl膜36を蒸着した(図4(a))。In this example, as a metal wheel, an iron wheel 31 having 50 μm thick chrome plating 20 on both sides is used.
Was used. A 100 nm thick SiO 2 insulating film 32 is formed on one surface of the iron wheel 31 by the CVD method, and the thickness is formed on the SiO 2 insulating film 32.
A CaF 2 film 33 having a thickness of 250 nm was deposited by the ΡVD method. Subsequently, a polycrystalline Si film 34 having a thickness of 100 nm was deposited by the CVD method. In this case, the temperature is 450 ° C., and the CaF 2 film 33
Is formed as a base of the polycrystalline Si film 34, the polycrystalline Si film of the same property is directly formed on the SiO 2 insulating film 32.
The required polycrystalline Si film can be obtained at a lower temperature than when a film is obtained (580 ° C.). Of course, CaF
It does not depart from the gist of the present invention to deposit polycrystalline Si at a high temperature without vapor deposition of 2 or the like. The same effect can be obtained by forming an Al 2 O 3 film or a MgO film instead of the CaF 2 film. Next, on the polycrystalline Si film 34, the thickness 2
A SiO 2 insulating film 35 having a thickness of 00 nm was deposited, and an Al film 36 having a thickness of 800 nm was further deposited thereon (FIG. 4A).
【0026】次いで、Al膜36の上にポリイミド樹脂
からなる接着剤37を用いてガラス基板38を貼り付
け、その後、鉄ホイール31、SiO2 絶縁膜32、C
aF2膜33を順に除去して多結晶Si膜34を露出し
た(図4(b))。Next, a glass substrate 38 is attached onto the Al film 36 by using an adhesive 37 made of a polyimide resin, and then the iron wheel 31, the SiO 2 insulating film 32, C are attached.
The aF 2 film 33 was sequentially removed to expose the polycrystalline Si film 34 (FIG. 4B).
【0027】以後の製造工程において、本例では接着剤
37としてポリイミド樹脂を用いたことから、プロセス
温度の上限は 280℃以下であることが望ましい。In the subsequent manufacturing process, since the polyimide resin is used as the adhesive 37 in this example, the upper limit of the process temperature is preferably 280 ° C. or lower.
【0028】続いて、多結晶Si膜34を島状にエッチ
ング加工し、プラズマCVD法でSiO2 絶縁膜39を
蒸着した(図4(c))。次いで、スパッタ法にてタン
タルとモリブデンの合金膜40を蒸着し、CDΕ法にて
合金層40をパターニングしてMOSトランジスタのゲ
ート電極40aを形成した(図5(d))。Subsequently, the polycrystalline Si film 34 was etched into an island shape, and a SiO 2 insulating film 39 was deposited by plasma CVD (FIG. 4 (c)). Then, an alloy film 40 of tantalum and molybdenum was vapor-deposited by the sputtering method, and the alloy layer 40 was patterned by the CD method to form a gate electrode 40a of the MOS transistor (FIG. 5D).
【0029】次にイオン注入法により、多結晶Si膜3
4に対して燐イオン41を1平方センチメートル当たり
5×1015個の割り合いでドープした。注入イオンの多
結晶Siの中での活性化は 260℃、 1.5時間の熱処理で
なされた。さらにプラズマCVD法で、厚さ 1μmのS
iO2 絶縁膜42を蒸着し、コンタクトホールを写真食
刻法で開孔した。そしてTiN膜43をスパッタ蒸着
し、最後にAl膜44を写真食刻法により形成した(図
5(e))。以上により、絶縁性透明基板としてガラス
基板38を用いたMOSトランジスタを完成させた。こ
のガラス基板を用いた液晶表示装置は、第1の実施形態
と同様の効果を及ぼすことは言うまでもない。Next, the polycrystalline Si film 3 is formed by the ion implantation method.
4 was doped with phosphorus ions 41 at a rate of 5 × 10 15 per square centimeter. Activation of implanted ions in polycrystalline Si was performed by heat treatment at 260 ° C. for 1.5 hours. Furthermore, by plasma CVD method, S of 1 μm thickness
An iO 2 insulating film 42 was vapor-deposited, and a contact hole was formed by photolithography. Then, the TiN film 43 was sputter-deposited, and finally the Al film 44 was formed by the photolithography method (FIG. 5E). As described above, the MOS transistor using the glass substrate 38 as the insulating transparent substrate was completed. It goes without saying that the liquid crystal display device using this glass substrate exerts the same effect as that of the first embodiment.
【0030】以上、本発明に係る半導体装置の製造方法
によれば、金属ホイール上にて、多結晶Si膜の膜形成
で要求される比較的高温による熱処理を完了させるの
で、ガラス基板の耐熱温度によるプロセス温度の上限制
限が解消される。よって、成膜方法の選択の自由度が拡
大し、多結晶Si膜の成膜において従来レーザーアニー
ル法を採用しなければならなかった工程が単純な熱CV
D法で済むようになる。As described above, according to the method of manufacturing a semiconductor device of the present invention, the heat treatment at the relatively high temperature required for forming the polycrystalline Si film on the metal wheel is completed, so that the heat resistant temperature of the glass substrate is increased. The upper limit of process temperature due to is eliminated. Therefore, the degree of freedom in selection of the film forming method is expanded, and the process in which the conventional laser annealing method must be adopted in forming the polycrystalline Si film is simple thermal CV.
The D method will be sufficient.
【0031】[0031]
【発明の効果】以上説明したように本発明によれば、耐
熱基板上にて、IV族半導体膜の形成で要求される比較的
高温による熱処理を完了させるので、透明絶縁性基板の
耐熱温度による、IV族半導体膜形成時のプロセス温度の
上限制限が解消される。よって、成膜方法の選択の自由
度が拡大し、特にIV族半導体膜として多結晶Si膜を成
膜する場合において、従来はレーザーアニール法を採用
しなければならなかった工程が単純な熱CVD法で済む
ようになり、また、絶縁性透明基板としてガラス基板よ
りもさらに耐熱性に劣る樹脂製透明基板を用いることが
可能になる。As described above, according to the present invention, the heat treatment at the relatively high temperature required for the formation of the group IV semiconductor film is completed on the heat resistant substrate. The upper limit of the process temperature at the time of forming the group IV semiconductor film is solved. Therefore, the degree of freedom in the selection of the film forming method is expanded, and particularly in the case of forming a polycrystalline Si film as a group IV semiconductor film, the conventional thermal annealing method is a simple thermal CVD method that requires the laser annealing method. In addition, a resin transparent substrate having heat resistance lower than that of the glass substrate can be used as the insulating transparent substrate.
【図1】本発明に係る半導体装置の製造方法の一部を説
明するための工程順模式図1A to 1C are schematic views in order of steps for explaining a part of a method for manufacturing a semiconductor device according to the present invention.
【図2】本発明に係るMOSトランジスタの製造方法を
説明するための図FIG. 2 is a diagram for explaining a method of manufacturing a MOS transistor according to the present invention.
【図3】図2に続いてMOSトランジスタの製造方法を
説明するための図FIG. 3 is a view for explaining the manufacturing method of the MOS transistor subsequent to FIG. 2;
【図4】本発明に係る他のMOSトランジスタの製造方
法を説明するための図FIG. 4 is a diagram for explaining another MOS transistor manufacturing method according to the present invention.
【図5】図4に続いてMOSトランジスタの製造方法を
説明するための図FIG. 5 is a view for explaining the manufacturing method of the MOS transistor subsequent to FIG. 4;
11……Alホイール 12、14、16……SiO2 絶縁膜 13……SiN絶縁膜 15……a−Si膜 17……Al膜 19……アクリル基板 31……鉄ホイール 32、35……SiO2 絶縁膜 33……CaF2 膜 34……多結晶Si膜 36……Al膜 38……ガラス基板11 ... Al wheel 12, 14, 16 ... SiO 2 insulating film 13 ... SiN insulating film 15 ... a-Si film 17 ... Al film 19 ... Acrylic substrate 31 ... Iron wheel 32, 35 ... SiO 2 Insulating film 33 ... CaF 2 film 34 ... Polycrystalline Si film 36 ... Al film 38 ... Glass substrate
Claims (4)
含む複数の膜を成膜する成膜工程と、 前記成膜工程で得た前記IV族半導体膜を含む積層膜の上
に透明絶縁性基板を接着する工程と、 前記積層膜から前記耐熱基板を除去する工程と、を有す
ることを特徴とする半導体装置の製造方法。1. A film forming step of forming a plurality of films containing at least a group IV semiconductor film on a heat-resistant substrate, and a transparent insulating film on the laminated film containing the group IV semiconductor film obtained in the film forming step. A method of manufacturing a semiconductor device, comprising: a step of adhering a substrate; and a step of removing the heat resistant substrate from the laminated film.
含む複数の膜を成膜する成膜工程であって、前記IV族半
導体膜の成膜前にAl2 O3 、MgO、CaF2 の中か
ら選ばれる少なくとも1つの材料からなる半導体下地膜
を成膜する工程を含む成膜工程と、 前記成膜工程で得た前記IV族半導体膜を含む積層膜の上
に透明絶縁性基板を貼り付ける工程と、 前記積層膜から前記耐熱基板及び前記半導体下地膜を各
々除去する工程と、を有することを特徴とする半導体装
置の製造方法。2. A film forming step of forming a plurality of films including at least a group IV semiconductor film on a heat-resistant substrate, wherein Al 2 O 3 , MgO and CaF 2 are formed before forming the group IV semiconductor film. A film forming step including a step of forming a semiconductor underlayer film made of at least one material selected from the above, and a transparent insulating substrate attached on the laminated film including the group IV semiconductor film obtained in the film forming step. And a step of removing the heat resistant substrate and the semiconductor underlayer film from the laminated film, respectively.
おいて、 前記IV族半導体膜が多結晶Si膜であることを特徴とす
る半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 2, wherein the group IV semiconductor film is a polycrystalline Si film.
装置の製造方法において、 前記透明絶縁性基板が樹脂製透明基板であることを特徴
とする半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein the transparent insulating substrate is a resin transparent substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23253795A JPH0982967A (en) | 1995-09-11 | 1995-09-11 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP23253795A JPH0982967A (en) | 1995-09-11 | 1995-09-11 | Method for manufacturing semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0982967A true JPH0982967A (en) | 1997-03-28 |
Family
ID=16940889
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP23253795A Pending JPH0982967A (en) | 1995-09-11 | 1995-09-11 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0982967A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000089249A (en) * | 1998-09-09 | 2000-03-31 | Sony Corp | Electro-optical device, drive substrate for electro-optical device, and manufacturing method thereof |
| JP2000111943A (en) * | 1998-09-30 | 2000-04-21 | Sony Corp | Method of manufacturing electro-optical device and method of manufacturing drive substrate for electro-optical device |
| WO2003049194A1 (en) * | 2001-12-06 | 2003-06-12 | Sharp Kabushiki Kaisha | Functional line and transistor array using it |
| CN101995493A (en) * | 2009-08-18 | 2011-03-30 | 综合测试电子系统有限公司 | An elastic unit for clamping an electronic component and extending below an electronic component receiving volume of an align fixture |
-
1995
- 1995-09-11 JP JP23253795A patent/JPH0982967A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000089249A (en) * | 1998-09-09 | 2000-03-31 | Sony Corp | Electro-optical device, drive substrate for electro-optical device, and manufacturing method thereof |
| JP2000111943A (en) * | 1998-09-30 | 2000-04-21 | Sony Corp | Method of manufacturing electro-optical device and method of manufacturing drive substrate for electro-optical device |
| WO2003049194A1 (en) * | 2001-12-06 | 2003-06-12 | Sharp Kabushiki Kaisha | Functional line and transistor array using it |
| US7339192B2 (en) | 2001-12-06 | 2008-03-04 | Sharp Kabushiki Kaisha | Function line and transistor array using the same |
| CN101995493A (en) * | 2009-08-18 | 2011-03-30 | 综合测试电子系统有限公司 | An elastic unit for clamping an electronic component and extending below an electronic component receiving volume of an align fixture |
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