JPS6042868A - Manufacturing method of amorphous silicon thin film field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an amorphous silicon thin film field effect transistor (
a-8iTPT).

Conventional Structure and Problems The a-8i TFT is expected to be applied to drive circuits for large-area display devices.

However, in the conventional a-8i TFT, the switch notching operation speed is slow, so in order to increase the operation speed, it is necessary to further shorten the effective gate length. Unfortunately, in order to improve the aperture ratio, it is necessary to miniaturize the a-3i TPT. Figure 1 shows the a-3i TFT made using the conventional manufacturing method.
FIG. In the illustrated a-3i TFT, a gate electrode 2 is formed on the surface of a glass support plate 1, and a gate insulating film 3 and an amorphous silicon layer 4 serving as an active layer are formed thereon. Then, the amorphous silicon layer 4 is selectively etched to form a pattern. On top of that, amorphous silicon is deposited and selectively etched to form a source region 6 and a drain region 6, and A4 wiring 7 is formed in each of the source region 5 and drain region 6.
．． However, in this case, when forming the Al wiring 7.8, it is necessary to precisely align it with the source region 6 and drain region 6 made of n+ amorphous silicon below. Further, the source region 6 and the drain region 6 need to be formed larger than the Al wirings 7 and 8 in consideration of mask alignment margins, and an increase in the area of the a-8i TFT is unavoidable.

Purpose of the Invention The present invention solves the above-mentioned problems and enables high integration.
An object of the present invention is to provide a method for manufacturing a -8i TFT.

Structure of the Invention The method for manufacturing an a-8i TFT of the present invention includes using a metal wiring pattern to a source region and a drain region as a mask.
A feature of this method is that the source region and drain region are formed by etching amorphous silicon.

DESCRIPTION OF EMBODIMENTS An embodiment of the method for manufacturing an a-8i TFT according to the present invention will be described in detail below with reference to the drawings.

First, as shown in FIG. 2, a gate electrode 1o is formed on the surface of the glass support plate 9. On top of that, Plazus CV D
(Chemical Vapor Deposit
The insulating coating 11, for example, silicon nitride (813N4), silicon oxide y (Si0
2), etc., and further, an amorphous silicon film 12 and an n-type amorphous silicon film 13 are sequentially formed using a plasma CVD apparatus (FIG. 3). Next, as shown in Figure 4,
N-type amorphous silicon film 13 and amorphous silicon film 12
Using the same mask, etching a, -8iTFT to make the maniacs disappear. Thereafter, the lease region wiring 14, the drain region wiring 15, and their thin wiring are formed of Al. Next, source region and drain region wiring 14.
Using 15 as a mask, the n-type amorphous silicon film 13 is etched to form a source region 16 and a drain region 17 (FIG. 6).

Effects of the Invention As is clear from the above explanation, the a-3tT of the present invention
F TQ ■ 1. To form the source region and drain region by etching the n+ amorphous silicon film using the cell core line method using the metal wiring pattern as a mask,
Compared to the conventional a-:5i TFT manufacturing method, only one mask can be produced. Therefore, in the present invention, it is possible to reduce the area of the source region and drain region of n+ amorphous silicon, making it possible to achieve high integration of TFTs.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of an a-8i TFT manufactured by a conventional manufacturing method, and FIGS. 2 to 6 are process sectional views showing an embodiment of the present invention. 9...Glass support plate, 1o...Gate electrode, 11...Insulating coating, 12...Amorphous silicon coating, 13... n+ Amorphous silicon, 14... Source region Al wiring, 16...
... Drain region Al wiring, 16 ... Source region, 17 ... Drain region 0 Name of agent Patent attorney Toshio Nakao and 1 other person Figure 1 Figure 2 Figure 0 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] A step of forming a gate electrode on a support plate at least whose surface layer is made of an insulator, and forming an insulating thin film, an amorphous silicon film to become an active layer, and a conductive non-conductive film from above the gate electrode to the support plate. a step of sequentially forming a crystalline silicon film; a step of selectively etching the amorphous silicon film and the conductive amorphous silicon film using the same mask to form island regions; selectively forming a conductive thin film on the silicon film; etching the conductive amorphous silicon film using the conductive thin film as a mask;
1. A method for manufacturing an amorphous silicon thin film field effect transistor, comprising the step of forming a source region and a drain region.