JPH0983203A - High frequency circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a bias circuit in a multi-stage circuit to reduce the chip area and to improve the performance resulting from reducing a loss in the circuit. SOLUTION: A pre-stage FET 10 (post-stage FET 11) in the multi-stage circuit is coupled with one-terminal of a bias supply line 3 whose electric length is λ/4 via a matching circuit 8 (9) and a main line 1 (2), the other terminal of the bias supply line 3 is connected to ground via a capacitor 4 in terms of high frequencies, and the bias supply line 3 is structured to be 2-layers as a capacitor structure via a dielectric film. The density of the capacitance in this capacitor structure is increased to make the reactance negligibly small in a line block sufficiently smaller than the electric wavelength λ. In this case, the 2-layered bias supply line 3 has the identical electric characteristic to that of a single-layer bias supply line used for a conventional circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bias supply circuit used at high frequencies.

[0002]

2. Description of the Related Art In high frequency circuits such as microwaves and millimeter waves, attempts have been made to reduce the size and cost by integration. However, a bias supply circuit (also referred to as “bias circuit”) generally used in an integrated circuit or the like occupies a relatively large area.

FIG. 3 shows an example of a conventional bias circuit composed of a microstrip line.

Referring to FIG. 3, the bias circuit includes a microstrip line 20 having an electrical length of λ / 4 (λ is, for example, a center frequency wavelength of a used frequency band), and a capacitor connected to one end of the microstrip line 20. 4 and a low-pass filter 5.

A bias voltage Vd supplied to the drain of a field effect transistor (hereinafter referred to as "FET") 10 through the bias circuit is applied to the bias applying point 6, and a gate of the FET 11 is applied to the bias applying point 7. A bias voltage Vg supplied via the bias circuit is applied to the.

In this bias circuit, one end of the microstrip line 20 is short-circuited at high frequency by the capacitor 4 (short-circuited to ground at high frequency).
The impedance on the side of the microstrip line 20 viewed from the side 2 is infinite. Therefore, the bias circuit does not participate in the matching state.

Further, DC is provided between the main line 1 and the main line 2.
Cut capacitor 19 is inserted, DC to the front and rear stages
(DC) bias can be applied independently.

[0008]

When actually designing the layout of the above-mentioned conventional bias circuit, in order to avoid the problem of electromagnetic interference (crosstalk), the microstrip line 20 includes the matching circuits 8 and 9 and the matching circuits 8 and 9. , FETs 10 and 11 and the like are required to be sufficiently separated. Therefore, the area occupied by each bias circuit becomes relatively large.

Further, the above-mentioned conventional bias circuits are provided in the same number as the required number of biases, and there is a problem that the ratio of the bias circuits to the total chip area is inevitably large. .

Further, since the loss is introduced by inserting the bias supply circuit, it is desired to reduce the number of bias circuits from the viewpoint of improving the performance.

Therefore, the present invention solves the above-mentioned problems of the prior art, and provides a bias circuit in a multi-stage circuit, which reduces the chip area and suppresses the loss in the circuit to improve the performance of the high frequency circuit. The purpose is to do.

[0012]

In order to achieve the above object, the present invention provides a high frequency circuit having a plurality of stages of bias supply circuits formed by using transmission lines, wherein the transmission lines are multi-layered, and Provided is a high-frequency circuit characterized by supplying a common bias to the next stage.

In the high frequency circuit according to the present invention, one end of the transmission line is short-circuited at high frequency.

Further, the high frequency circuit according to the present invention is characterized in that the electric length of the transmission line is λ / 4.

[0015]

The present invention is characterized in that the bias supply lines provided between the respective stages are multi-layered and the bias to the preceding stage and the next stage is supplied through one transmission line.

The multi-layered bias supply circuit constitutes a plate capacitor together with the conductor layers (metal wirings) of the respective layers and the dielectric film inserted therebetween. The capacitance density of this capacitor is sufficiently high (for example, the line width of metal wiring is expanded, the distance between metal wiring is reduced, or the use of a dielectric film with a large dielectric constant).
Then, the reactance of the capacitor structure in a sufficiently small line section (line section on the bias supply line) is negligibly small compared to the electrical wavelength λ.

In this case, the metal wiring layers of the multilayer bias supply line are set to the same potential in terms of high frequency, and the multilayer bias supply line can be regarded as a normal (single layer) transmission line.
Therefore, in the high frequency design, the multilayer bias supply line can be treated as a conventional transmission line, and a plurality of DC biases can be supplied.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of a bias circuit according to an embodiment of the present invention.

Referring to FIG. 1, the FET 10 at the front stage and the FET 11 at the rear stage are connected to one end of the bias supply line 3 through the matching circuit 8 and the main line 1 and the matching circuit 9 and the main line 2, respectively. .

The other end of the bias supply line 3 is short-circuited at high frequency (short-circuited to ground at high frequency) via the capacitors 4 and 4 ', respectively.

In order to explain one embodiment of the present invention in more detail, the plane structure of the bias supply line 3 is shown in FIG.
Shown in

Referring to FIG. 2A, the first wiring metal 12 and the second wiring metal 13 whose one ends are respectively connected to the main line 1 and the main line 2 have a multilayer structure. The second wiring metal 13 is formed in the upper layer of the first wiring metal 12 of the first layer so as to overlap therewith. The first wiring metal 12 and the second wiring metal 13 are connected to the main line 1
And the side opposite to the side connected to the main line 2 is connected to one terminal of the capacitors 4 and 4 ', respectively, and the other terminals of the capacitors 4 and 4'are connected to the ground.

FIG. 2B shows a cross section taken along line AB of the bias supply line whose plan view is shown in FIG.

Referring to FIG. 2B, the first wiring metal 1
The second wiring metal 13 and the second wiring metal 13 have a capacitor structure with a dielectric film 18 sandwiched therebetween.

When the capacitance per line length is sufficiently large,
The reactance of high frequency in the capacitor structure in a sufficiently small line section compared to the electrical wavelength λ (where λ is the wavelength of the central frequency of the used frequency band) becomes negligibly low. In this case, the multilayer line forming the bias supply line 3 can be regarded as having the same electrical characteristics as the single-layer line in terms of high frequency.

Therefore, if the electrical length of the bias supply line 3 is λ / 4, the impedance of the bias supply line as viewed from the main line 1 and the main line 2 side becomes infinite and does not contribute to the matching impedance.

Further, the multi-layer line also includes a DC cut capacitor, so that a DC (direct current) bias can be independently applied to the front stage and the rear stage. That is, the capacitor structure composed of the first wiring metal 12, the second wiring metal 13, and the dielectric film 18 (see FIG. 2B) interposed therebetween is the DC cut capacitor 19 shown in FIG. As shown in FIG. 1, in the present embodiment as well, from the bias application point 6 to the FET 10 in the previous stage.
A bias voltage Vd is applied to the drain of the FET via the low-pass filter 5, the bias supply line 3, the main line 1, and the matching circuit 8.
The bias voltage Vg can be applied to the gate of 1 independently of the bias voltage Vd through the low-pass filter 5 ′, the bias supply line 3, the main line 2, and the matching circuit 9.

N for which two biases need to be applied per stage
In the stage circuit (N is a predetermined positive integer), it is necessary to provide the bias supply lines equal in number to 2N in the conventional example, but in the present embodiment, the number of bias supply lines is N + 1. can do.

Therefore, in this embodiment, the total area occupied by the bias supply lines can be significantly reduced as compared with the conventional example. Therefore, the bias circuit according to this embodiment is suitable for, for example, a microwave integrated circuit (MIC).

Further, in this embodiment, since the number of bias supply lines is small, the loss (insertion loss in signal transmission) due to the insertion of the bias supply lines is reduced, and the characteristics of the entire high frequency circuit can be improved. I am trying.

As described above, the two-layer bias supply line has been described as the embodiment of the present invention. However, the present invention is not limited to the above-mentioned embodiment, and the circuits of the front stage or the rear stage are connected in parallel. If the branch is required and a plurality of biases are required, a multilayered bias supply line can be used.

The electrical length of the bias supply line is not limited to the length λ / 4 described in the above embodiment. Furthermore, the present invention is not limited to the microstrip line as the type of transmission line, and can be applied to various planar waveguides such as a coplanar line.

Although the field-effect transistor (FET) is used as the basic active element in the circuit in the embodiment of the present invention, the present invention is not particularly limited to the type of transistor. Further, a bias circuit having a configuration according to the principle of the present invention can be applied to a device other than a transistor as long as a bias is required.

[0035]

As described above, according to the present invention,
By sharing the bias supply line that occupies a relatively large area, it is possible to significantly reduce the area of the entire chip, which is suitable for integration. Further, according to the present invention, since the number of bias supply lines can be reduced, it is possible to reduce the loss due to the lines.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a configuration of a bias circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for explaining a structure of a bias supply line according to an embodiment of the present invention. (A) It is a top view of a bias supply line. FIG. 3B is a cross-sectional view of the bias supply line taken along the line AB of FIG.

FIG. 3 is a diagram for explaining a conventional bias circuit.

[Explanation of symbols]

 1, 2 Main line 3 Multilayer bias supply line 4 Capacitor 5 Low-pass filter 6, 7 Bias application point 8, 9 Matching circuit 10, 11 FET 12 First wiring metal 13 Second wiring metal 14 Bias supply line coupling point 15 High frequency Short circuit point 16 Via hole 17 Substrate 18 Dielectric film 19 DC cut capacitor 20 Bias supply line

Claims (5)

[Claims] 1. A high-frequency circuit having a plurality of stages of bias supply circuits configured by using transmission lines, wherein the transmission lines are multi-layered so that the biases of the previous stage and the next stage are shared and supplied. High frequency circuit. 2. The high frequency circuit according to claim 1, wherein one end of the transmission line is short-circuited at a high frequency. 3. The high frequency circuit according to claim 2, wherein the electrical length of the transmission line is λ / 4. 4. A first bias supply transmission line and a second bias supply transmission line, each of which is disposed in a different layer from each other, wherein the first and second bias supply transmission lines are at least one via a dielectric. And a bias supply circuit configured to supply predetermined biases from the first and second transmission lines for bias supply to the circuits of the corresponding stages, respectively. High frequency circuit. 5. A bias supply circuit including at least the first and second bias supply transmission lines has an electric characteristic equivalent to that of a single-layer bias supply transmission line in an operating frequency band. The high frequency circuit according to item 4.