JPH0983300A - Audio signal processing equipment - Google Patents

Abstract

(57) [Abstract] [PROBLEMS] To enable a function test without connecting a signal generator or a measuring instrument. SOLUTION: A signal processing means 1 for processing a digital audio signal, a data storage means 2 for storing data to be sent to a data sending means 3, and a data stored in a data storage means 2 for an input signal switching means 5. Data sending means 3 for sending, timing signal generating means 4 for supplying a timing signal for sending data to the data sending means 3 based on a synchronizing signal input from the outside, and input to the signal processing means 1. Input signal switching means 5 for switching so that the signal to be output is not the audio input signal input from the outside but the signal output from the data sending means 3.
And a data storage means 2, a timing signal generation means 4, an input signal switching means 5 and a control means 6 for controlling.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an audio signal processing device for digitally processing an audio signal and outputting it.

[0002]

2. Description of the Related Art FIG. 7 shows the configuration of a conventional audio signal processing apparatus for digitally processing an audio signal. Conventionally, a DSP (Digital Signal Processor) is used in a device for digitally processing an audio signal. The audio signal processing device has a configuration in which a plurality of DSPs 50 are arranged as shown in FIG. 7 in order to realize processing such as equalizer, filter, and mixing. When a digital audio signal is transmitted between the devices, the digital audio signal is transmitted serially between the devices, so that the digital audio signal is input / output serially to / from the DSP 50.

As described above, in the conventional audio signal processing apparatus, a plurality of DSPs are used to perform audio signal processing on a serially input digital audio signal, and the result is serially output.

[0004]

However, in the above-described conventional audio signal processing device, in order to test various functions such as an equalizer, a filter, and a mixing realized by a DSP or the like, an audio signal is input from the outside. However, it is necessary to verify that the output data is correct, and for that purpose, a signal generator for inputting signals from the outside and a measuring instrument for measuring output signals must be connected. There was a problem that the function could not be tested.

The present invention solves the above-mentioned conventional problems, and provides an audio signal processing apparatus capable of performing a function test without connecting a signal generator, a measuring instrument or the like. To aim.

[0006]

To achieve the above object, the present invention provides, as a first means, a signal processing means for digitally processing an audio signal, a data storage means for storing arbitrary data, and this data. The data transmission means for reading out the data stored in the storage means and transmitting it at a predetermined timing, and the timing signal for the data transmission means to transmit arbitrary data based on a synchronization signal input from the outside, Timing signal generating means to be supplied to the data transmitting means, and input signal switching for switching the signal input to the signal processing means to be a signal transmitted from the data transmitting means instead of an audio input signal input from the outside. Means, the input signal switching means, the data storage means, and the timing signal generating means It has a configuration with.

In order to achieve the above object, the present invention further comprises, as a second means, an output data storage means for storing an audio output signal output from the signal processing means in the first means, and this output data storage means. And a control means for controlling to read the data stored in the means.

[0008]

Therefore, according to the present invention, the first means allows the input signal switching means to input not the signal input from the outside but the arbitrary data stored in the data storage means to the signal processing means. Therefore, the function implemented by the signal processing means can be tested without connecting the signal generator to the outside and inputting the audio signal to the audio signal processing device.

Further, according to the present invention, the data output from the signal processing means in the first means can be stored and read out by the second means, so that the result processed by the signal processing means is output. The result of the function test can be verified without checking the signal by connecting a measuring device to the outside.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic block diagram of a first embodiment of the present invention. 1 is a signal processing means for digitally processing an audio signal, 2 is a data storage means for storing data to be sent to a data sending means which will be described later, 3 is data storage means 2
The data transmitting means 4 for transmitting the data stored in the input signal switching means to the later-described input signal switching means, 4 is the data transmitting means for the timing signal for the data transmitting means 3 to transmit the data based on the synchronizing signal inputted from the outside. An input signal for switching the timing signal generation means 5 to be supplied to 3 is such that the signal input to the signal processing means 1 is not the audio input signal input from the outside but the signal output from the data sending means 3. Switching means, 6 is data storage means 2
And a control means for controlling the timing signal generating means 4 and the input signal switching means 5.

FIG. 2 is a circuit block diagram of a first embodiment embodying the configuration of FIG. 1, and 10 shows digital processing for realizing functions such as an equalizer, a filter, and a volume by a DSP or a dedicated LSI. Signal processing circuit
(Corresponding to the signal processing means 1 in FIG. 1) and the input / output to / from the signal processing circuit 10 is 24-bit serial data.
Reference numeral 11 is a 24-bit register for storing 24-bit data (corresponding to the data storage means 2 in FIG. 1), and 12 is a parallel-serial converter (in FIG. 1) for converting 24-bit parallel data into serial data. Corresponding to the data transmission means 3), 13
Is a timing signal generation circuit (corresponding to the timing signal generation means 4 in FIG. 1) that generates a load clock and a shift clock to be supplied to the parallel-serial converter 12 from a bit clock and a word clock input from the outside.
A 2-to-1 selector (corresponding to the input signal switching means 5 in FIG. 1) for switching serial input data from the outside and serial data output by the parallel-serial converter 12, 15 is a switch for setting switching. It is a 1-bit register for use with, and is connected to the select terminal of the 2 to 1 selector 14. Reference numeral 17 is an L / R setting 1-bit register for setting the timing signal generating circuit 13, 16 is a CPU, and switching 1-bit registers 15 and 24
Write operation to the bit register 11 (Fig. 1
The control means 6 of FIG.
Corresponds to U16 and 1-bit register 17 for L / R setting).

Next, the circuit operation of the first embodiment will be described with reference to FIG.
This will be described with reference to the timing chart of FIG.

FIG. 5 shows a word clock, a bit clock, and audio data input from the outside, a load clock supplied from the timing signal generation circuit 13 to the parallel-serial converter 12, a shift clock, and a parallel-serial converter. 12 is a timing chart of serial data output from 12.

In the first embodiment, the word clock frequency is
48kHz, bit clock frequency is 64 word clock
The doubled frequency is 3.072 MHz, and 24-bit audio data is serially input in synchronization with these two clocks. Audio data is H (H
The format is such that the IGH) period is the audio L channel and the L (LOW) period is the audio R channel data, and 24-bit audio data is transmitted LSB first 24 clocks after 32 clocks. . The parallel-serial converter 12 is a synchronous load type parallel-serial converter 12, and the data shift operation is performed in synchronization with the rising edge of the shift clock. Therefore, by inputting the load clock and the shift clock as shown in FIG. 5 to the parallel-serial converter 12, the 24-bit data stored in the 24-bit register 11 is loaded into the parallel-serial converter 12. ,
Serial output is performed at the same timing as audio data.

Regarding the timing of the data output from the load clock, shift clock and parallel-serial converter 12 shown in FIG. 5, the L / R setting 1-bit register 17 is set so as to output the L channel data. This is an example of the case.

The output of the switching 1-bit register 15 is 2 to 1
Connected to the select terminal of the selector 14. When the select terminal of the 2to1 selector 14 is set to L, external serial input data is input to the signal processing circuit 10, and when the select terminal is set to H, serial data output from the parallel-serial converter 12 is input to the signal processing circuit 10. To be done. Therefore, the CPU 16 sets the switching 1-bit register 15 to H and writes 24-bit data to the 24-bit register 11, whereby 24-bit serial data is input to the signal processing circuit 10.

As described above, according to the first embodiment, any data written in the data storage means 2 by the control means 6 can be input to the signal processing means 1, so that a signal generator or the like is connected to the outside. It is possible to test the function without inputting an audio signal.

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 3 is a schematic block diagram of the second embodiment. The same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals and detailed description thereof will be omitted.

In FIG. 3, reference numeral 20 is an output data storage means for storing data output from the signal processing means 1, and control means 6 is an input signal switching means 5, a data storage means 2, and a timing signal generation means. In addition to controlling 4 and 4, data is read from the output data storage means 20.

FIG. 4 is a circuit block diagram in the second embodiment. The same components as those of the circuit configuration of the first embodiment shown in FIG. 2 will be assigned the same reference numerals and detailed description thereof will be omitted.

In FIG. 4, 30 is a serial-parallel converter for converting serial data output from the signal processing circuit 10 into parallel data, and 31 is parallel data output from the serial-parallel converter 30. It is a 24-bit register, and this 24-bit output data is stored in the CPU.
It can be read by 16. Reference numeral 32 is an input side L / R setting 1-bit register, which is the same as the L / R setting 1-bit register 17 shown in FIG. 2 of the first embodiment. 33
Is an output side L / R setting 1-bit register for setting which of the L channel and the R channel of the audio data output from the signal processing circuit 10 is to be stored. In addition to supplying a clock to the parallel-serial converter 12, the timing signal generation circuit 13 supplies a shift clock to the serial-parallel converter 30 and a latch clock to the 24-bit register 31, respectively. In addition,
The control means 6 of FIG. 3 includes the switching 1-bit register 15 and the CPU 16 of FIG. 4 and the input side L / R setting 1-bit register 32.
4 corresponds to the output side L / R setting 1-bit register 33, and the output data storage means 20 of FIG. 4 corresponds to the serial-parallel converter 30 and 24-bit register 31 of FIG.

Next, the circuit operation of the second embodiment will be described with reference to the timing chart of FIG.

FIG. 6 is a timing chart of audio data output from the signal processing circuit 10, a shift clock supplied to the serial-parallel converter 30, and a latch clock supplied to the 24-bit register 31.

Since the serial-parallel converter 30 performs the shift operation in synchronization with the rising edge of the shift clock,
By supplying a clock obtained by inverting the bit clock for 24 clocks, the audio data output from the signal processing circuit 10 is sequentially shifted by the serial-parallel converter 30. Since the 24-bit register 31 latches data in synchronization with the rising edge of the latch clock, it is shifted in the serial-parallel converter 30 by inputting the latch clock with the timing shown in FIG.
The 24-bit output data is stored in the 24-bit register 31. The data stored in the 24-bit register 31 is the CPU 16
Can be read by.

The timings of the shift clock and the latch clock shown in FIG. 6 are examples when the output side L / R setting 1-bit register 33 is set to store the data of the L channel.

As described above, according to the second embodiment, the data output from the signal processing means can be stored and read out by the CPU. Therefore, by comparing the data with the expected value, the measuring instrument or the like can be measured. The result of the function test can be verified without connecting and checking the output signal. Further, since the audio signal processing device alone can detect the abnormality of the hardware and the software without connecting a signal generator or a measuring device to the outside, it is possible to realize a self-determination function during system operation.

[0029]

According to the present invention having the structure described above, the input signal switching means inputs not the signal inputted from the outside but the arbitrary data stored in the data storage means to the signal processing means. Therefore, the function realized by the signal processing means can be tested without connecting an external signal generator and inputting an audio signal to the audio signal processing device.

Since the data output from the signal processing means can be stored, in addition to the above effects,
Even if you do not check the output signal by connecting an external measuring device,
It has an effect that the result of the functional test can be verified.

[Brief description of drawings]

FIG. 1 is a schematic block diagram of an audio signal processing device according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram of the audio signal processing device according to the first embodiment of the present invention.

FIG. 3 is a schematic block diagram of an audio signal processing device according to a second embodiment of the present invention.

FIG. 4 is a circuit block diagram of an audio signal processing device according to a second embodiment of the present invention.

FIG. 5 is a timing chart showing the circuit operation in the first embodiment of the present invention.

FIG. 6 is a timing chart showing the circuit operation in the second embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional audio signal processing device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Signal processing means, 2 ... Data storage means, 3 ... Data transmission means, 4 ... Timing signal generation means, 5 ... Input signal switching means, 6 ... Control means, 10 ... Signal processing circuit, 11 ... 24-bit register, 12 … Parallel-to-serial converter, 13… Timing signal generation circuit, 14… 2to
1 selector, 15 ... 1-bit register for switching, 16 ... C
PU, 17 ... 1-bit register for L / R setting, 20 ... Output data storage means, 30 ... Serial-parallel converter,
31 ... 24-bit register, 32 ... Input side L / R setting 1
Bit register, 33 ... 1-bit register for output side L / R setting, 50 ... DSP.

Claims (2)

[Claims] 1. A signal processing means for digitally processing an audio signal, a data storage means for storing arbitrary data, and a data transmission means for reading out data stored in the data storage means and transmitting it at a predetermined timing. ,
Timing signal generating means for supplying to the data transmitting means a timing signal for the data transmitting means to transmit arbitrary data based on a synchronizing signal inputted from the outside, and a signal inputted to the signal processing means Control the input signal switching means, the input signal switching means, the data storing means, and the timing signal generating means so that the signal is transmitted from the data transmitting means instead of the audio input signal input from the outside. An audio signal processing device, comprising: 2. An output data storage means for storing an audio output signal output from the signal processing means, and a control means for controlling to read the data stored in the output data storage means. The audio signal processing device according to claim 1.