JPH0983308A - Flip-flop circuit - Google Patents

Abstract

(57) [Abstract] [Purpose] In addition to the operation as a normal flip-flop circuit that inputs an input data signal and a clock signal and outputs an output data signal, even when there is no clock signal input,
The same signal as the input data signal is output as the output data signal. [Structure] Clocked gates 5, 6, 7, 8 for controlling a data signal by a clock signal, an inverter circuit 9,
10 and 11, and a clock input determination circuit 4 that determines whether or not a clock signal is input and outputs a clock signal or a control signal according to the state. When there is a clock signal input, the clock input determination circuit 4 outputs the clock signal as it is, and the flip-flop circuit normally operates.
When there is no clock signal input, the clock input determination circuit 4 outputs a control signal and the clocked gates 5, 6,
By inputting the control signal to 7 and 8, the data signal input from the data input terminal 1 is directly transmitted to the data output terminal 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-flop circuit, and more particularly to a flip-flop circuit having a data through function.

[0002]

2. Description of the Related Art A conventional flip-flop circuit is a circuit that does not operate unless a clock signal is input.

Further, a conventional flip-flop circuit having a data through function is a mode switching type having a data through function by inputting a mode switching signal (normal flip-flop operation mode or data through mode).
It is. As an example thereof, FIG.
No. 67612).

As shown in FIG. 3, the clocked gate 4
In the flip-flop circuit composed of 7, 48, 49, 50 and the inverter circuits 51, 52, the mode switching signal 44, the clock signal 42, and the clock inversion signal 43 are input, and the clock signals received by the four clocked gates are input. , The clock signal 42 by the mode switching signal 44,
The clocked gates 47 and 49 are opened and the clocked gates 48 and 5 are opened independently of the clock inversion signal 43.
A clock control circuit 46 for controlling to close 0 is provided, and has a function of data-through the input signal 41 of the flip-flop circuit to the output terminal 45 of the flip-flop circuit.

[0005]

An object of the present invention is to operate as a normal flip-flop circuit when there is a clock signal input, and to output the same signal as the input data signal even when there is no clock signal input. It is to provide a circuit that can output as a signal.

[0006]

A flip-flop circuit according to the present invention comprises a circuit for determining whether or not a clock signal is input, and a circuit for outputting a clock signal or a control signal according to the output signal in a clock signal input section. By providing the flip-flop circuit, the flip-flop circuit shares the data through function with the normal operation.

[0007]

1 is a block diagram showing a flip-flop circuit according to the present invention. In this embodiment, clocked gates 5, 6, 7, 8 for controlling data signals by clock signals are used.
And inverter circuits 9, 10, 11 and a clock input discriminating circuit 4 which determines the presence / absence of a clock signal input and outputs a clock signal or a control signal according to the state.

Next, the operation will be described. When there is a clock signal input, the clock input determination circuit 4 outputs the clock signal as it is and operates as a normal flip-flop circuit. When there is no clock signal input, the control signal is output from the clock input determination circuit 4, and the control signal is input to the clocked gates 5, 6, 7, and 8 to input the data signal input from the data input terminal 1. Is
It is directly transmitted to the data output terminal 3.

FIG. 2 is a block diagram showing an embodiment of the flip-flop circuit of the present invention. The present embodiment is a specific example of the clock input determination circuit 4 described above. The clock input determination circuit 24 includes a peak detector 25,
Comparator 26, OR circuits 27 and 29, AND circuit 2
It is composed of 8 and 30.

Next, the operation will be described. The peak detector 25 determines whether the clock signal input from the clock signal input terminal 22 has a signal component, and the comparator 26 converts the clock signal into a low / high level signal. When there is a clock signal, a high level signal is output, and when there is no clock signal, a low level signal is output. In the case of the normal flip-flop circuit shown in FIG. 4, clock signals of opposite phases should be input to the clocked gates 64, 65 and 66, 67, respectively, but in the case of the present embodiment, the clock signal input is If not, the OR circuits 27, 2
Since the high level signal is input to 9 and the low level signal is input to the AND circuits 28 and 30, the output signals of the OR circuits 27 and 29 are set to the high level, and the output signals of the AND circuits 28 and 30 are set to the low level. Clocked gate 31, 33
Is opened and the clocked gates 32 and 34 are closed, so that the data signal input from the data input terminal 21 is directly transmitted to the data output terminal 23. When there is a clock signal, a low-level signal is input to the OR circuits 27 and 29, and a high-level signal is input to the AND circuits 28 and 30, so that the clock signal does not receive any control, and each clocked gate 31, It is input to 32, 33, 34 and operates as a normal flip-flop circuit.

[0011]

By using the present invention, data can be transmitted in the flip-flop circuit even when there is no clock signal, and it can be used for both synchronous and asynchronous circuits.

[Brief description of drawings]

FIG. 1 is a block diagram of a flip-flop circuit according to the present invention.

FIG. 2 is a block diagram showing an embodiment of a flip-flop circuit of the present invention.

FIG. 3 is a block diagram of an example of a conventional example.

FIG. 4 is a block diagram of a normal flip-flop circuit.

[Explanation of symbols]

 1 ... Data signal input terminal, 2 ... Clock signal input terminal, 3 ... Output terminal, 4 ... Clock input determination circuit, 5, 6, 7, 8 ... Clocked gate, 9, 10, 11 ... Inverter circuit.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04B 10/06

Claims (4)

[Claims] 1. A flip-flop circuit which inputs an input data signal and a clock signal and outputs an output data signal, determines whether or not the clock signal is input to the input portion of the clock signal, and determines whether or not the clock signal is input. A flip-flop circuit, characterized in that by providing a circuit for outputting the clock signal or the control signal, the same signal as the input data signal is output as the output data signal when the clock signal is not input. 2. A circuit including a flip-flop for inputting an input data signal and a clock signal and outputting an output data signal, determining the presence or absence of the input of the clock signal, and depending on the state thereof, the clock signal or the control signal. A flip-flop circuit, which outputs an output data signal when there is no input of the clock signal, by providing a circuit for outputting the clock signal and a circuit for enabling the data through of the flip-flop portion by the control signal. . 3. An I incorporating any one of claims 1 and 2.
C. 4. An optical transmission module comprising any one of claims 1, 2 and 3.