JPH0983354A - Dpll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the incomplete phase adjustment that is caused by the jitters of the receiving data or the phases of the receiving data and receiving clocks. SOLUTION: A DPLL circuit counts the source clocks (× 16CLK) to generate receiving clocks, sets a signal DLY or FWD showing the phase delay or advance when the count value shows 8 to 15 or 1 to 7 at the time of detection of a receiving data changing point, and increases or decreases the full count number 16 of a counter by 1 or 2 to adjust the phases of the receiving clocks. In such a constitution, a means is added to set the delayed signal DLYLAT or FWDLAT of the signal DLY or FWD when the count value shows 8 to 10 or 5 to 7 respectively and to inhibit the signals FWD and FWDLAT via the signal DLYLAT and also to inhibit the signals DLY and DLYLAT via the signal FWDLAT respectively. Thus it is evaded to alternately repeat the plus and minus phase adjustment of the receiving clocks as long as the difference of these clock phases is large.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to D of data communication for adjusting the phase of a reception clock and synchronizing with data received from a partner having a different phase in serial data communication.
It relates to a PLL circuit.

[0002]

2. Description of the Related Art In a conventional data communication DPLL circuit, a received data and a source clock having a frequency higher than its baud rate are input and a received clock synchronized with the received data is generated. A frequency 16 times or 32 times the baud rate is normally used as the source clock, and this is counted to generate a reception clock. The phase adjustment is performed by comparing the phases of the reception data and the reception clock at each change point of the reception data and correcting the count value by 1 bit or 2 bits.

As shown in FIG. 3, a conventional DPLL circuit includes a change point detection circuit 1 for detecting a change point of received data RXD using a source clock, a synchronous binary counter 2 for counting the source clock, and a counter of this counter. When the count value, the source clock, and the change point detection signal are input, and the count value is larger or smaller than a predetermined value, a signal indicating that the clock phase is delayed or advanced is set, thereby decreasing or increasing the full count number of the counter 2. The phase adjusting circuit 3 outputs the reception clock RXC synchronized with the reception data.

A source clock 32 times the baud rate (x
The operation of the PLL circuit using 32 CLK) will be described. When the change point detection circuit 1 detects the change point of the reception data, the count value of the counter 2 is 1 to 15 (in this case, the phase of the reception clock output to the reception data is advanced). The phase adjusting circuit 3 delays the phase of the next reception clock by setting the signal FWD indicating the advance of the reception clock phase so that the full count value of the counter 2 increases to 33 or 34. On the contrary, when the change point of the received data is detected, the count value of the counter 2 is 16
In the case of .about.31 (in this case, the phase of the reception clock that is output with respect to the reception data is delayed), the phase adjustment circuit 3 causes the full count value of the counter 2 to be 31 or 3.
The signal DLY indicating the delay of the reception clock phase is set so as to be reduced to 0, and the phase of the next reception clock is advanced.
Further, when the count value is 0, the phases of the reception data and the reception clock are optimal, and therefore the phase is not corrected. As described above, the reception clock having no phase shift is output.

[0005]

In the above-mentioned conventional PLL circuit, there is a jitter in the received data and the timing at which the phase shift from the received clock becomes maximum (when the source clock is 32 times the baud rate, the count value is 15 or 16). , When the received data is received with a count value of 7 or 8) at 16 times the baud rate, the correction of the received clock may repeat positive and negative alternately at each change point of the received data, and the phase may not progress to the optimum phase. Occurs. This operation is performed with a source clock (× 16CLK) with a frequency 16 times the baud rate.
A DPLL circuit using the above will be described. The DPLL circuit is shown in FIG. 3 and its timing is shown in FIG.

This DPLL circuit is a system in which the full count number is increased to 17 when the count value of the counter 2 at the change point of the reception data RXD is 1 to 7, and the full count number is decreased to 15 when it is 8 to 15. . Received data is input as a waveform including jitter whose H level is shorter than the normal bit length. In FIG. 4, since the count value of the counter 2 at the first change point of the reception data RXD is 8, the signal DLY indicating the delay of the clock phase is set in the phase adjustment circuit 3. As a result, the full count number is reduced to 15 and the phase of the reception clock RXC is advanced. Received data RX
Since the count value at the second change point of D is 7, the signal FWD indicating the advance of the clock is set in the phase adjustment circuit 3. As a result, the full count number is increased to 17 and the clock phase is delayed. At the third change point of the reception data RXD, since the clock phase has been added and subtracted by the previous two corrections, the phase has returned to the initial phase.

As described above, when there is jitter, the correction of the third and subsequent clock phases only repeats plus and minus of the count number, and it does not proceed to the optimum phase forever. The data pattern in this case is 1,
Although 0, 1, ..., All sampled data is 0.

The present invention has been made in view of the above problems of the prior art, and an object thereof is that the phase adjustment is incomplete due to the jitter of the received data or the phase of the received data and the received clock. It is to provide a PLL circuit that does not exist.

[0009]

To achieve the above object, the present invention provides a change point detection circuit for detecting a change point of received data using a source clock, a counter for counting the source clock, and a counter for the counter. Generates the reception clock from the count value, and when the count value at the time of change point detection is larger or smaller than the value of the timing at which the phase shift becomes maximum, set a signal indicating the phase delay or advance of the reception clock and make a full count of the counter. Number is 1 bit or 2
In a DPLL circuit having a circuit for adjusting a clock phase by reducing or increasing bits, the circuit for adjusting the phase counts when the count value at the time of change point detection is larger or smaller than the value of the timing at which the phase shift becomes maximum. When the value is within a predetermined range close to the value of the timing, means for setting a delay signal of the signal indicating the phase delay or lead, and a signal indicating the phase lead by the delay signal of the signal indicating the phase delay and its A means for inhibiting the delay signal, a signal for indicating a phase delay in the delay signal of the signal for indicating the phase advance, and a means for inhibiting the delay signal are provided.

[0010]

1 shows a DPLL circuit and FIG. 2 shows its timing. In FIG. 1, reference numeral 1 is a change point detection circuit for detecting a change point of received data RXD using a source clock (× 16 CLK) 16 times the baud rate, and 2
Is a synchronous binary counter that counts the source clock, 3 is the phase adjustment circuit that inputs the count value of this counter and the source clock and the change point detection signal (DETECT), and outputs the received clock, 4 is the count value of the counter 2 It is an inverter that inverts the signal CY output from the phase adjustment circuit 3 and clears the counter 2 when the full count number is reached.

The phase adjusting circuit 3 reduces the full count number 16 of the counter 2 to 15 when the count value of the counter 2 when the change point detection signal is input from the change point detection circuit (at the change point) is 8 to 15. Means for setting the signal DLY indicating the delay of the clock, and means for setting the delay signal DLYLAT of the signal DLY until the next change point when the count value of the counter 2 is 8 to 15 and resetting it otherwise. Further, when the count value at the change point is 1 to 7, means for setting a signal FWD indicating a progress for increasing the full count number of the clock counter 2 to 17,
When the count value of the counter 2 is 5 to 7, the delay signal FWDLAT of the signal FWD is set until the next change point, and is reset otherwise, means for inhibiting the signals FWD and FWDLAT with the signal DLYLAT, and the signal FWDLAT Means for inhibiting the signals DLY and DLYLAT.

Next, the operation of this DPLL circuit will be described with reference to FIG. The change point detection circuit 1 detects a change point of the reception data RXD. Since the count value of the counter 2 at the first change point of the received signal data RXD is 8, the signals DLY and DLYLAT are set in the phase adjusting circuit 3, the full count number of the counter 2 is reduced to 15, and the count number is the full count number. When it reaches 15, the signal CY is output and the counter 2 is cleared via the inverter 4. Therefore, the phase of the next reception clock advances by one count.

The count value of the counter 2 at the time of the second change point is 7, but the delay signal DLYL is set in the phase adjusting circuit 3.
Since AT is set, signals FWD and FWDL
Since AT is inhibited and is not set, it is cleared when the count value of the counter 2 reaches the normal full count number 16.

Since the count value of the counter 2 at the time of the third change point is 9, the signals DLY and DLYLAT are set in the phase adjusting circuit 3 as in the case of the first change, and the full count number is reduced to 15 again. Therefore, the counter 2 is cleared when the count number reaches the full count number 15. As a result, the phase of the next reception clock advances by one count. Similarly, the count value at the time of the fourth and subsequent change points increases by one by 10, 11, 12, ..., And settles at 0. The counter value of the counter 2 at the change point is 11 to
When it reaches 15, the signal DLY operates in the same manner as in the conventional case.

When the count value of the counter 2 at the first change point is 7, the signals FWD and FWDLAT are set in the phase adjustment circuit 3 and the signals DLY and DLYL.
Since AT is inhibited and is not set, the full count number is increased to 17, and conversely to the above, the count value at the change point is decreased by one by 6, 5, 4, ...

[0016]

According to the present invention, since the phase adjustment can be perfectly performed, there is a case where the phase adjustment ends indefinitely due to the jitter of the received data or the phase of the received data and the received clock as in the conventional case. Disappears.

[Brief description of drawings]

FIG. 1 is a block diagram of a DPLL circuit according to an embodiment.

FIG. 2 is a timing diagram of an embodiment.

FIG. 3 is a block diagram of a DPLL circuit according to a conventional example.

FIG. 4 is a timing chart of a conventional example.

[Explanation of symbols]

 1 ... Received data change point detection circuit 2 ... Synchronous binary counter 3 ... Phase adjustment circuit RXD ... Received data RXC ... Received clock DETECT ... Received data change point detection signal DLY ... Phase delay signal DLYLAT ... Phase delay Delay signal of signal FWD ... Signal showing phase lead FWDLAT ... Delay signal of signal showing phase lead

Claims (1)

[Claims] 1. A change point detection circuit that detects a change point of received data using a source clock, a counter that counts the source clock, a reception clock that is generated from the count value of the counter, and a count when the change point is detected. When the value is larger or smaller than the value of the timing at which the phase shift becomes maximum, a signal indicating the phase delay or advance of the reception clock is set to adjust the clock phase by reducing or increasing the full count number of the counter by 1 bit or 2 bits. In a DPLL circuit having a circuit, a circuit for adjusting the phase is configured so that a count value at the time of detecting a change point is larger or smaller than a timing value at which the phase shift becomes maximum and the count value is close to the timing value. When within the range, means for setting a delay signal of the signal indicating the phase delay or lead, and this phase Means for inhibiting the signal indicating the phase advance and the signal indicating the phase advance by the delay signal indicating the phase, and the signal indicating the phase delay and indicating the phase delay by the delay signal indicating the phase advance A DPLL circuit, characterized in that means for inhibiting a delay signal of the signal is provided, and the phase adjustment of the reception clock is not alternately repeated positively and negatively while the phase difference between the reception data and the reception clock is large.