JPH0983357A - PLL circuit and digital signal reproducing device - Google Patents

Abstract

Kind Code: A1 A PLL circuit used as a reproduction clock generation circuit of a digital signal reproduction device, which is resistant to noise and has stable characteristics. SOLUTION: The comparison output of the phase comparator 3 is balanced (differential).
The signal is output in the form of a signal and supplied to the loop filter 4, and the output signal of the loop filter 4 is supplied to the control voltage input terminal of the VCO 5 in the form of a balanced signal. The in-phase component of noise included in the control voltage can be canceled. In addition, the charging and discharging currents of the loop filter capacitor flow through the transistors of the same conductivity type, and due to the difference in the element characteristics, P
It is possible to prevent the characteristics of the LL circuit from deteriorating.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a PLL circuit and a digital signal reproducing apparatus using the PLL circuit for a reproduced clock generating circuit.

[0002]

2. Description of the Related Art When a digital signal is recorded on a magnetic tape, an optical disk or the like and the digital signal is reproduced from this, a PLL circuit is used to generate a reproduction clock synchronized with the reproduction signal. The PLL circuit includes a VCO (voltage controlled oscillator), a phase comparator, and a loop filter. FIG. 4 shows an example of the configuration of the phase comparator and the loop filter of the PLL circuit. In FIG. 4, 41,
Reference numeral 42 denotes a pair of differentially connected NPN-type transistors, and the constant current source CS is connected to their common emitter connection points. The terminals 43a and 43b derived from the bases of these transistors 41 and 42 have clock signals (V
The output of the CO or the output obtained by dividing the output of the VCO) is supplied.

A transistor 44 having emitters connected to a common emitter connection point of the transistors 41 and 42 is provided, and an input signal (reference signal) is supplied to a terminal 45 derived from the base of the transistor 44. PNP transistors 46 and 47 forming a current mirror circuit are connected to the collector of the transistor 41 and the collector of the transistor 42, and the phase comparison output is taken out from the connection point of the collector of the transistor 47 and the collector of the transistor 42. That is, the current of the product output of the signals supplied to the input terminals 43 a and 43 b and the signal supplied to the input terminal 45 flows through the collectors of the transistors 41 and 42. The phase comparison output extracted from the collector connection point of the transistors 42 and 47 is extracted to the output terminal 49 via the loop filter 48 having a low-pass filter configuration. The control voltage from the output terminal 49 is used as the control voltage for the VCO.

[0004]

SUMMARY OF THE INVENTION The above-mentioned conventional PLL
The circuit is a PL that operates with a low-voltage power supply and can output high-frequency clocks as digital equipment becomes smaller and has higher performance.
The L circuit has the following problems. First, in order to operate with a low voltage power supply and generate a high frequency output, it is necessary to increase the sensitivity of the frequency change to the control voltage of the VCO. In that case, the influence when noise is mixed in the control voltage becomes large.

The second problem is that due to the difference in the conductivity type of the transistors, the transient characteristics differ between charging and discharging, and the characteristics of the PLL circuit deteriorate. In the configuration of FIG. 4 described above, current flows through the transistor 41 when the clock signal is at the high level at the terminal 43a and at the low level at the terminal 43b during the period when the reference signal is at the low level and the transistor 44 is off. The capacitor of the loop filter 48 is charged via the PNP type transistor 47. On the other hand, when 43a is low level and terminal 43b is high level, current flows through the transistor 42 and the capacitor is discharged. Therefore, the charging current is supplied from the PNP type transistor 47, and the discharging current flows through the NPN type transistor 42. Generally, P
The NP type transistor is inferior in high frequency characteristics to the NPN type transistor. Such a difference between the charge characteristic and the discharge characteristic has a problem that the capture ranges above and below the center frequency cause imbalance.

Therefore, an object of the present invention is to provide a PLL circuit which is capable of using a VCO that is resistant to noise and has high sensitivity, and which eliminates the difference in the characteristics of charging and discharging, and has excellent characteristics. .

Another object of the present invention is to provide a digital signal reproducing circuit having a PLL circuit which operates with a low voltage power supply and has good characteristics as a reproduced clock generating circuit.

[0008]

According to a first aspect of the present invention, a VCO, a phase comparator for phase-comparing an output signal of the VCO and an input signal, an output terminal of the phase comparator and a control signal input of the VCO. A PLL circuit comprising a loop filter inserted between a terminal and a terminal, wherein the output signal of the phase comparator and the output signal of the loop filter are in the form of a balanced signal.

According to a second aspect of the present invention, in a digital signal reproducing apparatus having a PLL circuit which is supplied with a reproduction signal from a recording medium and generates a reproduction clock synchronized with the reproduction signal, the PLL circuit includes a VCO and a VCO. Of the output signal of the phase comparator and a loop filter inserted between the output terminal of the phase comparator and the control signal input terminal of the VCO. The digital signal reproducing device is characterized in that the output signal of the filter is in the form of a balanced signal.

Since it is in the form of a balanced signal (differential), the in-phase component of noise is canceled and the influence of noise on the VCO can be reduced. Therefore, VC
A highly sensitive O can be used. Further, it is possible to prevent the charge characteristic and the discharge characteristic from being different from each other due to the difference in the conductive type of the transistor, and to prevent the deterioration of the characteristic of the PLL circuit.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, an input signal processing circuit 2, a phase comparator 3, a VCO 5, and a clock output buffer 6 are formed in an IC 1 surrounded by a broken line.
An input signal, for example, a reproduced digital signal from a magnetic tape is supplied from the input terminal t1, and the input signal processing circuit 2 performs processing such as waveform shaping for extracting the rising edge and the falling edge of the input signal, and phase comparison. Is supplied to the container 3.

The output signal of the VCO 5 is taken out to the output terminal t2 via the clock output buffer 6 and supplied to the phase comparator 3. The phase comparator 3 compares the phase of the output of the VCO 5 with the phase of the input signal passed through the input signal processing circuit 2 and generates a comparison output at the terminals t3 and t4. This comparison output is passed through the loop filter 4 constituted by external parts of IC1 to control voltage input terminals t5, t of VCO5.
6.

In this embodiment, the signals input / output between the circuit blocks forming the above-mentioned PLL circuit are in a balanced (differential) format. At least in the present invention, it is necessary that the output signal of the phase comparator 3 and the control voltage input terminal of the VCO 5 via the loop filter 4 are in the form of a balanced signal.

FIG. 2 shows an example of the circuit configuration of the phase comparator 3 and the loop filter 4 in one embodiment of the present invention. The phase comparator 3 is basically a transistor 1
It is composed of a multiplication circuit consisting of 1, 12, 13
A current flows in the direction of lowering the collector potential. The constant current source CS3 is connected to the common emitter connection point of the transistors 11 and 12. The output signals of the VCO 5 are supplied to the bases of the transistors 11 and 12 as balanced inputs from the terminals 14a and 14b. The emitter of the transistor 13 is further connected to the common emitter connection point, and the base of the transistor 13 is supplied with an input signal from the terminal 15. In FIG. 1, the input signal supplied from the input signal processing circuit 2 to the phase comparator 3 is in the balanced signal format, but in the example of FIG. 2, it is in the unbalanced signal format.

The collector of the transistor 11 is connected between the collector and the emitter of the PNP type transistor 14 and the power source line via the resistor R1, and the collector of the transistor 12 connects between the collector and the emitter of the PNP type transistor 15 and the resistor R2. Connected to the power supply line. The collectors of the transistors 11 and 12 are connected to the emitters of the transistors 20 and 21, respectively. The bases of the transistors 20 and 21 are commonly connected to the DC voltage source V2. The collectors of the transistors 20 and 21 and the collector of the transistor 13 are connected to the power supply line.

Further, a loop filter 4 composed of a capacitor and a resistor is connected between the collectors of the transistors 11 and 12. The loop filter 4 has a series circuit of a resistor and a capacitor connected in parallel with the resistor. The resistor in parallel with the capacitor defines the DC gain of the loop. Further, a transistor 16 in which the collector of the transistor 11 and its base are connected, and a transistor 17 in which the collector of the transistor 12 and its base are connected are provided. These transistors 16,
Seventeen collectors are connected to the power supply line. The emitters of the transistors 16 and 17 are commonly connected, and a common emitter connection point and a transistor 18 to which the emitters are connected are provided. A constant current source CS4 is connected to the common emitter connection point.
Is connected.

A direct current voltage source V1 is connected to the base of the transistor 18, and its collector is diode-connected P.
It is connected to the power supply line via the NP-type transistor 19 and the resistor R3. The base of the transistor 19 is commonly connected to the bases of the transistors 14 and 15 described above to form a current mirror circuit.

As shown in FIG. 3, the configuration of the phase comparator according to the embodiment of the present invention shown in FIG. 2 is such that the DC detector 33 is connected to the collectors of the transistors 11 and 12 to which the loop filter 4 is connected. Is connected, and the DC stopper 34 is also connected. Transistor 1
A current source CS is provided between the collectors of 1 and 12 and the power supply line.
By connecting 1 and CS2, the phase comparison output of the balanced signal can be supplied to the loop filter 4, but the DC potential is not fixed.

Therefore, the direct current detector 33 is constituted by the transistors 16, 17 and 18, and the transistors 11, 1 and
The collector potential of 2 is controlled so as not to exceed a certain level. As an initial state, consider a case where the base potential of the transistor 18 is higher than the base potentials of the transistors 16 and 17. In this state, the transistor 18 is turned on and the current I1 flows through its collector. Transistor 19,
By the current mirror composed of 14 and 15,
A current flows from the transistors 14 and 15 toward the transistors 11 and 12. Transistors 11, 12, 1
The phase detection circuit composed of 3 absorbs a current, but sets the current so that the current flowing into the transistors 14 and 15 is larger. As a result, transistor 1
The collector potentials of 1 and 12 rise while maintaining the phase difference information.

When the potential of either of the transistors 11 and 12 becomes higher than the base potential of the transistor 18, the transistor 18 is turned off. Therefore, the current in the current mirror circuit composed of the transistors 19, 14 and 15 also disappears, and the collector potential of the transistors 11 and 12 does not rise any further. Therefore, the transistor 11,
The potentials of 12 are controlled so that any one of them stops at the same potential as the base potential of the transistor 18.

Further, in order to prevent the collector potential of the transistors 11 and 12 from dropping too low and the operation of the circuit being delayed when the state is not fixed such as when the power is turned on,
A voltage stopper 34 including transistors 20 and 21 is provided. When the collector potential becomes V2-V _BE (V _BE : transistor collector-base voltage) or less, the transistors 20 and 21 are turned on, and the voltage is clipped so as not to fall below this voltage.

Note that the circuit example shown in FIG. 2 is an example, and a phase detector having a configuration other than this may be used.

The PLL circuit according to the present invention described above is used as a reproduction clock generation circuit in a digital signal reproduction circuit, for example, a digital VCR (video cassette recorder). In this case, for the phase comparator 3,
A reproduced digital signal is supplied as an input signal. Then, a signal that defines the timing of the reproduction signal processing is formed based on the reproduction clock from the PLL circuit.

[0024]

According to the present invention, since the in-phase component of noise in the phase comparison output is in the form of a balanced signal, it can be removed, and a noise-resistant configuration can be realized, and a high-sensitivity V signal can be obtained.
CO can be used, and a PLL circuit suitable for a low power supply voltage can be configured.

Further, according to the present invention, the current passes through the transistor of the same conductivity type (NPN type) when the capacitor of the loop filter is charged and when it is discharged, and the PLL circuit of the PLL circuit is changed depending on the characteristic of the element. It is possible to prevent the characteristics from being adversely affected.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a connection diagram of an example of a phase comparator and a loop filter in one embodiment of the present invention.

FIG. 3 is a simplified connection diagram of an example of a phase comparator and a loop filter according to an embodiment of the present invention.

FIG. 4 is a connection diagram of a phase comparator and a loop filter of a conventional PLL circuit.

[Explanation of symbols]

 3 Phase Comparator 4 Loop Filter 5 VCO 11, 12, 13 Transistors Constituting Phase Comparator

Claims (3)

[Claims] 1. A VCO, a phase comparator for phase comparing an output signal and an input signal of the VCO, and a loop filter inserted between an output terminal of the phase comparator and a control signal input terminal of the VCO. In the PLL circuit consisting of, the output signal of the phase comparator and the output signal of the loop filter are in the form of a balanced signal. 2. A digital signal reproducing apparatus having a PLL circuit which is supplied with a reproduction signal from a recording medium and generates a reproduction clock synchronized with the reproduction signal, wherein the PLL circuit comprises a VCO and an output signal of the VCO. It comprises a phase comparator for phase comparison with an input signal, and a loop filter inserted between the output terminal of the phase comparator and the control signal input terminal of the VCO. The output signal of the phase comparator and the loop A digital signal reproducing device characterized in that the output signal of the filter is in the form of a balanced signal. 3. The phase comparator according to claim 1 or 2, wherein the phase comparator outputs a balanced output signal to the loop filter and limits an output DC potential within a predetermined range. Characterized device.