JPH098639A - Output buffer circuit - Google Patents

Abstract

(57) [Summary] [Object] To provide an output buffer circuit capable of suppressing a shoot-through current between a power supply and a ground and reducing generation of noise. [Configuration] Output transistors 11 to 14 connected in parallel
And the output transistors 11 to 14 and 15 to 18 in a circuit in which resistors 19 to 24 are interposed between the input terminals of
Transistors 31 to 34 and 35 to 38 are connected to the input terminals of, and transistors 39 and 40 are inserted into the input terminals of the output transistors 11 and 15 of the first stage. With this configuration, when each of the output transistors 11 to 14 and 15 to 18 performs a switching operation, the input signal of the output transistor that is switched to the cutoff state is not affected by the resistance, and the input signal is not delayed, Since it operates faster than the output transistor on the side that switches to the conductive state, it is possible to prevent both of the output transistors 11 to 14 and 15 to 18 from being in the conductive state at the same time, suppress the through current, and reduce noise. .

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art In recent years, semiconductor integrated circuits have been subjected to measures for reducing noise that causes malfunctions of electronic devices and the like. However, with the power saving of electronic devices and the like, it is possible to realize circuits with lower noise. Is needed. The conventional output buffer circuit will be described below.

FIG. 4 shows a circuit diagram of a conventional output buffer circuit. In FIG. 4, V _DD is a positive power supply, V _SS is ground, 1,
2 is a first and second signal input terminal, 3 is a signal output terminal, 1
1 to 14 are P-channel MOS transistors (hereinafter "PM
15 to 18 are N channel MOS transistors (hereinafter referred to as "NMOS"), and 19 to 24 are resistors.

This conventional output buffer circuit is a PMOS
11-14 parallel circuit, NMOS15-18 parallel circuit, first signal delay circuit network composed of resistors 19-21, and second signal delay circuit network composed of resistors 22-24. It has and. The parallel circuit of the PMOSs 11 to 14 is connected between the positive power source V _DD and the signal output terminal 3, and
The parallel circuit of the OSs 15 to 18 is connected between the ground V _SS and the signal output terminal 3. The first signal delay circuit network including the resistors 19 to 21 is provided in a path from the first signal input terminal 1 to each control terminal of the PMOSs 11 to 14, and the first signal input terminal 1 to the PMOSs 11 to 14 is provided. The signal transmission time of the route to each control terminal of 14 is made different. A second signal delay circuit network composed of resistors 22 to 24 is provided from the second signal input terminal 2 to the NMOSs 15 to 18.
The signal transmission time of the path extending from the second signal input terminal 2 to the control terminals of the NMOSs 15 to 18 is different.

The operation of the conventional output buffer circuit configured as described above will be described below. First, if high-level (hereinafter referred to as "H level") signals are input to the first and second signal input terminals 1 and 2, the PMOSs 11 to 14 are cut off and are not conducted.
On the other hand, the NMOSs 15 to 18 become conductive, current flows from the signal output terminal 3 to the ground through the NMOSs 15 to 18, and the potential between the signal output terminal 3 and the ground becomes the same. As a result, a low level (hereinafter referred to as "L level") signal is output to the signal output terminal 3.

On the contrary, the first and second signal input terminals 1,
If L level signals are input to 2 respectively, N
The MOSs 15 to 18 are cut off and do not conduct. on the other hand,
The PMOS 11 to 14 become conductive, and the current is the positive power supply V
It flows from _DD to the signal output terminal 3 through the PMOSs 11 to 14, and the potential between the signal output terminal 3 and the positive power supply V _DD becomes the same. As a result, an H level signal is output to the signal output terminal 3.

In this conventional output buffer circuit, the PMO
S11 to 14 and NMOS 15 to 18 are connected in parallel,
Since the resistors (19 to 24) are provided between the respective control terminals, a signal transmitted to the control terminals of the respective transistors is delayed, a time difference is generated in the signals input to the respective transistors, and the switching of the transistors is delayed. Timing is staggered. This suppresses a sudden change in current when the input signal changes, and reduces output waveforms and noise on the power supply line generated by the sudden change in current.

[0008]

However, in the above-described conventional structure, the PMOS 11 to 14 and the NMOS 15 are affected by the switching timing difference between the transistor that receives the change of the input signal early and the transistor that receives the change of the input signal late.
There is a problem that any one of the transistors Nos. 1 to 18 is in a conductive state, which causes a through current to flow between the power supply and ground, and the through current causes noise.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an output buffer circuit capable of suppressing the through current between the power supply and the ground and reducing the generation of noise.

[0010]

According to a first aspect of the present invention, there is provided an output buffer circuit comprising a parallel circuit of a plurality of current source output transistors connected between a current source power source and a signal output terminal, and a current source power source. A parallel circuit of a plurality of current drawing output transistors connected between the signal output terminal and a first signal input provided on a path from the first signal input terminal to each control terminal of the plurality of current discharging output transistors A first signal delay circuit network that makes the signal transmission time of a path from a terminal to each control terminal of a plurality of current source output transistors different, and each control of a plurality of current source output transistors from a second signal input terminal The signal transmission time of the path provided from the second signal input terminal to each control terminal of the plurality of current drawing output transistors provided on the path to the terminal An input signal of a polarity inserted between the first signal input terminal and the start end of the first signal delay circuit for turning on the second signal delay circuit to be turned on. Is inserted between the first signal input terminal and each control terminal of the plurality of current discharging output transistors. A first simultaneous cutoff control transistor group for directly supplying an input signal having a polarity for cutting off the current discharge output transistor to the control terminals of the plurality of current discharge output transistors by bypassing the first signal delay circuit network. , An input signal having a polarity which is inserted between the second signal input terminal and the start end of the second signal delay circuit network and makes the plurality of current drawing output transistors conductive. A second sequential conduction control transistor for supplying a start of use circuitry second
A plurality of input signals having polarities that are inserted between the signal input terminal of the control circuit and the control terminals of the plurality of current drawing output transistors and cut off the plurality of current drawing output transistors by bypassing the second signal delay circuit network. And a second simultaneous cutoff control transistor group which is directly supplied to the control terminal of the current drawing output transistor.

An output buffer circuit according to a second aspect of the present invention is the output buffer circuit according to the first aspect, further comprising:
The signal delay circuit network includes a first and a second signal delay resistance circuit network, respectively. According to a third aspect of the present invention, in the output buffer circuit according to the second aspect, the plurality of current source output transistors and the plurality of current source output transistors each comprise a MOS field effect transistor, and the first signal delay circuit is provided. The resistance circuit network for use includes a first resistor film that connects between the gate electrodes of the plurality of current source output transistors, and the first resistor film is made of the same material as the gate electrodes of the plurality of current source output transistors. The second resistor circuit network for signal delay is formed of a second resistor film that connects the gate electrodes of a plurality of current drawing output transistors, and the second resistor film forms a plurality of current drawing outputs. It is formed of the same material as the gate electrode of the transistor.

[0012]

With this configuration, the first and second simultaneous interruption control transistor groups operate the first and second signal delay circuits only when the current source / current pull-in output transistors are switched to the interruption state. For bypassing the input signal without passing through it, it acts as a bypass for transmitting to the control terminal of the output transistor for current sinking and current sinking.
The time for the current drawing output transistor to switch to the cutoff state is shortened, it is possible to prevent both the current drawing output transistor and the current drawing output transistor from becoming conductive at the same time, and it is possible to reduce the occurrence of noise due to a through current. When the current source / current source output transistors are switched to the conductive state, the first / second sequential conduction control transistors are conductive and the input signal is the first signal.
-Input to the control terminal of the output transistor for current discharge / current draw through the second signal delay circuit, and the output transistor for current discharge / current draw is closer to the transistor closer to the last stage from the input side. The timing to switch to the state is delayed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention. In FIG. 1, V _DD is a positive power supply (power supply for discharging current), V _SS is ground (power supply for drawing current), 1 is a first signal input terminal, 2 is a second signal input terminal, and 3 is a signal output terminal. 11 to 14 are PMOS
(Output transistor for discharging current) 15 to 18 are N
MOS (current drawing output transistor), 19-2
1 is a resistor that constitutes the first (delay) circuit for signal delay,
Numerals 22 to 24 are resistors constituting the second signal delay (resistive) circuit network, and these are the same as the configuration of the conventional example. 3
1 to 34 are PMOSs (first simultaneous cutoff control transistors), 35 to 38 are NMOSs (second simultaneous cutoff control transistors), 39 is an NMOS (first sequential conduction control transistor), and 40 is a PMOS (transistor). Second sequential conduction control transistor).

The output buffer circuit of this embodiment is similar to the conventional example in that a parallel circuit of PMOSs 11 to 14 and an NMOS 15 are provided.
No. 1 to No. 18 parallel circuit and resistors 19 to 21
And a second signal delay circuit network composed of resistors 22 to 24. PMOS 11-
The parallel circuit of 14 is connected between the positive power supply V _DD and the signal output terminal 3, and the parallel circuit of the NMOS 15 to 18 is connected to the ground V _SS.
And the signal output terminal 3 are connected. Resistance 19-2
The first signal delay circuit network configured by 1 is provided in a path from the first signal input terminal 1 to the control terminals of the PMOSs 11 to 14, and the first signal input terminal 1 to the PMOS 1
The signal transmission times of the paths to the control terminals 1 to 14 are made different. The second signal delay circuit network composed of the resistors 22 to 24 is connected from the second signal input terminal 2 to the NMO.
It is provided on the route to each control terminal of S15-18, and the second
The signal transmission time of the path from the signal input terminal 2 to the control terminals of the NMOSs 15 to 18 is made different.

Further, in this embodiment, the NMOS 39
, PMOS 31-34, PMOS 40, NMOS
35-38 are provided. The NMOS 39 is inserted between the first signal input terminal 1 and the start end of the first signal delay circuit network, and supplies an input signal having a polarity for making the PMOSs 11 to 14 conductive to the start end of the first signal delay circuit network. Supply. PM
The OSs 31 to 34 have the first signal input terminal 1 and the PMOS 1
1 to 14 are inserted between the control terminals and the PMOS 11
An input signal having a polarity that cuts off .about.14 is bypassed through the first signal delay circuit network and directly supplied to the control terminals of the PMOSs 11-14. The PMOS 40 has a second signal input terminal 2
Is inserted between the start end of the second signal delay network and N
An input signal having a polarity for turning on the MOSs 15 to 18 is supplied to the starting end of the second signal delay circuit network. NMOS 35-3
A reference numeral 8 is inserted between the second signal input terminal 2 and the control terminals of the NMOSs 15 to 18 and bypasses the second signal delay circuit network for an input signal having a polarity for cutting off the NMOSs 15 to 18 so as to bypass the NMOSs 15 to 18. Supply directly to the control terminal of.

Therefore, the PMOSs 31 to 34 play a role of giving an input signal when the PMOSs 11 to 14 of the output transistors are switched to the cutoff state, and the NMOS 39.
Serves to provide an input signal when the PMOSs 11 to 14 switch to the conductive state. Also, NMOS 35-3
8 serves to provide an input signal when the NMOS transistors 15 to 18 of the output transistors are switched to the cutoff state, and PM
The OS 40 plays a role of supplying an input signal when the NMOSs 15 to 18 are switched to the conductive state.

The operation of the output buffer circuit of this embodiment having the above structure will be described below. First, as the initial state, the first and second signal input terminals 1 and 2 are
If an L level signal is input to the
To 14 are cut off, NMOSs 15 to 18 are conductive, P
MOS 31-34, 40 are conductive, NMOS 35-3
It is assumed that 9 is in a cutoff state and an L level signal is output to the signal output terminal 3.

First, assuming that an H level signal is input to the first and second signal input terminals 1 and 2 of FIG.
S31 to 34 and 40 are turned off, and NMOS 35 to
39 becomes conductive. At this time, an L level signal is input to the respective control terminals of the output transistors PMOS 11 to 14 and NMOS 15 to 18. As a result, an H level signal is output to the signal output terminal 3.
At this time, the signals entering the control terminals of the PMOSs 11 to 14 are delayed by the resistors 19 to 21, and the final stage (output side)
The closer the transistor is, the later the timing of switching to the conductive state. Therefore, the PMOS 11 connected in parallel is
-14 gradually switches to the conductive state from the first stage to the last stage. On the other hand, the signals input to the control terminals of the NMOSs 15 to 18 are not affected by the resistors 22 to 24 because they are input by the NMOSs 35 to 38. Therefore, NMOS1
5 to 18 are switched to the cutoff state almost at the same time when the signal is first input.

On the contrary, the first and second signal input terminals 1,
Similarly, when an L level signal is input to 2,
The MOS31 to 34, 40 are turned on, and the NMOS3
5 to 39 are cut off. At this time, an H level signal is input to the respective control terminals of the output transistors PMOS 11 to 14 and NMOS 15 to 18. As a result, an L level signal is output to the signal output terminal 3. At this time, the signals that enter the control terminals of the NMOSs 15 to 18 are delayed by the resistors 22 to 24, and the closer to the final stage (output side) the transistor is, the later the timing of switching to the conductive state is delayed. Therefore, NMOSs connected in parallel
In Nos. 15 to 18, the conductive state is gradually switched from the first stage to the last stage. On the other hand, the signals that enter the control terminals of the PMOSs 11 to 14 are not affected by the resistors 19 to 21 because they are input by the PMOSs 31 to 34. Therefore, PM
The OSs 11 to 14 are switched to the cutoff state almost at the same time when the signal is first input.

FIG. 2 compares the operation waveforms of the individual output transistors of the conventional output buffer circuit and the output buffer circuit of this embodiment. First, FIG.
(B) represents the relationship between the output current and time of each output transistor connected in parallel in the conventional output buffer circuit, and the relationship between the through current flowing between the power supply (V _DD ) and the ground (V _SS ) and the time. FIGS. 2 (c) and 2 (d) show the relationship between the output current and time of each output transistor connected in parallel in the output buffer circuit of this embodiment, power supply (V _DD ) -ground (V _SS ). It is a figure showing the relation between the penetration current which flows between and time. Here, when the NMOSs 15 to 18 are switched to the cutoff state and the PMOSs 11 to 14 are switched to the conductive state, the NMOSs 15 to 18 are referred to as “blocking side output transistors”, the PMOSs 11 to 14 are referred to as “conduction side output transistors”, and the PMOSs 11 to When 14 switches to the cutoff state and NMOSs 15 to 18 switch to the conductive state, the PMOSs 11 to 14 are referred to as “blocking side output transistors” and the NMOSs 15 to 18 are referred to as “conduction side output transistors”.

In the conventional output buffer circuit shown in FIGS. 2 (a) and 2 (b), since both the cutoff side output transistor and the conduction side output transistor are deviated in the timing of switching due to the resistance, they are conducted in an early time. The time during which the conducting-side output transistor that switches to the state and the blocking-side output transistor that switches to the blocking state at a later time are simultaneously in the conducting state becomes longer, and the amount of through current flowing between the power supply and ground increases. On the other hand, in the output buffer circuit of this embodiment shown in FIGS. 2 (c) and 2 (d), the conduction side output transistor has a deviation in the timing of switching to the conduction state by the resistance, but the cutoff side output transistor has the resistance. Since there is no intervention, there is no deviation in the switching timing, and switching to the cutoff state occurs almost at the same time. Therefore, there is almost no time during which both the conduction-side output transistor and the cut-off-side output transistor are in the conduction state at the same time, and the amount of through current flowing between the power supply and the ground can be reduced.

FIG. 3 shows PMOSs 11 to 11 in this embodiment.
FIG. 19 is a mask layout diagram of an output transistor section composed of 14, NMOSs 15 to 18, 50 is polysilicon (first and second resistor films), and a control terminal (gate electrode) of the output transistor and a resistance between the control terminals. Used as. As shown in FIG. 3, polysilicon 50 forming a control terminal is used for the wiring between the control terminals of the output transistors connected in parallel, and the control terminals of the output transistors are connected in series with the polysilicon 50. It is configured. With this configuration, the resistors 19 to 24 shown in FIG.
Can be configured by the sheet resistance of the polysilicon 50, so that the area on the layout can be reduced.

As described above, according to this embodiment, the PMO
The PMOSs 31 to 34 are connected to the control terminals of S11 to 14, the NMOS 39 is connected to the control terminal of the first-stage PMOS 11, and the NMOS 3 is connected to the control terminals of the NMOS 15 to 18.
5 to 38 are connected, and PMOS 40 is connected to the control terminal of the first-stage NMOS 15
14, by eliminating the timing deviation when the output transistors of the NMOSs 15 to 18 are switched to the cutoff state and generating the timing deviation only when the output transistors are switched to the conductive state.
It is possible to prevent both of 5 to 18 from becoming conductive at the same time, and to suppress the generation of noise due to a through current.

In the above embodiment, the output transistors include four transistors, PMOS 11 to 14 and NMOS 15 to 18, respectively. However, the number of the transistors may be two or more. PMO
The numbers of S and NMOS need not necessarily match. Further, in the above embodiment, the PMOSs 31 to 34 and the NMOSs 35 to 38 used for controlling the cutoff side of the output transistors are the PMOSs 11 to 14 and the NMOS 15 of the output transistor section.
The number is the same as that of ~ 18, but not necessarily the same number.

[0025]

According to the output buffer circuit of the present invention, an input having a polarity which is inserted between the first signal input terminal and the starting end of the first signal delay circuit network and makes the plurality of current discharging output transistors conductive. A first sequential conduction control transistor for supplying a signal to the starting end of the first signal delay network; and a first signal input terminal and each control terminal of the plurality of current discharge output transistors. A first simultaneous cutoff control transistor group for supplying an input signal having a polarity for cutting off the plurality of current discharge output transistors, directly to the control terminals of the plurality of current discharge output transistors, bypassing the first signal delay circuit network. And an input signal having a polarity which is inserted between the second signal input terminal and the start end of the second signal delay circuit network to make the plurality of current drawing output transistors conductive. A plurality of current drawing outputs inserted between the second sequential conduction control transistor supplied to the beginning of the signal delay network and the second signal input terminal and the control terminals of the plurality of current drawing output transistors. By providing a second simultaneous cutoff control transistor group for supplying an input signal of a polarity for cutting off the transistor to the control terminals of the plurality of current drawing output transistors by bypassing the second signal delay circuit network. , The first and second simultaneous cutoff control transistor groups output the input signal without passing through the first and second signal delay circuit networks only when the current discharge / current draw output transistors switch to the cutoff state. In order to serve as a bypass for transmitting to the control terminal of the output / current sink output transistor, the output current / current sink output transistor Register time is faster to change the cut-off state, prevents both the output transistor for attracting and for the current source current is turned on at the same time, it is possible to reduce the generation of noise due to through current.

[Brief description of drawings]

FIG. 1 is a circuit diagram of an output buffer circuit according to an embodiment of the present invention.

FIG. 2 is a diagram for comparing operation waveforms of output transistors in an embodiment of the present invention and a conventional example.

FIG. 3 is a mask layout diagram of an output transistor section according to an embodiment of the present invention.

FIG. 4 is a circuit diagram of a conventional output buffer circuit.

[Explanation of symbols]

1 1st signal input terminal 2 2nd signal input terminal 3 Signal output terminal 11, 12, 13, 14, 31, 32, 33, 34, 4
0 P-channel MOS transistor 15, 16, 17, 18, 35, 36, 37, 38, 3
9 N-channel MOS transistor 19, 20, 21, 22, 23, 24 Resistance 50 Polysilicon

Claims (3)

[Claims] 1. A parallel circuit of a plurality of current source output transistors connected between a current source and a signal output terminal, and a plurality of current source connected between a current source and a signal output terminal. Of the parallel output output transistors and a path from the first signal input terminal to the control terminals of the plurality of current output output transistors, and the plurality of current output output transistors are provided from the first signal input terminal. The first signal delay circuit network that makes the signal transmission time of the path to each control terminal different, and the path provided from the second signal input terminal to each control terminal of the plurality of current drawing output transistors are provided. A second signal that makes the signal transmission time of the path from the second signal input terminal to each control terminal of the plurality of current drawing output transistors different. A delay circuit; and an input signal having a polarity that is inserted between the first signal input terminal and the start end of the first signal delay circuit to turn on the plurality of current discharging output transistors. 1
A first sequential conduction control transistor to be supplied to the start end of the signal delay circuit network, and a plurality of the plurality of current conduction output control transistors inserted between the first signal input terminal and the control terminals of the plurality of current discharging output transistors. First simultaneous cut-off control transistor for supplying an input signal of a polarity for cutting off the current discharge output transistor of (3) directly to the control terminals of the plurality of current discharge output transistors by bypassing the first signal delay circuit network A group, and a second input signal having a polarity that is inserted between the second signal input terminal and the start end of the second signal delay network to make the plurality of current drawing output transistors conductive.
A second sequential conduction control transistor supplied to the beginning of the signal delay circuit network, and a plurality of the plurality of current conduction output transistors inserted between the second signal input terminal and the control terminals of the plurality of current drawing output transistors. A second simultaneous cutoff control transistor group for supplying an input signal having a polarity for cutting off the current drawing output transistor by bypassing the second signal delay circuit network and directly supplying it to the control terminals of the plurality of current drawing output transistors. And an output buffer circuit having. 2. The first and second signal delay networks include:
An output buffer circuit as claimed in claim 1, each comprising a first and a second signal delay resistor network. 3. A plurality of current source output transistors and a plurality of current source output transistors each comprise a MOS field effect transistor, and a first signal delay resistor network includes a plurality of current source output transistors. A first resistor film that connects between the gate electrodes, and the first resistor film is formed of the same material as the gate electrodes of the plurality of current output output transistors,
The second signal delay resistor network is composed of a second resistor film connecting the gate electrodes of the plurality of current drawing output transistors, and the second resistor film is connected to the plurality of current drawing outputs. The output buffer circuit according to claim 2, wherein the output buffer circuit is formed of the same material as the gate electrode of the transistor.