JPH098754A - Hysteresis circuit - Google Patents

Abstract

PURPOSE: To provide a hysteresis circuit with which the adverse effect of offset is prevented. CONSTITUTION: This circuit is provided with Trs 8 and 9 to which a stereo composite signal and its inversion signal are impressed, Trs 10, 12, 11 and 13 to which a switching signal and its inversion signal are impressed, Trs 16, 17, 18 and 19 for which a common emitter is respectively connected to the common emitters of the Trs 10 and 12 and Trs 11 and 13, trigger circuit composed of Trs 21 and 22 for generating trigger responding to a differential current between the added collector current of Trs 10, 13, 17 and 19 and the added collector current of Trs 11, 12, 16 and 19, and AND circuits 27a and 27b for cutting off a second input signal and its inversion signal to be impressed to the Trs 16-Trs 19 responding to this trigger.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a stereo detection circuit for detecting stereo reception or monaural reception in FM stereo broadcasting.

[0002]

2. Description of the Related Art Conventionally, in an FM stereo receiver, whether stereo broadcasting or monaural broadcasting is detected, and during stereo broadcasting, a stereo decoder performs a stereo decoding operation or indicates that stereo broadcasting is being received. The stereo display element lights up. Also, during monaural broadcasting,
According to the detection result, the stereo decoder does not perform the stereo decoding operation, and the stereo display element is turned off.
A circuit for detecting whether or not it is such a stereo broadcast is known as shown in FIG.

In FIG. 2, a stereo composite signal is applied to an input terminal (1), and the stereo composite signal is applied to a synchronous detection circuit (2) and a PLL (phase locked loop). The PLL circuit (3) reproduces a switching signal synchronized with the subcarrier signal based on the pilot signal in the stereo composite signal, and applies it to the synchronous detection circuit (2). The stereo composite signal and the switching signal are synchronously detected by the synchronous detection circuit (2). The output signal of the synchronous detection circuit (2) is applied to the trigger circuit (4), and the switching transistor (5) is turned on / off according to the output signal of the trigger circuit (4) to display the display element (6). Turns on or off, and the stereo decoder (7)
Operate stereo decoding.

Here, during stereo broadcasting, a switching signal synchronized with the subcarrier signal is reproduced in the PLL circuit (3), so that the synchronous detection circuit (2) performs a synchronous detection operation by the switching signal. Therefore, when the output signal is generated from the synchronous detection circuit (2) and the level of the output signal exceeds the on level, the output signal is generated from the trigger circuit (4). Then, the display element (6) lights up according to the output signal of the trigger circuit (4) and the stereo decoder (7) performs stereo decoding. Since the trigger circuit (4) has a hysteresis characteristic and the off level is set lower than the on level, the trigger circuit (4) caused by the fluctuation of the level of the stereo composite signal.
Can be prevented from malfunctioning.

Further, since there is no pilot signal during monaural broadcasting, the synchronous detection circuit (2) does not perform synchronous detection operation and does not generate an output signal. Therefore, the trigger circuit (4)
No output signal is generated, the display element (6) is turned off, and the stereo decoder (7) does not perform stereo decoding.
Incidentally, the synchronous detection circuit (2) is composed of a double balanced type differential amplifier as shown in FIG. The stereo composite signal and its inverted signal are applied to the transistors (8) and (9), the switching signal is applied to the transistors (10) and (11), and the inverted signal is applied to the transistors (12) and (13). To be done. The collector current of the transistor (8) and the collector current of the transistor (9) generated according to the stereo composite signal are
It is supplied to the common emitters of the transistors (10) and (12) and the common emitters of the transistors (11) and (13), respectively. Further, the collector currents of the transistors (10) to (13) are generated in response to the switching signal, and the added collector currents of the transistors (10) and (13) are supplied to the transistor (14) and the transistor (14) and the current mirror. It is generated in the collector of the transistor (15) that constitutes the circuit. Therefore, the output terminal (1
From 6), a difference current is generated between the added collector current of the transistors (11) and (12) and the collector current of the transistor (15). Therefore, according to the stereo composite signal and the switching signal, the respective transistors operate to generate the synchronous detection output signal at the output terminal (16). By using the double-balanced differential amplifier in this way, it is possible to provide a stereo state detection circuit that can be easily integrated into an IC.

[0006]

However, in the synchronous detection circuit (2), a DC offset voltage is generated due to variations in the characteristics of the transistors forming the differential pair. Therefore, the DC offset voltage causes the trigger circuit (4). There is a problem that the on / off operation of) malfunctions. For example, if the ON voltage and the OFF voltage of the trigger circuit (4) are set to 10 mV and 5 mV and a DC offset voltage of 6 mV is generated, the output signal is output by the synchronous detection circuit (2) performing a detection operation by stereo broadcasting. When the trigger circuit (4) is generated and the input voltage of the trigger circuit (4) becomes 10 mV or more, an output signal is generated from the trigger circuit (4).
After that, when the stereo broadcast is changed to the monaural broadcast, the synchronous detection circuit (2) stops the detection operation, and the output voltage becomes 6 mV corresponding to the DC offset voltage. The output voltage is 5
Since it does not become lower than the off voltage of mV, the output signal continues to be generated from the trigger circuit (4). Therefore, even during monaural broadcasting, the display element (6) was erroneously turned on and the stereo decoder (7) was erroneously decoding.

When the circuit of FIG. 2 is integrated into an IC,
The malfunctioning stereo detection circuit cannot be used, and the chip becomes an error chip, which has been an obstacle to improving the yield. Therefore, conventionally, in order to improve the yield, the on-voltage and the off-voltage of the trigger circuit (4) are increased to a level at which the DC offset voltage is not adversely affected. However, the stereo detection sensitivity is deteriorated by increasing the ON voltage of the trigger circuit (4).

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and an input stage circuit in which the gain is set to the first state and an output signal of the input stage circuit is equal to or higher than a predetermined level. If there is, a trigger circuit for generating a trigger and a gain changing circuit for changing the setting of the gain of the input stage circuit to the second state according to the trigger circuit are provided.

The input stage circuit includes a first differential pair to which a first input signal and its inverted signal are applied, and a second and third differential pair to which a second input signal and its inverted signal are applied. And are provided. Further, in the gain changing circuit, a common emitter is connected to a common emitter of each of the second and third differential pairs, and a fourth input signal and an inverted signal thereof are applied to a fourth and fifth differential pair. And a cutoff circuit that cuts off the first input signal and its inverted signal according to the output signal of the trigger circuit.

Furthermore, the ratio of the emitter area of the transistors forming the second and third differential pairs to the emitter area of the transistors forming the fourth and fifth differential pairs is set to 1: K. It is characterized by Furthermore, the first input signal is an FM stereo composite signal,
The second input signal is applied as a switching signal synchronized with the subcarrier signal, and an output signal indicating a stereo state is generated at the output terminal of the trigger circuit.

[0011]

According to the present invention, in the initial state, the first to fifth differential pairs are turned on, the first and second input signals are applied, and synchronous detection is performed. The output signals of the second to fifth differential pairs are applied to the trigger circuit, and triggers are generated according to the output signal levels of the second to fifth differential pairs. The cutoff circuit cuts off the second input signal and its inverted signal by the trigger, and only the first to third differential pairs operate. This allows
The output signal levels of the second and third differential pairs become high. Therefore, it is possible to prevent malfunction of the trigger circuit due to fluctuations in the first and second input signal levels.

[0012]

FIG. 1 is a diagram showing an embodiment of the present invention,
(16) and (17) constitute a fourth differential pair, the common emitter of which is connected to the common emitters of the transistors (10) and (12), and (18) and (19) are the fifth differential pair. And the common emitter is a transistor (1
Transistors connected to the common emitters of 1) and (13), (20) an LPF (low-pass filter) to which an output signal from the output terminal (16) is applied, and (21) and (22) a trigger circuit. Transistors constituting the sixth differential pair, (23) and (24) are transistors constituting a current mirror circuit which becomes an output load of the sixth differential pair, (2
5a) and (25b) are first output stage transistors to which the output signal of the sixth differential pair is applied, and (26a) and (26).
b) is a second output stage transistor to which the output signal of the sixth differential pair is applied, and (27a) and (27b) are AND circuits which are turned on / off according to the output signal of the first output stage transistor (25b). Is. The same elements as those in the conventional example shown in FIG. 2 are designated by the same reference numerals as those in the conventional example shown in FIG. Further, the transistors (8) and (9) form a first differential pair, and the transistors (10) and (1)
2) is a second differential pair, which includes transistors (11) and (1
3) constitutes a third differential pair.

In FIG. 1, a stereo composite signal, which is an input signal, is applied to the bases of the transistors (8) and (9) via the input terminal (1), and at the same time, the PLL.
Applied to the circuit (3). An inverted signal of the stereo composite signal is applied to the base of the transistor (9). In the PLL circuit (3), the switching signal synchronized with the subcarrier signal in the stereo composite signal is reproduced. On the other hand, in the initial state, the output signal from the output stage transistor (25a) becomes the “H” level,
The AND circuits (27a) and (27b) are on.
Therefore, the switching signal from the PLL circuit (3) is
It is applied to the bases of the transistors (10) to (13) and also applied to the bases of the transistors (16) to (19) through AND circuits (27a) and (27b). The transistors (12), (13), (1
An inverted signal of the switching signal is applied to the bases 7) and 18).

Since there is no pilot signal in the composite signal during monaural broadcasting, the synchronous detection circuit composed of the transistors (8) to (13) and the transistors (16) to (19) does not perform synchronous detection, and the output terminal No output signal is generated from (16). Therefore, the bases of the transistors (21) and (22) have a constant voltage source (2
The same bias from 8) is applied and the transistor (2
The collector currents of 1) and (22) are the same. As a result, the collector current of the transistor (24) and the collector current of the transistor (21) become the same, the input current is not supplied to the bases of the output stage transistors (25a) and (26a), and the output stage transistors (25a) and (25a). Two
6a) is turned off. Therefore, the output stage transistor (25
An output signal of "H" level is generated from the collector end of b), and the AND circuits (27a) and (27b) maintain the ON state. The "H" level output circuit generated from the collector terminal of the output stage transistor (26b) is applied to the stereo display circuit and the stereo decoder in the subsequent stage through the output terminal (32).

In stereo broadcasting, the PLL circuit (3)
A switching signal is generated from the synchronous detection circuit, and the synchronous detection circuit including the transistors (8) to (13) and the transistors (16) to (19) performs the synchronous detection operation. The collector current of the transistor (8) and the collector current of the transistor (9) generated according to the stereo composite signal are the common emitter of the transistors (10), (12), (16) and (17) and the collector current of the transistor (9), respectively. 11),
It is supplied to the common emitters of (13), (18) and (19). Further, the transistors (10) to (19)
Collector current is generated in response to the switching signal, and the transistors (10), (13), (17) and (19)
Is added to the transistor (14) and is generated in the collector of the transistor (15) that forms a current mirror circuit with the transistor (14). For that reason,
From the output terminal (16) to the transistors (11), (1
2), (16) and (18) and the collector current of the transistor (15) difference current is generated. Therefore, according to the stereo composite signal and the switching signal, the respective transistors operate to generate the synchronous detection output signal at the output terminal (16).

Here, the synchronous detection output signal will be described. However, the transistor (1
A case where 0), (11), (16) and (19) are turned on will be described. When the output current of the constant current source (29) is 2I, the collector currents of the transistors (8) and (9) become (I + i) and (I-i), respectively. However, i
Is the change in the collector current of the transistors (8) and (9) according to the stereo composite signal. If the ratio of the emitter area of the transistors (10) to (13) to the emitter area of the transistors (16) to (19) is 1: K, the collector current I1 of the transistor (10) becomes

[0017]

[Equation 1]

Therefore, the collector current I2 of the transistor (16) is

[0019]

[Equation 2]

[0020] The collector current I3 of the transistor (11) is

[0021]

(Equation 3)

Therefore, the collector current I4 of the transistor (19) is

[0023]

(Equation 4)

It becomes Therefore, the output current Io1 of the output terminal (16) is a difference current between the inversion current of the added collector currents of the transistors (10) and (19) and the added collector current of the transistors (11) and (16).

[0025]

(Equation 5)

## EQU1 ## Conversely, the transistor (12),
When (13), (17) and (18) are on,
The output current Io1 ′ of the output terminal (16) is

[0027]

(Equation 6)

Then, (1-K) / (1 of the change current 2i
+ K) times. After that, the output signal of the output terminal (16) is smoothed by the LPF (20), and then the transistor (2
It is applied to the base of 1). In the differentially connected transistors (21) and (22), the transistor (2
3) and (24) emitter resistors (30) and (31)
The values R1 and R2 of R1> R2 have a relation of R1> R2, and when there is no input signal applied to the base of the transistor (21), the collector current of the transistor (24) becomes larger than the collector current of the transistor (21). , The output stage transistor (25a) is off. After that, the input signal to the base of the transistor (21) increases, and the collector current of the transistor (21) changes to the transistor (24).
The output stage transistors (25a) and (26a) are turned on at the time when the collector current becomes larger than the collector current. Therefore, the emitter resistance (30) of the transistors (23) and (24)
By arbitrarily setting the ratio of (31) and (31), the on level or the off level of the trigger circuit can be arbitrarily set.

When the output stage transistor (25a) is turned on, the output stage transistor (25b) is also turned on,
An output signal of "L" level is generated from the collector terminal of the transistor (25b). Similarly, the output stage transistors (26a) and (26b) are turned on, and an "L" level output signal is generated at the output terminal (32). After that, the AND circuits (27a) and (27b) are turned off, and the switching signal is cut off. Therefore, the transistors (16) to (19) do not operate, and the transistors (8) to (13)
By this, synchronous detection is performed, and a synchronous detection output signal is generated from the output terminal (16). You. Since the operation of the synchronous detection is the same as that of the conventional example, the description of the operation will be omitted.

Now, the operation detection output signal will be described. However, in order to simplify the explanation, the transistor (1
A case where 0) and (11) are turned on will be described. As described above, the collector currents of the transistors (8) and (9) are (I + i) and (I-i), respectively, and the emitter areas of the transistors (10) to (13) are 1. Therefore, the collector current I5 of the transistor (10)
Is

[0031]

(Equation 7)

Therefore, the collector current I6 of the transistor (11) is

[0033]

(Equation 8)

## EQU1 ## Therefore, the output current Io2 of the output terminal (16) is a difference current between the inversion current of the added collector currents of the transistors (10) and (19) and the added collector current of the transistors (11) and (16).

[0035]

[Equation 9]

It becomes On the contrary, when the transistors (12) and (13) are turned on, the output current Io2 ′ of the output terminal (16) is

[0037]

(Equation 10)

## EQU4 ## Therefore, when the AND circuits (27a) and (27b) are turned off, the output terminal (16)
Output signal is multiplied by (1 + K) / (1-K), which means that the gain of the synchronous detection circuit is increased. Therefore, the input signal level of the trigger circuit becomes high, and the off level of the trigger circuit seen from the input terminal (1) becomes small. Therefore,
Even if the level of the stereo composite signal fluctuates, it is possible to prevent a malfunction that the output stage transistors (25a) and (26a) are turned off.

After that, when the subcarrier signal is not reproduced by the PLL circuit (3) after returning to the monaural broadcasting, the output signal is not generated from the output terminal (16), and the base voltages of the transistors (21) and (22) are changed. Be the same. Therefore, the output stage transistors (25a) and (26a) are turned off, and the output signals from the output stage transistors (25b) and (26b) become "L" level.

By the way, the transistors (21) and (2
If the on level and off level of the trigger circuit composed of 2) are 10 mV, the DC offset voltage generated from the output terminal (16) is 6 mV, and (1 + K) / (1-K) = 1.5, the input terminal (1) When the input voltage (including the DC offset voltage) of the trigger circuit becomes 10 mV according to the stereo composite signal of, the output signal is generated from the trigger circuit and the output current of the output terminal (16) is multiplied by 1.5. . Therefore, the input voltage of the trigger circuit changes to 12 mV. When the pilot signal does not exist in the stereo composite signal, the input voltage of the trigger circuit becomes only the DC offset voltage, which is lower than the off voltage of the trigger circuit, and the trigger circuit is turned off. like this,
The input / output characteristics of the hysteresis circuit are shown in FIG. In the initial state, the relationship between the input signal and the output signal is as shown by a straight line (a), and when the output signal level is higher than 10 mV, the relationship between the input signal and the output signal is as shown by a straight line (b). On the contrary, when the relationship between the input signal and the output signal is as shown by the straight line (b) and the output signal level becomes lower than 10 mV, the relationship between the input signal and the output signal is as shown by the straight line (a). Therefore, the hysteresis circuit can have only one on / off level.

[0041]

As described above, according to the present invention, since the hysteresis characteristic can be obtained by simply adjusting the gain of the input stage circuit, an input signal including an offset of about ON / OFF level can be obtained. On the other hand, a malfunction can be prevented, and a hysteresis circuit suitable for IC integration can be provided. Further, since the gain of the input stage circuit is controlled by the output signal of the trigger circuit, it is possible to form a circuit having one reference level. Further, in the initial state, the first to fifth differential pairs operate, and then the output signals generated from the trigger circuit are generated in response to the first to third differential signals.
Since only the differential pair operates, the off voltage of the trigger circuit is apparently lowered, and the malfunction of the trigger circuit due to the fluctuation of the input signal can be prevented. Further, since the on / off level of the trigger circuit is constant regardless of the operating states of the fourth and fifth differential pairs, the operation of the trigger circuit can be surely turned off. Therefore, erroneous detection from the stereo state to the monaural state near the on / off level due to the offset is eliminated, and erroneous lighting of the stereo display element and erroneous operation of the stereo decoder can be prevented. Moreover, since the differential pair is added to the differential pair, the gain can be controlled with a simple configuration.

Further, the on / off level of the trigger circuit can be set independently of the DC offset voltage. Therefore, when integrated into an IC,
It is possible to achieve both improvement in yield and improvement in stereo detection sensitivity.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

FIG. 3 is a characteristic diagram for explaining the present invention.

[Explanation of symbols]

 1 input terminal 3 PLL circuit 20 LPF 27a, 27b AND circuit

Claims (5)

[Claims] 1. An input stage circuit having a gain set to a first state, a trigger circuit for generating a trigger when an output signal of the input stage circuit is at a predetermined level or higher, and the trigger circuit according to the trigger circuit. A hysteresis circuit, comprising: a gain changing circuit for changing the gain of the input stage circuit to a second state. 2. The input stage circuit comprises a first differential pair to which a first input signal and its inverted signal are applied, and a second and third differential pair to which a second input signal and its inverted signal are applied. The hysteresis circuit according to claim 1, further comprising: 3. The gain changing circuit has fourth and fifth common emitters, the common emitters being connected to the common emitters of the second and third differential pairs, respectively, and the second input signal and its inverted signal being applied to the bases. 3. The hysteresis circuit according to claim 2, comprising a differential pair and a cutoff circuit that cuts off the first input signal and its inverted signal according to the output signal of the trigger circuit. 4. The ratio of the emitter area of the transistors forming the second and third differential pairs to the emitter area of the transistors forming the fourth and fifth differential pairs is set to 1: K. The hysteresis circuit according to claim 3, wherein: 5. The first input signal is an FM stereo composite signal, the second input signal is applied as a switching signal in synchronization with a subcarrier signal, and an output signal indicating a stereo state is generated at an output end of the trigger circuit. The hysteresis circuit according to claim 2, wherein: