JPH098760A - Multiplexer - Google Patents

Abstract

PURPOSE: To easily and surely multiplex asynchronous serial data by discriminating the coincidence/non-coincidence of a logical level at the timing of continuous edges and setting the timing of a latch based on this result while the edge of a reference signal, whose frequency is double as high as the clock frequency of serial data, is defined as a reference. CONSTITUTION: In latch circuits 29, 30, 35 and 36 by using the reference signal as the reference, latch digital video signals DV1 and DV2 are successively latched by position information extracting circuits 12 and 13. Thus, the logical levels of DV1 and DV2 are successively and cyclically detected at the timing of respective edges of a master clock MCK whose clock cycle is 1/2 as short as the clock cycle of digital video signals DV1 and DV2. Further, the position information extracting circuits 12 and 13 discriminate the matching/mismatching of the logical level corresponding to the continuous edges among these detected logical levels while using AND circuits 31 and 37.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer, for example, when a digital video signal composed of serial data is multiplexed and transmitted, a reference signal whose frequency is twice the clock frequency of the digital video signal is used. By determining the coincidence or non-coincidence of the logic levels of the digital video signal at the timing of consecutive edges with reference to the edge, asynchronous serial data can be multiplexed easily and reliably.

[0002]

2. Description of the Related Art Conventionally, in a television camera system, a camera control unit and a camera head unit are connected by a coaxial cable or the like so that the camera head unit transmits an image pickup result to the camera control unit. Control signals, return images, etc. are transmitted to the camera head unit.

[0003]

By the way, in the television camera system of this type, if the work of laying the cable connecting the camera head unit and the camera control unit can be simplified, the work of installation can be remarkably improved. Conceivable. For this reason, if one cable can be shared by a plurality of camera head units, for example, the imaging results can be transmitted from a plurality of camera head units installed at relay points with one cable, and cable laying work can be performed. It is believed that can be simplified.

Specifically, in a camera head unit that sends a digital video signal that is the image pickup result in the form of serial data, a digital video signal that is output from another camera head unit and a digital video that is the image pickup result. It is considered that one cable can be shared by two camera head units by multiplexing the signal and the signal in bit units.

However, when the digital video signals are multiplexed in this way, the digital video signals output from other camera head units are input with a delay according to the transmission distance. It will vary depending on the length of the cable connecting the camera head units. Therefore, in this type of television camera, a digital video signal whose phase relationship is not defined is multiplexed with the digital video signal obtained as a result of imaging, and eventually serial data whose phase is asynchronous is multiplexed. Will be transformed.

In this case, the conventional serial data multiplexing method detects phase information of each serial data by generating a clock synchronized with each serial data in a PLL (Phase Locked Loop) circuit, and detects the phase information of each serial data. Each serial data is latched on the basis of, to eliminate the phase difference between the serial data, and then multiplexed.

However, this method has the drawback that the detection accuracy of the phase information changes depending on the frequency of occurrence of each logic level in the serial data, the arrangement, etc. (that is, due to the pattern effect), and when the clock is generated. There is a problem that the accuracy of the phase information changes depending on the stability of the oscillator circuit and the overall configuration becomes complicated.

Particularly in this type of digital video signal, the transfer rate becomes high, so if such a conventional serial data multiplexing system is simply applied, in the end, the digital video signal can be simply and surely obtained. Is difficult to multiplex.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a multiplexer capable of easily and reliably multiplexing serial data such as a digital video signal.

[0010]

In order to solve such a problem, in the present invention, first and second serial data are multiplexed and the first and second serial data are serialized in synchronization with a prescribed master clock. It is applied to a multiplexer that converts data. In this multiplexer, reference signal generating means for generating a reference signal having a clock cycle of 1/2 cycle with respect to the clock cycle of the first serial data, and timing of consecutive edges of the reference signal, A determination unit that detects the logical level of the first serial data and determines whether the logical levels are the same or not, and a latch that latches the first serial data and that has a timing according to the determination result of the determination unit. A latch means for outputting the result and an output means for switching and outputting the latch result and the latch result of the second serial data are output at a prescribed timing.

In particular, at this time, the first serial data is a digital video signal input via a prescribed transmission path, and the second serial data is a digital video signal.

[0012]

A reference signal having a clock cycle of ½ cycle with respect to the clock cycle of the first serial data is generated, and at the timing of consecutive edges of the reference signal, the first
By detecting the logic level of each serial data and determining the coincidence / non-coincidence of the logic levels, the phase relationship of the first serial data with respect to this edge can be detected. As a result, it is possible to output the latch result at the timing according to the determination result of the determination means, and to latch the first serial data at the correct timing. The latch result and the second serial data are latched. The result and the result can be switched and output at a specified timing, and multiplexed easily and reliably.

In particular, at this time, when the first serial data is a digital video signal input through a prescribed transmission line and the second serial data is a digital video signal. The transmission speed becomes high, and even in such a case, the timing can be set so that the latch means can secure a sufficient setup time and holdup time.

[0014]

Embodiments of the present invention will be described in detail below with reference to the drawings.

(1) First Embodiment FIG. 2 is a block diagram showing a television camera system according to an embodiment of the present invention. The television camera system 1 includes camera head units 2 and 3 and a camera. Head unit 3 and camera control unit 4
Are connected by optical fiber cables 5 and 6, respectively.

Here, the optical fiber cables 5 and 6 are
It is formed by bundling two optical fibers, one of which is assigned to a main line system for transmitting an imaging result, and the other one is assigned to a return system for transmitting a return image and the like.

The camera control unit 4 transmits a digital video signal of the return image, control data, etc. to the camera head units 2 and 3 via the return system of the optical fiber cable 6. Here, the digital video signal of each return image has a transmission rate of 270.
It is formed of serial data of [Mbps], and the camera control unit 4 inserts control data or the like in the blanking period of this digital video signal and transmits it.

At this time, the camera control unit 4
Is for multiplexing the two systems of digital video signals corresponding to the camera head units 2 and 3 to transmit data at a transmission speed of 540
By generating the transmission data D1 of [Mbps] and sending the transmission data D1 to the optical fiber cable 6, the digital video signal is transmitted to the camera head units 2 and 3.

Further, the camera control unit 4 receives the multiplexed data D2 transmitted via the main line system of the optical fiber cable 6 and separates the multiplexed data into two systems of serial data, thereby the camera head unit. The imaging results 2 and 3 are received in the form of a digital video signal.

The camera head unit 3 receives the transmission data D1 from the return system of the optical fiber cable 6, separates the transmission data D1 into two systems of serial data, and thereby the transmission data D1 is respectively transferred to the camera head unit 2. And digital video signals corresponding to 3 and 3. The camera head unit 3 sends a digital video signal corresponding to the camera head unit 2 out of the two systems of digital video signals to the camera head unit 2 and inputs the remaining digital video signal to a prescribed signal processing circuit. As a result, the camera head unit 3 is formed so as to operate on the basis of this digital video signal to pick up an image of a desired subject.

Further, the camera head unit 3 has a transmission speed 27 inputted from the main line system of the optical fiber cable 5.
The digital video signal DV1 of 0 [Mbps] and the digital video signal of the transmission rate 270 [Mbps] which is the image pickup result are multiplexed to generate the multiplexed data D2 of the transmission rate 540 [Mbps], and the multiplexed data D2 is generated. It is sent to the main line system of the optical fiber cable 5.

On the other hand, the camera head unit 2 is
The digital video signal input from the camera head unit 3 is input to a prescribed signal processing circuit, whereby the digital video signal is operated with the digital video signal as a reference, and a digital video signal which is an imaging result is generated. The camera head unit 2 transmits this digital video signal DV1 to the camera head unit 3 via the main line system of the optical fiber cable 6.

As a result, in the television camera system 1, the digital video signals of the two systems resulting from the imaging are multiplexed by the camera head unit 3 and transmitted to the camera control unit 4, and the digital video signal of the return image is controlled by the camera. By multiplexing and transmitting from the unit 4, the camera head unit 2
3 and 3, the optical fiber cable 6 is shared so that the work of laying the transmission path can be simplified.

FIG. 3 is a block diagram showing the multiplexing circuit 10 of the camera head unit 3. The camera head unit 3 includes the digital video signal DV1 of the camera head unit 2 and the image pickup result by the multiplexing circuit 10. Multiplexed with the digital video signal DV2 to generate multiplexed data D2.

That is, in this multiplexing circuit 10, the master clock generation circuit 11 PLs the transmission data D1.
The master clock M having a frequency of 540 [MHz] is input to the L circuit and is synchronized with the transmission data D1.
Generate CK. In the camera head unit 3,
This master clock MCK is used as a clock for the operation reference of the image pickup system and the signal processing system.

The phase information extraction circuits 12 and 13 latch each digital video signal DV1 and DV2 with two reference signals generated with reference to the master clock MCK, and output the serial data DL1 and DL2 as the latch result. Outputs serial data DL1
And DL2 select signal SL is output.

That is, as shown in FIG. 1, the phase information extraction circuits 12 and 13 give the master clock MCK to the reference signal generation circuit 20. As shown in FIG. 4, in the reference signal generation circuit 20, the ½ frequency divider circuit 21 has a master clock MCK (FIG. 4) having a frequency of 540 [MHz].
(A)) is divided by 2 to obtain a digital video signal DV1
And a reference clock CK (FIG. 4B) having the same frequency as the clock frequency of SV2.

The OR circuit 23 uses the master clock MCK.
From the reference clock CK, a logical sum signal is obtained in which the signal level changes in synchronization with the signal level of the master clock MCK during the period in which the signal level of the reference clock CK is held at the L level, and the signal is thereby obtained. A reference signal S11 having a level change of 1/2 cycle of the digital video signals DV1 and DV2 is generated (FIG. 4 (D)).

The inverter circuit 24 is the OR circuit 2
The reference signal S11 output from the circuit 3 is inverted and output (FIG. 4C). As a result, the reference signal generation circuit 20
The signal level changes in the clock cycle of the digital video signals DV1 and DV2, the rising timing of the signal level is synchronized with the master clock MCK, and the deviation of this timing is caused by the digital video signals DV1 and DV1.
The reference signals S1 and S11 that are set to 1/4 of the V2 clock cycle are generated.

Further, in the reference signal generation circuit 20, the OR circuit 25 inputs the master clock MCK and the reference clock CK via the inverter circuit 26, and the signal level of the reference clock CK is held at the H level. During this period, by obtaining an OR signal in which the signal level changes in synchronization with the signal level of the master clock MCK, the change in the signal level becomes 1/2 cycle of the digital video signals DV1 and DV2, Further, a reference signal S21 having a phase shifted by 1/2 cycle with respect to the reference signal S11 is generated (FIG. 4 (F)).

The inverter circuit 27 is the OR circuit 2
The reference signal S21 output from the circuit 5 is inverted and output (FIG. 4 (E)). As a result, the reference signal generation circuit 20
A reference signal S1 whose signal level rises cyclically at the timing of each edge of this master clock MCK with reference to a master clock MCK whose clock period is 1/2 the clock period of the digital video signal DV1 (DV2). , S11, S2, S21 are generated.

The position detection circuit 28 supplies the digital video signal DV1 (DV2) (FIG. 4G) to the latch circuits 29 and 30 which are D-flip-flop circuits, and the signal levels of the reference signals S1 and S11 rise, respectively. The digital video signal DV1 (DV2) is latched at the timing. Further, the position detection circuit 28 inputs the latch results of the latch circuits 29 and 30 to the AND circuit 31,
The output signal of the AND circuit 31 is used as the first position detection signal P
It is output to the protection circuit 33 as 1.

On the other hand, the position detection circuit 34 applies the digital video signal DV1 (DV2) to the latch circuits 35 and 36 which are D-flip-flop circuits, and the digital signals are digitalized at the timing when the signal levels of the reference signals S2 and S21 rise. The video signal DV1 (DV2) is latched. Further, the position detection circuit 34 uses the latch circuit 3
The latch results of 5 and 36 are input to the AND circuit 37, and the output signal of this AND circuit 37 is used as the second position detection signal P2.
To the protection circuit 33.

In this way, the phase information extraction circuits 12 and 13 sequentially latch the digital video signal DV1 (DV2) by the latch circuits 29, 30, 35 and 36 with reference to the reference signals S1, S11, S2 and S21. Thus, the logic level of the digital video signal DV1 (DV2) is sequentially and cyclically detected at the timing of each edge of the master clock MCK whose clock period is ½ of the clock period of the digital video signal DV1 (DV2). It is designed to do. Further, the phase information extraction circuits 12 and 13 are
Among the detected logic levels, the match / mismatch of the logic levels corresponding to consecutive edges is determined.

That is, as shown in FIG. 5, the clock period T2 is 1/2 the clock period T1 of the digital video signal DV1 (DV2) (FIG. 5A) consisting of a serial data string. Considering the relationship between the clock CKM (FIG. 5 (B)), even when the digital video signal DV1 (DV2) and the clock CKM are asynchronous, the signal level of the clock CKM is twice in one cycle of the digital video signal DV1 (DV2). Get down.

Paying attention to the two periods A and B in which the signal level of the clock CKM falls, in the latch result of latching the digital video signal DV1 (DV2) at the front and rear edges of the period A, the digital video signal DV
When the logic level of 1 (DV2) is switched in 1-bit units, it is possible to obtain a latch result that does not match in this phase relationship.

On the other hand, in the latch result of latching the digital video signal DV1 (DV2) at the front and rear edges of the subsequent period B, the digital video signal DV1 (DV
Even if the logic level of 2) is switched in 1-bit units, a coincident latch result can be obtained in this phase relationship.

As a result, the clocks CK1 and C are respectively generated.
When the digital video signal DV1 (DV2) is latched at a time point midway between the periods A and B by the rising edge of K2 (FIGS. 5C and 5D), a mismatched latch result is obtained in the period A. At the intermediate timing, the digital video signal DV1 (DV2) cannot be correctly latched, while at the intermediate timing of the period B when the latch result of coincidence is obtained, sufficient setup time and hold-up time must be secured. The digital video signal DV1 (DV2) can be correctly latched. At the middle timing of this period B, the digital video signal DV1
Even if the phase of (DV2) changes, a sufficient phase margin can be secured.

As a result, the latch timing is set to the intermediate timing between the periods A and B and the timing delayed by 1/4 clock period from the respective timings (in FIGS. 5E and 5F, this timing is set). (The timing is indicated by an arrow), it is determined whether or not the latched results coincide, and the digital video signal DV1 (DV2) is latched at any timing of the intermediate timing of the period A and the intermediate timing of the period B. , It is possible to detect whether the digital video signal DV1 (DV2) can be reliably latched. That is, it is possible to detect which latch timing is close to the intermediate position of each bit, and thus it is possible to detect the phase information of the digital video signals DV1 and DV2 based on the latch timing. .

As a result, in this embodiment, the position detection circuits 28 and 34 (FIG. 1) output the latched results by the timing signals CK3 and CK4, respectively.
9, 30 and 35, 36, and the coincidence and non-coincidence are determined by the AND circuits 31 and 37, and the determination result is output to the protection circuit 33 as the first and second position detection signals P1 and P2.

By the way, the digital video signal DV1 (DV1
It is necessary that the logic level of 2) be switched in 1-bit units. That is, the digital video signal DV1
When (DV2) is continuously held at the same logic level, the coincidence determination result can be obtained regardless of the timing of latching.

Therefore, the protection circuit 33 captures the first and second position detection signals P1 and P2 which are continuous in correspondence with the encoding process of this digital video signal by a prescribed number of bits, and continuously uses these consecutive bits. Then, the position detection signal P1 or P2 for which a matching determination result is obtained is detected. Further, the protection circuit 33 switches the signal level of the selection signal SL corresponding to the detected position detection signal P1 or P2,
As a result, the latch timing corresponding to the period B described above with reference to FIG. 5 is selected.

In this way, the latch circuits 40 and 41 formed by the D-flip-flop circuit use the first and second reference signals S1 and S2 corresponding to the position detection signals P1 and P2, respectively, as a reference for digital video. The signal DV1 (DV2) is latched (FIG. 4), and the resulting digital video signals DL1 and DL2 (FIG. 4 (H)) are latched.
And (I)) are output.

Multiplexer (MUX) 45 (FIG. 3)
Receives the digital video signals DL1 and DL2 output from the phase information extraction circuits 12 and 13, respectively, at the contacts of the selection circuits 46 and 47, and sets the contacts of the selection circuits 46 and 47 with reference to the selection signal SL. As a result, the multiplexer 45 selects the digital video signal D1 or D2 which correctly represents the logic levels of the digital video signals DV1 and DV2 and which is synchronized with two cycles of the master clock MCK. Further, the multiplexer 45 inputs the digital video signals output from the selection circuits 46 and 47 to the selection circuit 48,
By switching the contact point of the selection circuit 48 with reference to the master clock MCK, multiplexed data D2 in which the logic levels of the digital video signals DV1 and DV2 are alternately continuous in 1-bit units is generated.

Thus, the multiplexing circuit 10 has a simple structure in which the master clock MCK is divided and the digital video signals DV1 and DV2 are latched.
The asynchronous digital video signals DV1 and DV2 can be reliably multiplexed and transmitted.

Note that the digital video signal of the return image sent from the camera control unit 4 side is simply latched and output from the selection circuit because the phase relationship is managed by the camera control unit 4 by the prescribed clock. It is designed to be multiplexed and transmitted.

In the above configuration, the digital video signal DV1 which is the image pickup result of the camera head unit 2 is
It is input to the camera head unit 3 at a transmission rate of 270 [Mbps] and is input to the multiplexing circuit 10 of the camera head unit 3. In the phase information extraction circuit 12 of the multiplexing circuit 10 (FIG. 1), the digital video signal DV1 is converted into the reference signals S1, S11, S2, S, respectively.
Latch circuits 29, 30, 3 that operate based on 21
5, 5 and 36, the clock frequency is sequentially and cyclically latched at the timing of each edge of the master clock MCK.

Further, in the digital video signal DV1, the AND circuits 31 and 37 determine whether the consecutive latch results of these latch results match or not, and the determination results are output to the protection circuit 33 as the position detection signals P1 and P2. It In the protection circuit 33, when the digital video signal DV1 is detected as the position detection signal P1 or P2 for which the coincidence result is continuously obtained by the specified bit, and when the position detection signal P1 or S2 is latched at any timing. It is detected whether it can be latched securely.

As a result, the digital video signal DV1
Is a reference signal S by latch circuits 40 and 41, respectively.
Of the latch results DL1 and DL2, which are latched at a timing synchronized with the master clock MCK with reference to 1 and S2, the latch result DL1 is reliably latched.
Alternatively, DL2 is selectively output from the selection circuit 46 (FIG. 3).

On the other hand, the digital video signal DV2, which is the image pickup result of the camera head unit 3, is input to the phase information extraction circuit 13, where it is processed in the same manner as the digital video signal DV1 and synchronized with the master clock MCK. Is output from the selection circuit 7.

The selection outputs of the selection circuits 46 and 47 are sequentially and alternately output at the timing of the master clock MCK by the selection circuit 48, whereby the digital video signals DV1 and DV2 are sequentially and alternately repeated bit by bit. Multiplexed data D2 is generated, and this multiplexed data D2 is transmitted to the camera control unit 4 via the optical fiber cable 6. This is 1
Connect the optical fiber cable 6 of the book to the camera head unit 2
3 and 3 can share the imaging result, and the cable laying work can be simplified.

According to the above configuration, the clock cycle is 1 /
At the timing of the edge of the master clock of 2, the logical level of the digital video signal which is the imaging result is detected,
The phase information of the digital video signal with respect to this edge can be easily detected by determining the coincidence / non-coincidence of the logic levels from the consecutive detection results. As a result, the digital video signal can be simply and reliably multiplexed by latching and outputting the digital video signal on the basis of the position detection result including the phase information.

(2) Second Embodiment FIG. 6 is a block diagram showing a phase information extraction circuit applied to a television camera system according to a second embodiment of the present invention. The phase information extraction circuits 50 and 51 are applied to the multiplexing circuit 10 instead of the phase extraction circuits 12 and 13 according to the first embodiment described above, and the position detection signals P1 and P2 and the digital video signals DL1 and DL2 are output. Output.

Here, the phase information extraction circuits 50 and 51
Replaces the dedicated latch circuits 40 and 41 (FIG. 1) for generating the digital video signals DL1 and DL2, and sequentially and cyclically detects the logic level of the digital video signal DV1 (DV2) based on the master clock MCK. Of the latch circuits 29, 30, 35, 36, the latch circuits 30, 36 are used to generate the digital video signals DL1 and DL2.

According to the configuration shown in FIG. 6, in the latch circuits 30 and 36 for detecting the logic level of the digital video signal DV1 (DV2), the digital video signal DL1 is also added.
By generating DL2 and DL2, the same effect as that of the first embodiment can be obtained with a simpler configuration than that of the first embodiment.

(3) Third Embodiment FIG. 6 is a block diagram showing a phase information extraction circuit applied to a television camera system according to a third embodiment of the present invention. That is, the phase information extraction circuits 52 and 5
3 is applied to the multiplexing circuit 10 in place of the phase extraction circuits 12 and 13 according to the first embodiment, outputs position detection signals P1 and P2, and outputs the digital video signal DL.
1, digital video signals DL3 and D instead of DL2
L4 is output.

That is, as shown in FIG. 8, the phase information extraction circuits 52 and 53 are the same as the phase information extraction circuits 12 and 13 according to the first embodiment. The reference clock CK (FIG. 8 (B)) is generated from FIG. 8 (A)), and the reference signals S1, S11, S2, S21 (FIGS. 8 (C) to (F) are generated from the reference clock CK and the Marster clock MCK. ))
Generate Further, the phase information extraction circuits 52 and 53 are
These reference signals S1, S11, S2 and S21 are output to the latch circuits 29, 30, 35 and 36, respectively, whereby the position detecting circuits 28 and 29 respectively output the digital video signals DV1 (DV2) (FIG. 8 (G)). The position detection signals P1 and P2 are generated.

The phase extraction circuit 1 according to the first embodiment
In addition to the configuration common to 2 and 13, the phase information extraction circuit 52
And 53 receive the reference signals S1 and S2 in delay circuits 54 and 55, respectively, where the master clock MCK
The reference signals S1 and S are delayed by the period Δt of ¼ cycle of the above, and the latch reference signals S12 and S22 (FIGS. 8 (H) and (I)) are generated.

As a result, the phase information extraction circuits 52 and 53
Is a latch reference signal S12 whose signal level rises at an intermediate timing when the signal levels of the reference signals S1 and S11 rise, and a latch reference signal S22 whose signal level rises at an intermediate timing when the signal levels of the reference signals S2 and S21 rise. Produces and. Further, the phase information extraction circuits 52 and 53 use the latch reference signal S12.
And S22 as a reference, the latch circuits 56 and 57 latch the digital video signal DV1 (DV2), thereby generating the digital video signals DL3 and DL4.

That is, in the above-described first and second embodiments, the timing for latching the digital video signal DV1 (DV2) to generate the position detection signals P1 and P2 and the digital video signals DL1 and DL2 are generated. Therefore, if the timing of latching the digital video signal DV1 (DV2) is the same, and the data transfer rate of the digital video signal DV1 is increased, stable operation may not be possible.

However, in the case of this embodiment, the digital video signal DV is generated in order to generate the position detection signals P1 and P2.
1 (DV2) is latched at a timing intermediate to that of the digital video signal DV1.
Latch (DV2) to digital video signal DL3,
By generating DL4, sufficient setup time and hold-up time can be secured, and stable operation can be achieved even when the data transfer speed is increased accordingly. Further, the delay time Δt can be selected according to the characteristics of the latch circuit or the like to cope with the case where the data transfer rate is further increased, and the phase margin for phase fluctuation, temperature fluctuation, etc. can be improved. .

According to the configuration shown in FIG. 7, the position detection signal P
1, digital video signal DV1 to generate P2
The digital video signal DV1 has an intermediate timing with respect to the timing of latching (DV2).
Latch (DV2) to digital video signal DL3,
By generating DL4, it is possible to more reliably multiplex digital video signals and the like.

(4) Other Embodiments In the above embodiment, the digital video signal D
Phase information extraction circuit 12 for both V1 and DV2
Although the case where the phase information is detected and processed by each of 13 and 13 is described, the present invention is not limited to this, and the digital video signal DV1 is generated in the same device and is held in a constant phase relationship with the master clock. Therefore, the processing by the phase information extraction circuit 13 may be omitted.

In the above embodiment, the reference signal S
Although the case where the digital video signals DV1 and DV2 are latched by the rising edges of S1, S11, S2, and S21 has been described, the present invention is not limited to this and may be latched at the falling edges.

Further, in the above-mentioned embodiment, the case where the position detection signals P1 and P2 are generated by the OR circuit from the latch result by the reference signals S1, S11, S2 and S21 has been described, but the present invention is not limited to this. An AND circuit can be applied when the phase information extraction circuit is formed by a negative logic circuit.

Further, in the above-described embodiment, the case where the latch results DL1 and DL2 by the reference signals S1 and S2 are selectively output from the selection circuit 47 has been described. However, the present invention is not limited to this, and one latch circuit is used for digital output. The video signals DV1 and DV2 may be latched, and the reference signals S1 and S2 that serve as a reference for the latch may be selectively supplied by the selection signal SL.

In the above embodiment, the case where the phase information of the digital video signal is detected by the two position detection circuits 28 and 34 simultaneously in parallel has been described.
The present invention is not limited to this, and the phase information extraction circuit may be formed by one position detection circuit, and the detection target of this position detection circuit may be sequentially switched to sequentially detect the phase information of the digital video signal.

Further, in these cases, one position detection circuit may be shared by two phases of phase information extraction circuits.
The two position detection circuits 28 and 34 may be shared by the two phase information extraction circuits. Furthermore, the reference signal generation circuit is 2
It may be shared by the phase information extraction circuits of the system.

Further, in the above-mentioned embodiment, the case where the digital video signals of two systems are multiplexed has been described, but the present invention is not limited to this, and further, when the digital video signals of a plurality of systems are multiplexed. It can be widely applied when multiplexing serial data of a plurality of systems. Further, in these cases, it can be applied to the case where serial data having different transmission rates are multiplexed and transmitted. That is, in this case, like the television camera system 61 shown in FIG. 9, the serial data DT1 output from the data terminal device 62 such as a tablet can be multiplexed and transmitted, and various control data and the like can be multiplexed. You can also do it.

In the above embodiment, the case where the digital video signal is multiplexed in bit units has been described. However, the present invention is not limited to this, and the digital video signal or the like is multiplexed in a specified data length as a unit. It can also be applied to the case.

Further, in the above-mentioned embodiment, the case where the multiplexed serial data is transmitted by a pair of optical fibers has been described, but the present invention is not limited to this, and it is transmitted bidirectionally by using one optical fiber. For example, it can be widely applied to the case of transmitting serial data multiplexed by various transmission paths.

[0072]

As described above, according to the present invention, the coincidence or non-coincidence of the logic levels is determined at the timing of consecutive edges with reference to the edge of the reference signal whose frequency is twice the clock frequency of the serial data. However, by setting the latch timing based on this determination result, asynchronous serial data can be multiplexed easily and reliably.

[Brief description of drawings]

FIG. 1 is a block diagram showing a phase information extraction circuit applied to a television camera system according to an embodiment of the present invention.

FIG. 2 is a block diagram showing an overall configuration of the television camera system of FIG.

FIG. 3 is a block diagram showing a multiplexing circuit of the camera head unit of FIG.

FIG. 4 is a signal waveform diagram for explaining the operation of the phase information extraction circuit of FIG.

5 is a signal waveform diagram for explaining the principle of detecting phase information in the phase information extraction circuit of FIG.

FIG. 6 is a block diagram showing a phase information extraction circuit applied to a television camera system according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a phase information extraction circuit applied to a television camera system according to a third embodiment of the present invention.

8 is a signal waveform diagram for explaining the operation of the phase information extraction circuit of FIG.

FIG. 9 is a block diagram showing a television camera system according to another embodiment of the present invention.

[Explanation of symbols]

1, 61 Television camera system 2, 3 Camera head unit 4 Camera control unit 10 Multiplexing circuit 11 Master clock generation circuit 12, 13, 50, 51, 52, 53 Phase information extraction circuit 20 Reference signal generation circuit 28, 34 Position Detection circuit 29, 30, 35, 36, 40, 41 Latch circuit 33 Protection circuit 46, 47, 48 Selection circuit

Claims (2)

[Claims] 1. A multiplexing device that multiplexes first and second serial data and converts the first and second serial data into serial data that is synchronized with a prescribed master clock, wherein the first and second serial data are multiplexed. Reference signal generating means for generating a reference signal having a clock cycle of ½ of the clock cycle of the serial data, and logic levels of the first serial data at timings of consecutive edges of the reference signal, respectively. Determination means for detecting whether the logic levels match or not, latching means for latching the first serial data and outputting a latch result at a timing according to the determination result of the determination means; And output means for switching and outputting the latched result of the second serial data at a prescribed timing. Duplex unit. 2. The first serial data is a digital video signal input via a prescribed transmission path, and the second serial data is a digital video signal. The multiplexing device according to.