JPH099055A - Image processing circuit - Google Patents

Abstract

PURPOSE: To prevent the increase of the capacity and the number of memories by dividing the memory reading a white reference board and acquiring/storing white data into plural banks. CONSTITUTION: White data are sequentially written into the bank 0 of the memory 19 for respective picture elements in a main scanning direction and white data of the whole read picture elements for one line are stored. When the acquirement of white data for one line is terminated, CPU 20 accesses to the memory 19. When the acquirement of white data is the first line, CPU 20 copies white data acquired to the bank 0 on a corresponding bank 1. When CPU 20 terminates the writing of white data for one line into the bank 1 of the memory 19, the read position of the white reference board 15 is changed, and white data is newly acquired. When the acquirement of white data for one line is terminated, CPU 20 accesses to the memory 19, reads white data stored in the first addresses of the banks 0 and 1 and writes data of a larger value into the first address of the bank 1. A similar processing is executed by updating the address by one.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image processing circuit incorporated in an image reading device which reads an original image using an image sensor.

[0002]

2. Description of the Related Art As an image reading device for reading an image using an image sensor, many products such as an image scanner and a facsimile device have been developed. The image sensor used in such an image reading apparatus is roughly classified into a CCD line sensor or a contact type image sensor. The CCD line sensor is an image sensor of a type in which a document image is optically reduced to form an image on the sensor and the image is read. On the other hand, the contact image sensor is an image sensor of a type in which an original image is formed on the sensor one by one and the image is read. These image sensors convert the light and shade of the original image into the level of an electric signal and output it as analog image data. The analog image data from the image sensor is converted into digital image data through an image processing circuit that performs analog-digital conversion (hereinafter referred to as A / D conversion), shading correction, MTF correction, and the like.

FIG. 4 is a block diagram simply showing the flow of image processing in a conventional image processing circuit. In FIG. 4, 1 is an image sensor. An analog signal processing unit 2 amplifies or clamps analog image data output from the image sensor 1, that is, a unit that processes the image data in an analog manner. Reference numeral 3 is an analog-digital conversion unit that converts an analog signal into a digital signal. The analog-to-digital converter 3 converts the analog-level image data read by the image sensor 1 into digital image data.

Reference numeral 4 is a shading correction unit. The processing content of the shading correction unit 4 will be described in detail later. Reference numeral 5 is a portion that performs image processing such as MTF correction, γ correction, and binarization processing, and is not directly related to the description of the present invention, and thus detailed description thereof is omitted. In brief, the MTF correction corrects blurring of a read image due to a decrease in MTF (Modulation Transfer Function) due to a spatial frequency characteristic of an optical system such as a lens or an image sensor in an image reading apparatus. However, this is a process for sharpening the image. The γ correction is a process of correcting the image data according to the γ characteristic of the device (printer, monitor, etc.) that outputs the read image data. The binarization process is a process of converting multi-valued image data into binary image data, such as when outputting read image data to a printer.

The shading correction performed by the shading correction section 4 will be described below. Shading correction is mainly due to the influence of the light amount distribution characteristics of the light source and the sensitivity variation between each pixel of the image sensor, and the output at each pixel of the image sensor varies even when the original image of a certain density is read, and the read image This is a process for suppressing a phenomenon such as uneven density. Shading correction is usually performed before reading the original image. The portion that performs the processing is shown in FIG. 4 as the shading correction unit 4.

Shading correction will be described with reference to FIG. FIG. 5 is a configuration diagram of a reading unit of a conventional image reading apparatus, which is an example configuration using a CCD line sensor as an image sensor. In FIG. 5, 6
Is a document placing member, and plate glass or the like is used. The original 7 is placed on the original placing member 6 and the image is read. 8
Is a carriage, which is an optical unit for reading the image of the original 7. An image sensor 9, a light source 10, a plurality of reflectors 11 to 13 and a lens 1 are provided in the carriage 8.
4 are equipped. When the light source 10 is turned on and the light is reflected on the image surface of the original 7 and returned to the carriage 8, the reflector 1
It is polarized by 1 to 13 and passes through the lens 14 to form an image on a pixel (light receiving element) on the image sensor 9. Pixels (light receiving elements) on the image sensor 9 according to the contrast of the original image
The amount of light focused on the image changes, and the image sensor 9 converts the amount of light into an electrical signal to detect the density of the image and reads the image. The carriage 8 moves in the direction of arrow d by a drive source (not shown) to read an image. Here, in the description of the present specification, the direction of arrow d is the reading sub-scanning direction. On the other hand, the direction perpendicular to this and perpendicular to the paper surface of FIG. 4 is the main scanning direction for reading.

FIG. 6 is a correspondence diagram between the reading area and the pixels of the image sensor 9 in the conventional image reading apparatus.
The pixels (light receiving elements) of the image sensor 9 are arranged in a line in the main scanning direction. For convenience, one pixel of the image sensor 9 and one pixel of the image to be read are described in a one-to-one correspondence, but when the image sensor 10 is a CCD line sensor as shown in FIG. 5, one pixel of the CCD line sensor is It is very small compared to 1 pixel of the image to read,
The pixel is optically reduced to form an image on one pixel of the CCD line sensor. The reading width in the main scanning direction depends on the number of pixels of the image sensor 9, and the reading width in the sub scanning direction depends on the movement amount of the carriage 8. Reference numeral 15 is a white reference plate, which is used when acquiring white data (Dw) during shading correction.

Now, in order to perform shading correction, white data (D
It is necessary to obtain w) and black data (Dk). The white data is the output level of each pixel of the image sensor 9 when the white reference plate 15 is read. The black data is, for example, the output level of each pixel of the image sensor 9 when the light source 10 is turned off. Therefore, the white data and the black data can be obtained with the carriage 8 moved to a position where the white reference plate 15 can be read, as shown in FIG.

FIG. 7 is a conceptual diagram of white data and black data in a conventional image reading apparatus. The image sensor output (image data) when the image is read basically changes between white data and black data according to the lightness and darkness of the original image as shown in FIG. By representing the level of the read image data by the ratio of the white data and the black data, the variation in the output between the pixels of the image sensor 9 when the document image having the constant density is read is corrected, and the image data is read. Can be corrected to a uniform level. When the image data (D) is handled with an 8-bit data amount, shading correction is generally performed by a correction formula such as formula (1).

Ds = (D−Dk) ÷ (Dw−Dk) × 255 Equation (1) The image data (D) is normalized by 8 bits by the equation (1), and the normalized image is obtained. The data (Ds) is the true image data. White data is for one line of read pixels in the main scanning direction (for the number of read pixels of the image sensor)
Desirable to get. Due to the influence of the light amount distribution characteristic of the light source, etc., the white level greatly varies among the pixels of the image sensor. This is because the white data is a highlight standard and is considered to be the maximum level of the image sensor output, and thus the level variation between pixels is large and the influence on the image is strong. On the other hand, the black data is a dark reference and is an output level in a state where light does not enter the image sensor 9, so that the influence as described above is small. Therefore, black data is acquired by, for example, sampling the level of a pixel in a state where the light source is turned off and holding the data. From this, regarding shading correction,
A memory that can store at least one line of read pixels in the main scanning direction (the number of read pixels of the image sensor) is required for acquiring white data.

[0011]

However, the conventional image processing circuit has the following problems. In the shading correction, if dust or dirt happens to be attached to the reading position of the white reference plate 15, for example, when acquiring white data, the output level of the pixel of the image sensor corresponding to the portion where the dust or dirt is attached is The deterioration is extremely low, which causes defects such as streaks in the read image. In order to suppress the occurrence of such a defect, a method is adopted in which white data is acquired over a plurality of lines while changing the reading position of the white reference plate 15. In that case, for example, in each pixel of the image sensor, the maximum value of the data acquired over a plurality of lines is set as white data, and finally the white data for one line is formed. However, by adopting such a method, the memory capacity for storing white data increases according to the number of lines to be read, and the number of pixels for one line increases with the increase in the reading resolution and the reading width. Then, there is a problem in that a single memory cannot be used and a plurality of memories are required, resulting in an increase in cost.

Therefore, an object of the present invention is to provide an image processing circuit which does not increase the capacity or the number of memories.

[0013]

According to the present invention, a memory for acquiring and storing white data when a white reference plate is read is divided into a plurality of banks.

[0014]

With the above configuration, white data is acquired in each of the plurality of banks under the condition that the reading positions of the white reference plate are different from each other. For example, in each read pixel, the maximum value of the white data acquired in the plurality of banks is It is stored in a predetermined bank.

[0015]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 1 is a block diagram of an image processing circuit according to an embodiment of the present invention. In FIG. 1, reference numeral 16 denotes an AD for converting analog image data output from an image sensor (not shown) and subjected to signal processing such as amplification by an analog signal processing unit (not shown) into digital image data.
It is a converter. The resolution of the AD converter 16 determines the data amount of the image data (D). In this embodiment, the resolution of the AD converter 16 is set to 8 bits, so that the maximum amount of image data is 256 levels.

Reference numeral 17 is a black memory for holding the value of black data (Dk) necessary for shading correction. Usually register latches are used. Reference numeral 18 denotes a shading calculation unit that calculates the formula (1). The shading calculation unit 18 includes data (D, D) necessary for the calculation of Expression (1).
k, Dw) is input and the calculation result is output as Ds. The memory 19 is a memory that acquires and stores white data (Dw) during shading correction. AB in the memory 19 indicates an address bus, and DB indicates a data bus. The configuration of the memory 19 will be described later.

Reference numeral 20 denotes C which controls the image reading apparatus.
It is PU. The CPU 20 controls the carriage (position control, speed control, etc.), controls the image reading timing, etc.
Performs various controls of the image reading device. AB in the CPU 20 indicates an address bus, and DB indicates a data bus. In this embodiment, the CPU 20 is an 8-bit microcomputer and the data bus has a bit length of 8 bits.

Reference numeral 21 is an address generator for generating an address signal to the memory 19, which is usually composed of a counter or the like. 22 designates the address of the memory 19 as the CPU
20 is a selector for selecting which of 20 and address generator 21 to give.

Here, when the logic of the input selection signal is high, the address signal of the CPU 20 is selected, and when it is low, the address signal of the address generator 21 is selected and given to the memory 19. As the selection signal, an address decoding circuit (not shown) decodes the address signal of the CPU 20 according to the allocation of the address space (CPU
It is obtained by determining whether the address signal of 20 is the address assigned to the memory 19).

When the CPU 20 issues an address signal corresponding to the address space assigned to the memory 19, the selection signal becomes high, and the CPU 20 can access the memory 19. Otherwise, the select signal is always low.

A unidirectional bus controller 23 controls connection / disconnection of signal lines. By the logic of signal A,
Controls connection / disconnection between input and output. The signal A is output from, for example, the I / O port of the CPU 20. Here, when the signal A is low, the input and output of the unidirectional bus controller 23 are connected. The unidirectional bus controller 23 controls the connection between the output of the AD converter 16 and the data bus of the memory 19. During shading correction, the signal A is set to low only when the white reference plate is read and white data is acquired (written) in the memory 19. The signal A also serves as the most significant bit of the address of the memory 19, and CP
The address of the memory 19 is composed of the address signal from the address generator 21 and the signal A except when the U 20 accesses the memory 19.

Reference numeral 24 is a bidirectional bus controller for controlling connection / disconnection of signal lines. The logic of the enable signal controls the connection / non-connection between the inputs and outputs of the bidirectional bus controller 24, and further the input / output is determined according to the logic of the input / output control signal. Here, when the enable signal is high, JK is connected, and when JK is connected, when the input / output control signal is low, J is input and K is output. Conversely, when JK is connected, it is input. When the output control signal is high, J is output and K is input. The enable signal and the input / output control signal are supplied to the CPU 2 according to the address space allocation in an address decoding circuit (not shown).
The address signal of 0 and the read / write signal (a signal (not shown) indicating whether the CPU 20 performs a read operation or a write operation with respect to the external I / O) are decoded (CPU 20
Is determined by whether or not the address signal of is the address assigned to the memory 19 and the access mode (read / write) of the CPU 20.

When the CPU 20 issues an address signal corresponding to the address space of the memory 19, the enable signal becomes high and the CPU 20 can access the memory 19, and the logic of the read / write signal changes the state of the input / output control signal. Decided.

Now, the structure of the memory 19 will be described with reference to FIG. In order to simplify the explanation, in this embodiment, the memory 19 has a configuration of 8192 × 8 bits, that is, a memory having a capacity of 8 KB (kilobytes). Memory 1
Address 9 is a hexadecimal number description, 0000h-1FFF
h. Therefore, the address of the memory 19 is 13 bits, and it is divided into two banks (bank 0, bank 1) by the logic (0 ... Low, 1 ... High) of the most significant bit and used. The capacities of bank 0 and bank 1 are both 4 KB. In FIG. 1, except when the memory 19 is accessed by the CPU 20, the most significant bit of the address (13 bits) of the memory 19 is the signal A, and the lower 12 bits are the address signal from the address generator 21. The bank is selected by the logic of A.

Acquisition of white data at the time of shading correction in the image processing circuit configured as described above will be described. At the time of explanation, the explanation will be given with reference to the flowchart of FIG. First, the CPU 20 moves the carriage 8 to the reading position of the white reference plate 15 (step 1, see FIG. 5).

The acquisition of the data (white data) obtained by reading the white reference plate 15 is to write the data into the bank 0 of the memory 19 via the unidirectional bus controller 23. Therefore, the signal A is set to low, the output of the AD converter 16 and the data bus of the memory 19 are connected, and the CPU
By prohibiting the access of the memory 19 by the memory 20, the selection signal is low, and the address of the memory 19 is configured by the signal A through the selector 22 and the address signal from the address generator 21. White data is stored in the bank 0 (address 0000) of the memory 19 one after another for each pixel in the main scanning direction.
h to 0FFFh), and the white data in all the read pixels for one line in the main scanning direction is stored in the memory 19 (step 3). The white data of the first read pixel of the read line is written at the address 0000h, and thereafter, for each pixel, is sequentially written at the updated address of 0001h and 0002h.

When the acquisition of the white data for one line in the main scanning direction to the memory 19 is completed, the CPU 20 next makes the memory 1
Access 9 During the access of the CPU 20, the selection signal becomes high, and the address of the memory 19 is given from the address bus (AB) of the CPU 20. The CPU 20
The memory 19 and the AD converter 16 must be disconnected so that the memory 19 can normally access the memory 19. Therefore, the signal A is switched to high (step 4).

When the white data is acquired in the first line (step 5), the CPU 20 reads the white data acquired in the bank 0 of the memory 19 and writes the read white data in the corresponding bank 1 address (the data of the bank 0). Processing is performed on all the read pixels for one line in the main scanning direction (step 6).

The address correspondence between bank 0 and bank 1 is a match of the lower 12 bits of the address. For example, the address 0000h of bank 0 is the address 1000 of bank 1.
Corresponds to h.

In this way, when the CPU 20 finishes writing the white data of all the read pixels for one line in the main scanning direction into the bank 1 of the memory 19, the reading position of the white reference plate 15 is changed to newly add the main scanning direction 1. Start acquiring white data for the line. The position of the carriage 8 is changed by the CPU 20 and the reading position of the white reference plate 15 is changed (step 1). As described above, in the acquisition of white data, the signal A is low, and the CPU 19 causes the memory 19
Access is prohibited, the selection signal is low (step 2). Then, new white data for one line in the main scanning direction is newly acquired in bank 0 of the memory 19 (step 3). At this point, the first acquired white data for one line in the main scanning direction (white data for the first line) is still stored in the bank 1 of the memory 19.

When the acquisition of the white data for one line in the main scanning direction to the memory 19 is completed, the CPU 20 accesses the memory 19 (during access, the selection signal is high, and the signal A
Is also high. ). The CPU 20 uses the address 00 of the memory 19
The white data stored in 00h and 1000h (the data of the first read pixel in each line when the white reference plate 15 is read) is read, and the white data having the larger value of the two white data is stored in the address of the memory 19. 100
Write to 0h. The same process is performed for all read pixels for one line in the main scanning direction while updating the address one by one. As a result, while the reading position is changed and the white reference plate 15 is read for two lines, the larger value of the data in each read pixel is stored in the bank 1 as white data (step 7).

When the acquisition of the white data is further continued (step 8), the carriage 8 is moved to change the reading position of the white reference plate 15 and the data is stored in the bank 0 of the memory 19, as described above. The maximum value of the white data in each read pixel is finally stored in the bank 1 of the memory 19 by acquiring and comparing the value with the white data stored in the bank 1 and writing the larger value in the bank 1. Is stored. With the above processing, the acquisition of white data is completed.

Thereafter, the actual image reading operation is started. At the time of image reading, the signal A is always high, and the read image data is input only to the shading calculation unit 18. In synchronism with this image data, the white data of the corresponding pixel is sequentially sent from the bank 1 of the memory 19 to the shading calculation unit 18, and together with the black data (Dk) held in the black memory 17, the expression (1) is obtained. The data (Ds) is sent to the image processing unit of the next stage while processing the calculation of 1 in real time. Further, the CPU 20 is prohibited from accessing the memory 19 during image reading, and the enable signal of the bidirectional bus controller 24 is always low. Therefore, in the memory 19, the data bus is connected only to the shading calculation unit 18.

As described above, the memory 19 is divided into two banks, and the bank 0 is the white data acquisition area and the bank 1 is the maximum white data storage area in each read pixel. It is possible to acquire over a plurality of lines, and it is possible to prevent a decrease in white data due to adhesion of dust or dirt at the reading position of the white reference plate and an influence (a streak or the like) on a read image due to the decrease.

In this embodiment, the maximum value of the acquired white data is stored in the bank 1. However, the average value of the acquired white data may be changed to white data, and various changes may be made. .

Although the memory is divided into two banks in the above description, the memory may be divided into two or more banks. After the white level for the number of lines corresponding to the number of banks is acquired by increasing the number of banks, the CPU 2
Since 0 may store the maximum value of each read pixel in a predetermined bank, the processing of the CPU 20 is reduced and the white data acquisition processing time is shortened. The number of banks may be optimized from the number of read pixels in the main scanning direction determined by the reading resolution and the reading width and the memory capacity.

[0038]

According to the image processing circuit of the present invention, the memory for acquiring and storing white data is divided into a plurality of banks so that the white data can be acquired over a plurality of lines, and the white reference plate is obtained. The white data value is prevented from lowering due to dust or dirt adhering to the reading position of the paper, and the resulting influence on the read image (such as streaks) is prevented, and the increase in the amount of white data acquisition memory and the increase in the number are prevented. It is effective for reduction.

[Brief description of drawings]

FIG. 1 is a configuration diagram of an image processing circuit according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a white data acquisition memory according to an embodiment of the present invention.

FIG. 3 is a flowchart showing a white data acquisition process at the time of shading correction according to an embodiment of the present invention.

FIG. 4 is a block diagram simply showing a flow of image processing in a conventional image processing circuit.

FIG. 5 is a configuration diagram of a reading unit of a conventional image reading device.

FIG. 6 is a correspondence diagram of a reading area and pixels of the image sensor 9 in a conventional image reading apparatus.

FIG. 7 is a conceptual diagram of white data and black data in a conventional image reading device.

[Explanation of symbols]

 16 AD Converter 17 Black Memory 18 Shading Calculation Unit 19 Memory 20 CPU 21 Address Generation Unit 22 Selector 23 Unidirectional Bus Controller 24 Bidirectional Bus Controller

Claims (5)

[Claims] 1. An image processing circuit incorporated in an image reading apparatus for reading an original image using an image sensor, and performing analog-digital conversion processing, shading correction processing, MTF correction processing, etc. on image data read by the image sensor. An image processing circuit comprising a memory for acquiring and storing white data when a white reference plate is read in the shading correction process, wherein the memory is divided into a plurality of banks. 2. When white data is acquired over a plurality of lines by changing the reading position of the white reference plate, white data having different reading positions of the white reference plate is acquired in each of the plurality of banks except a predetermined bank. The image processing circuit according to claim 1, wherein: 3. When white data is acquired over a plurality of lines by changing the reading position of the white reference plate, white data having different reading positions of the white reference plate is acquired in each of the plurality of banks except a predetermined bank. The image processing circuit according to claim 1, wherein the predetermined bank stores data calculated from white data acquired by another bank. 4. When white data is acquired over a plurality of lines by changing the reading position of the white reference plate, white data having different reading positions of the white reference plate are acquired in each of the plurality of banks. The image processing circuit according to claim 1. 5. When white data is acquired over a plurality of lines by changing the reading position of the white reference plate, white data having different reading positions of the white reference plate are acquired in each of the plurality of banks, and as a result, The image processing circuit according to claim 1, wherein data calculated from white data acquired over a plurality of lines is stored in a predetermined bank of the plurality of banks.