JPH10107175A - Package for semiconductor device - Google Patents

Abstract

(57) Abstract: Provided is a package that enables stable power supply to a semiconductor chip without increasing the number of external pins for a highly integrated semiconductor device. A plurality of signal pins are protruded and mounted on a side surface, and a _VDD conductor having a large surface area and a GND conductor having a large surface area are provided on a bottom surface. Although not shown in FIG. 1, all VDD on the internal semiconductor chip
The pad is electrically connected to the surface of the package 1 through a plurality of bonding wires and a conductor plate for VDD having a wide cross-sectional area and a conductor for VDD. Similarly, all GNDs on the internal semiconductor chip are connected. The pad is electrically connected to the surface of the package 1 via a plurality of bonding wires, a GND conductor plate having a wide cross-sectional area, and a GND conductor. As a result, the impedance between the semiconductor chip and the external power supply line is reduced, and power is supplied stably without increasing the number of external pins.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a package for a semiconductor device.

[0002]

2. Description of the Related Art FIG. 4 is a perspective view of a lower surface of an external appearance of an example of a conventional semiconductor device package (referred to as a first conventional example). As shown in FIG. 4, the conventional package 21 has a plurality of signal pins 22 protruding from the package 21 and one or a plurality of _VDD pins.
The (positive power supply potential) pin 23 and the GND (ground potential) pin 24 are mounted similarly to the signal pin 22. FIG. 5 is a cross-sectional / top perspective view of the package 21 when the package 21 is cut along the line BB. 5 shows the internal configuration of the package 21, in which signal pins 22, _VDD pins 23 and GND pins 24 are extended inside the package 21, and the bonding wires 2
5 are connected to a signal pad, a _VDD pad, a GND pad (these pads are not shown), etc. on the internal semiconductor chip 26, respectively. In this conventional example, the degree of integration of the circuits on the semiconductor chip 26 is increased, and when many circuits, especially output buffers and the like, operate simultaneously, the power supply potential fluctuation becomes large and the semiconductor device malfunctions. There is a risk of inviting. On the other hand, in order to stabilize the power supply potential, it is necessary to arrange a large number of power supply pads and power supply pins on the semiconductor chip 26 to lower the impedance of the power supply line. There is a problem that the size of the apparatus is increased.

[0003] An example of the first prior art in which the aim is to reduce the fluctuation of the GND potential in order to suppress the fluctuation of the GND potential is disclosed in Japanese Unexamined Patent Publication No. 3-2700063 (the second prior art). There is an example). FIG. 6 is a bottom perspective view of the appearance of the second conventional example. As shown in FIG. 6, a plurality of signal pins 32 are
Are protrudingly mounted, and one or more V
_{The DD} pins 33 are mounted similarly to the signal pins 32, and a conductor plate 34 is provided on the bottom surface of the package. Also,
FIG. 7 is a cross-sectional / top perspective view of the package 31 seen through the conventional example cut along the line CC. FIG.
3 shows the internal configuration of the package 31. The signal pins 32 and the _VDD pins 33 are extended inside the package 31, and the semiconductor chips 36 inside the package 31 are respectively connected by bonding wires 35. It is connected to the upper signal pad and the V _DD pad (these pads are not shown). A plurality of conductor protrusions 37 are connected to the conductor plate 34, and a plurality of GNDs arranged on the semiconductor chip 36 and an upper portion of the conductor protrusions 37 are connected to the conductor plate 34.
Pads (not shown) are connected by bonding wires 35, respectively. In this conventional example,
Unlike the case of the first conventional example described above, the connection to the GND potential is performed not via the GND pin but via the GND conductor plate 34 disposed on the bottom surface.
As a result, the impedance of GND is reduced, and
The fluctuation of the D potential is suppressed.

Japanese Patent Laid-Open Publication No. 60-20524 discloses an example in which improvements are made for the purpose of stable power supply and effective use of external pins as in the case of the second conventional example. There is a conventional example (referred to as a third conventional example). FIG. 8 is a cross-sectional / top perspective view of the appearance of the third conventional example. As shown in FIG. 8, inside the package 41, a semiconductor chip 42 is surrounded.
A _VDD conductor 43 and a GND conductor 44 are arranged one by one, and a plurality of signal conductors 45 are arranged around the conductor 43 and the GND conductor 44. V on the semiconductor chip 42
_DD pad (not shown) is connected to bonding wire 4
6 are all connected to the V _DD conductor 43.
A V _DD pin 47 extending directly below the _DD conductor is connected to the outside of the package 41. Similarly, a plurality of GND pads (not shown) arranged on the semiconductor chip 42 are all connected to the GND conductor 44 by bonding wires 46, and are connected by GND pins 48 extending directly below the GND conductor. It is connected to the outside of the package 41. The V _DD pin 47 and the GND pin 4
The number of 8 is at least one each. A plurality of signal pads (not shown) arranged on the semiconductor chip 42 are connected to the plurality of signal conductors 45 in a one-to-one manner, and extend directly below each signal conductor. Externally connected via a signal pin 49. Further, in this conventional example, the _VDD pin 47 and the GND pin 48
Has been proposed, and the use of a part of the signal pin 49 instead is proposed. In the third conventional example, a plurality of power supply pads on the semiconductor chip 42 are once connected to a power supply conductor inside the package 41, and further connected collectively to the outside via a small number of pins. Accordingly, it is an object to provide a stable power supply while effectively using the external pins.

[0005]

In the above-mentioned conventional package for a semiconductor device, in the case of the first conventional example, power is supplied using a power supply pin in the same manner as a signal pin. The power supply pads on the chip and the power supply pins are connected only in a one-to-one relationship. In the case of the second conventional example,
The V _DD power supply is still performed by the V _DD pin similar to the signal pin, and the V _DD pad and the V _DD pin on the semiconductor chip are substantially in a one-to-one relationship as in the first conventional example. In this conventional example, the stable supply of the power supply / _VDD power is not realized by any means other than increasing the number of the power supply pins / V _DD pins. As the degree of integration of the semiconductor device increases, the number of corresponding power supply pins / _VDD pins must be increased in order to maintain a stable supply of the power supply / _VDD power supply. However, there is a drawback that the occupied area of the package increases and the package becomes larger.

Further, in the case of the third conventional example, power supply to all the power supply pads depends on a small number of pins having a small cross-sectional area, thereby achieving a structure that achieves effective use of the pins. Therefore, when the degree of integration of the semiconductor chip is further increased and the power supply is increased, there is a disadvantage that the impedance of the pin cannot be ignored and the stable supply of the power cannot be performed.

An object of the present invention is to reduce the impedance of a V _DD / GND power supply line by combining a large number of bonding pads and a conductor having a large cross section in a highly integrated semiconductor device, thereby reducing the number of external pins. An object of the present invention is to provide a semiconductor device package capable of stably supplying power to a semiconductor chip without increasing the number of semiconductor devices.

[0008]

The semiconductor device package of the present invention occupies a larger area on the surface of the package than the other external pins corresponding to the respective sectional areas. At least a high-potential power supply conductor and a low-potential power supply conductor to be arranged are provided, and the semiconductor chip inside the package and an external power supply line are electrically connected via the high-potential power supply conductor and the low-potential power supply conductor. It is characterized by being connected.

The high-potential power supply conductor plate having a large surface area, a large-surface-area insulator, and a large-surface-area high-potential power supply plate are sequentially stacked on the lower surface of the semiconductor chip inside the package. A power supply conductor electrically connected to the high-potential power supply conductive plate and led out to a package surface; the low-potential power supply conductor is electrically connected to the low-potential power supply conductive plate; Alternatively, the lead may be led out to the surface of the package through a cutout portion of the high-potential power supply conductor plate.

The high potential power supply may be defined as a positive potential power supply and the low potential power supply may be defined as a ground potential, or the high potential power supply may be defined as a positive potential power supply,
The low potential power supply may be defined as a negative potential power supply. Alternatively, the high potential power supply may be defined as a positive potential power supply, and the low potential power supply may be defined as a positive potential power supply having a lower potential than the positive potential power supply.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a bottom perspective view of the external appearance of an embodiment of the present invention. As shown in FIG. 1, the package 1 of the present embodiment has a plurality of signal pins 2 protrudingly mounted on the side surface of the package 1 and a large surface area V _DD conductor 3 and a plurality of signal pins 2 on the bottom surface. A large-area GND conductor 4 is provided. FIG. 2 is a cross-sectional / top perspective view of the package 1 seen through the mold package 1 cut along line AA. Section of Fig. 2 /
In the top perspective perspective view, the internal configuration of the package 1 is shown, in which a semiconductor chip 5, a GND conductor plate 6 and a _VDD conductor plate 7 are provided, and a signal pin 2 is provided from an external side surface. Is inserted inside. The semiconductor chip 5 uses the GND conductor plate 6 as an island and
It is fixed on the conductor plate 6 for D. Conductor plate for GND 6
Has an area larger than the area occupied by the semiconductor chip 5, and a GND bonding region is arranged around the semiconductor chip 5. The GND conductor plate 6 has V
_The insulator 8 is fixed on the upper part of the _DD conductor plate 7 with the insulator 8 interposed therebetween. The conductor plate 7 for _VDD has an area larger than the area occupied by the conductor plate 6 for GND.
Is provided with a _VDD bonding region. One end of the signal pin 2 is fixed via an insulator 8 outside the _VDD bonding region. At the bottom of the GND conductor plates 6 and V _DD conductor plate 7, and each GND conductor 4 and V _DD conductor 3 of a rectangular parallelepiped is joined, their lower ends, as power supply contact of the large area, respectively, It is exposed on the bottom of the package 1. In addition, the joint part of the conductor plate 6 for GND and the conductor 4 for GND,
Junction and the V _DD conductor plate 7 and the V _DD conductor 3 has a Hirodan area as well. The term “wide area or wide cross-sectional area” as used herein means an area where the impedance in the area / cross-sectional area can be ignored when a current flows through the conductor cross section. Indicates an area having a value larger than the cross-sectional area of. The arrangement position of the V _DD conductor plate 7 is partially cut out so as not to come into contact with the GND conductor 4.

A plurality of GND pads 10 arranged on the upper portion of the semiconductor chip 5 are connected to the GND conductor plate 6 by bonding wires 9, and are connected to the outside of the GND conductor 4 through wide-area contacts of the GND conductor 4. Connected to GND line. Similarly, a plurality of V _DD pad 11 disposed on top of the semiconductor chip 5 is connected to all the bonding wires 9 to V _DD conductor plate 7, through the contact of the large area of the V _DD conductor 3 Connected to external _VDD line. The plurality of signal pads 12 on the semiconductor chip 5 are connected to the corresponding signal pins 2 by bonding wires 9, respectively, and are connected to external signal lines via the signal pins 2.

By configuring the package 1 as described above, it is possible to significantly reduce the impedance of the V _DD / GND power supply line inside the package, thereby supplying power to the semiconductor device from the outside. In this case, there is an effect that stable power supply can be performed even when the corresponding semiconductor chip 5 is a highly integrated semiconductor chip.

[0015]

As described above, the present invention has a structure in which all the V _DD pads and the GND pads on the semiconductor chip are connected to the V _DD conductor and the GND conductor in the package, respectively. _DD conductor and GN
The number of power supply pins is increased by having a structure in which electrical connection from the D conductor to the package surface is performed by a conductor having a wide cross-sectional area and connection to an external power supply line is performed by a contact conductor having a wide area. Without arranging a large number of _VDD pads and GND pads on a semiconductor chip, it is possible to reduce the impedance at the bonding wire and its connection point as a whole,
In addition, the connection between the external power supply line and the power supply pad on the semiconductor chip can be performed with low impedance, and the integration degree of the semiconductor chip inside the package can be increased without increasing the number of pins of the package. Regardless of the above, there is an effect that the power supply can be performed stably.

[Brief description of the drawings]

FIG. 1 is a bottom perspective view of one embodiment of the present invention.

FIG. 2 is a sectional / top transparent perspective view of the first embodiment.

FIG. 3 is a cross-sectional / lower-surface perspective view of the first embodiment.

FIG. 4 is a bottom perspective view of a first conventional example.

FIG. 5 is a sectional / top transparent perspective view of the first conventional example.

FIG. 6 is a bottom perspective view of a second conventional example.

FIG. 7 is a cross-sectional / top perspective view of the second conventional example.

FIG. 8 is a sectional / top transparent perspective view of a third conventional example.

[Explanation of symbols]

1, 21, 31, 41 Package 2, 22, 32, 49 Signal pin 3, 43 _VDD conductor 4, 44 GND conductor 5, 26, 36, 42 Semiconductor chip 6 GND conductor plate 7 _VDD conductor plate Reference Signs List 8 insulator 9, 25, 35, 46 bonding wire 10 GND pad 11 _VDD pad 12 signal pad 23, 33, 47 _VDD pin 24, 48 GND pin 34 conductor plate 37 conductor protrusion 45 signal conductor

Claims (5)

[Claims] 1. A high-potential power supply conductor and a low-potential power supply arranged such that an occupied area on a package surface occupies a larger surface area in comparison with other external pins in accordance with respective cross-sectional areas. A semiconductor device package comprising at least a conductor and electrically connecting a semiconductor chip inside the package and an external power line via the high potential power conductor and the low potential power conductor. 2. A high-potential power supply conductor plate having a large surface area, a large-surface-area insulator, and a large-surface-area high-potential power supply conductor plate sequentially laminated on a lower surface of a semiconductor chip inside a package. A power supply conductor is electrically connected to the high-potential power supply conductive plate and led out to the package surface, and the low-potential power supply conductor is electrically connected to the low-potential power supply conductive plate, and the insulator and 2. The semiconductor device package according to claim 1, wherein the package is led out to a surface of the package through a cutout portion of the high-potential power supply conductor plate. 3. The semiconductor device package according to claim 1, wherein the high potential power supply is defined as a positive potential power supply, and the low potential power supply is defined as a ground potential. 4. The semiconductor device package according to claim 1, wherein said high potential power supply is defined as a positive potential power supply, and said low potential power supply is defined as a negative potential power supply. 5. The semiconductor device according to claim 1, wherein the high potential power supply is defined as a positive potential power supply, and the low potential power supply is defined as a positive potential power supply having a lower potential than the positive potential power supply. package.