JPH10107221A - Semiconductor memory device and method of manufacturing the same - Google Patents

Abstract

[PROBLEMS] To secure the capacity of a filter capacitor in a DRAM power supply circuit while keeping the occupied plane area small. SOLUTION: COB (Capasitor Over the Bitline)
The storage node 15 of the DRAM having the structure is used as a first electrode layer 15a, and the bit line 11 and the cell plate 17 are used as second electrode layers 11a and 17a, respectively, to constitute a filter capacitor. Therefore, two capacitors C1 and C2 connected in parallel with each other are formed above and below the first electrode layer 15a, and these constitute one filter capacitor. The dielectric film 14a of the lower capacitor C1 is
The storage contact 13 is formed using the sidewall insulating film 14.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having a memory cell region having a semiconductor memory element and a peripheral circuit region having a filter capacitor such as a power supply circuit. And its manufacturing method.

[0002]

2. Description of the Related Art Generally, in a semiconductor integrated circuit, a filter capacitor is provided in a peripheral circuit region of a memory cell region in order to remove noise superimposed on a power supply voltage.

Specifically, for example, Japanese Patent Application Laid-Open No. 5-160341
Japanese Patent Application Laid-Open Publication No. H11-163873 discloses that an n-type semiconductor region formed on a substrate has an MO.
An SFET is formed, and a conductive film is formed via a dielectric film on a p-type semiconductor region which is a junction isolation layer of an n-type semiconductor region formed on a substrate. An integrated circuit device in which a noise removing capacitor is constituted by the semiconductor region described above. This noise removing capacitor has a considerably large surface area and is formed in the junction separation layer, which is a region where most of the capacitor is idle.

In Japanese Patent Application Laid-Open No. 61-218155, a power supply line for supplying a power supply voltage and a ground line for supplying a ground potential are formed so as to overlap each other in the same wiring region via an interlayer insulating film. A semiconductor integrated circuit device in which the capacitance between the two functions as a bypass capacitor is disclosed. Also in this case, it is possible to form a bypass capacitor functioning as a filter capacitor without increasing the chip size.

[0005]

By the way, when forming the filter capacitor, in addition to suppressing the increase in the chip size as described above, in addition to the reduction in the circuit layout and the manufacturing process, this filter capacitor is taken into consideration. It is desired to form a filter capacitor in a peripheral circuit portion of a memory cell portion where a semiconductor element which is a main component of a semiconductor integrated circuit is formed with good consistency with the semiconductor element.

For example, as a method of manufacturing a filter capacitor in consideration of the matching with the semiconductor element, when a memory cell is formed of a DRAM including a MOSFET and a capacitor as the semiconductor element, a MOSFE is used.
Forming the constituent member of T and depositing the material of the constituent member on the formation site of the filter capacitor,
A dielectric film constituting a memory capacitor of a RAM and a two-layer electrode film sandwiching the same are formed, and a dielectric film constituting a filter capacitor and a two-layer electrode film sandwiching the same are formed.
Forming a layer of electrode film has been performed.

However, when the semiconductor element and the filter capacitor are simultaneously formed as described above, the required capacitance is ensured even if the dielectric film of the filter capacitor is formed as thin as possible to increase the capacitance. Therefore, there is a problem that the ratio of the area of the filter capacitor to the chip area is increased, which in turn causes an increase in chip size.

For example, an area of 300 μm × 300 μm or more is usually required to secure a capacitance of several tens of pF or more necessary for effectively removing noise.
In a semiconductor memory device with a high degree of integration, the filter capacitor occupies an area sufficient to produce tens or more circuit elements.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a filter circuit in which a filter capacitor occupied area in a peripheral circuit area is kept small, a sufficient noise elimination function of a filter capacitor is secured, and a semiconductor element and a filter in a memory cell area are provided. An object of the present invention is to provide a semiconductor memory device in which a capacitor is formed with good matching and a method of manufacturing the same.

[0010]

According to the present invention, there is provided a semiconductor memory device having a memory cell region and a peripheral circuit region having a capacitor, wherein the capacitor is a first electrode layer and a first electrode layer. The upper and lower surfaces of the one electrode layer are configured to have a second electrode layer facing each other via a capacitor dielectric film.

In one embodiment of the semiconductor memory device according to the present invention, a concave portion is formed on the upper surface of the first electrode layer, and the first electrode layer is formed on the entire surface including the side surface of the concave portion by the capacitor dielectric film. And the second electrode layer.

In one embodiment of the semiconductor memory device according to the present invention, each of the memory cells is provided with an access transistor and a memory capacitor, and the memory capacitor is substantially less than a bit line in the memory cell region. Is also formed at an upper layer position, and the first electrode layer of the capacitor in the peripheral circuit region is made of the same material as the lower electrode formed at a hierarchical position corresponding to a lower electrode which is a storage node of the memory capacitor. A portion of the second electrode layer facing the lower surface of the first electrode layer of the capacitor in the peripheral circuit region is formed at a hierarchical position corresponding to the bit line in the memory cell region. Upper surface of the first electrode layer of the capacitor in the peripheral circuit region, the conductive film being made of the same material as that of the bit line. It said portion of the second electrode layer to Oite facing is composed of a conductive film of the upper electrode of the same material formed on the hierarchical position corresponding to the upper electrode is a cell plate of the memory capacitor.

According to a method of manufacturing a semiconductor memory device of the present invention, an access transistor forming a memory cell is formed in a region to be a memory cell region of a semiconductor substrate, and an access transistor is formed on the semiconductor substrate in the memory cell region and the peripheral circuit region. Forming a first insulating film serving as an interlayer insulating film over the entire surface of the semiconductor device; forming a first opening reaching the one diffusion layer of the access transistor in the first insulating film; Forming a first conductive film over the entire surface of the first insulating film including the inside of the opening, and processing the first conductive film into a bit line shape in the memory cell region; Processing the first conductive film into a predetermined pattern in a peripheral circuit region, and forming an interlayer insulating film on the entire surface of the semiconductor substrate in the memory cell region and the peripheral circuit region Forming a second insulating film, insulating the second in the memory cell region layer and the first
Forming a second hole for making contact with the other diffusion layer of the access transistor in the insulating film, and forming the second insulating film on the first conductive film in the predetermined pattern in the peripheral circuit region. Forming a third opening in the film, forming a third insulating film over the entire surface including the inside of the second and third openings, and masking the peripheral circuit region to form the memory. The third in the cell area
Anisotropically etching said insulating film to form a side wall insulating film made of said third insulating film on the side surface of said second hole, and the entire surface including the inside of said second and third holes. Forming a second conductive film in the memory cell region, processing the second conductive film into a shape of a lower electrode of a memory capacitor, and forming the second conductive film in a capacitor in the peripheral circuit region. Processing into a shape of a first electrode; forming a fourth insulating film on the second conductive film in the memory cell region and the peripheral circuit region; Forming a third conductive film over the entire surface of the semiconductor substrate in the region, processing the third conductive film into the shape of an upper electrode of a memory capacitor in the memory cell region, and forming the third conductive film in the peripheral circuit region. The third conductive film and a step of processing the shape of the second electrode of the capacitor in.

[0014]

In the semiconductor memory device of the present invention, the capacitor provided in the peripheral circuit region has three electrode films, and in these three electrode films, an intermediate first electrode layer has upper and lower surfaces. Thus, two capacitors are substantially formed by capacitive coupling with the second electrode layer. That is, 1
Since substantially two capacitors are formed in an area occupied by one capacitor, for example, by electrically connecting each second electrode layer at one end and using the two capacitors in a state of parallel connection, one capacitor is formed. A capacitor having a capacitance substantially twice as large as the area occupied by the capacitor is formed, and a sufficient capacitance can be secured even if the occupied plane area of the capacitor is significantly reduced.

In the method for manufacturing a semiconductor memory device according to the present invention, for example, a memory cell in which a memory cell is formed from an access transistor and a memory capacitor in a memory cell region.
When a RAM is formed, the capacitors in the peripheral circuit region are formed with substantially the same process as the configuration of the memory cell region, as described below.

That is, first, for the second electrode layer under the capacitor in the peripheral circuit region, a first conductive film is formed on the entire surface of the interlayer insulating film formed in the memory cell region and the peripheral circuit region, In the cell region, the first conductive film is processed into a bit line shape, and in the peripheral circuit region, the first conductive film is processed into a predetermined pattern to form a second electrode layer below the capacitor.

Next, regarding the capacitor dielectric film under the capacitor in the peripheral circuit region, an insulating film for forming a sidewall insulating film of a storage contact in the memory cell region is replaced with a capacitor dielectric film under the capacitor in the peripheral circuit region. Use for

Next, as for the first electrode layer of the capacitor in the peripheral circuit region, a second conductive film is formed on the entire surface of the second interlayer insulating film formed in the memory cell region and the peripheral circuit region. In the cell region, the second conductive film is processed into the shape of the lower electrode which is the storage node of the memory capacitor, and in the peripheral circuit region, the second conductive film is processed into the shape of the first electrode of the capacitor.
You.

Next, as for the capacitor dielectric film on the capacitor in the peripheral circuit region, an insulating film for forming the capacitor dielectric film of the memory capacitor in the memory cell region is used.

As for the second electrode layer above the capacitor in the peripheral circuit region, a third conductive film for forming an upper electrode which is a cell plate of the memory capacitor in the memory cell region is used.

As described above, in the method of manufacturing a semiconductor memory device according to the present invention, the capacitor in the peripheral circuit
It is formed with good consistency using a material for forming the configuration of the M memory cell region. At this time, as the capacitor in the peripheral circuit region, a capacitor in which the upper and lower second electrode layers are capacitively coupled to the intermediate first electrode layer, respectively, is formed. Therefore, a capacitor having a capacitance substantially twice as large as the plane area occupied by one capacitor is formed, and a sufficient capacitance can be secured.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

In this embodiment, noise superimposed on a DRAM memory cell region (hereinafter, simply referred to as "memory cell region") including a MOS transistor serving as an access transistor and a memory capacitor and a power supply circuit is removed. For example, a DRAM including a peripheral circuit region of a memory cell region including a filter capacitor provided in a power supply circuit (hereinafter, simply referred to as a “peripheral circuit region”) and a method of manufacturing the DRAM will be described.

FIG. 1 is a schematic sectional view showing a DRAM according to the present embodiment. FIG. 1A is a schematic sectional view showing a memory cell region, and FIG. 1B is a schematic sectional view showing a peripheral circuit region. It is a schematic sectional drawing which shows the part of a filter capacitor. FIG. 2 is a schematic cross-sectional view of the memory cell region substantially orthogonal to FIG.

The DRAM of the present embodiment has a so-called COB (Capacitor Over the Bitline) structure in which a memory capacitor is formed substantially above a bit line. In this DRAM, FIG. 1 (a) and FIG.
As shown in FIG. 5, each element formation region is defined by a field shield element isolation structure 21 formed on a p-type silicon semiconductor substrate 1, and a MOS transistor is formed in this element formation region. A memory capacitor electrically connected to the impurity diffusion layer is formed.

In the field shield element isolation structure 21, a shield plate electrode 3 made of a polycrystalline silicon film is formed on the silicon oxide film 2, and a silicon oxide film 4 is formed so as to cover the shield plate electrode 3. Each element formation region is electrically separated from the other element formation regions by fixing the potential of the shield plate electrode 3.

In the memory cell region, a gate oxide film 6 is formed on the entire surface of the silicon semiconductor substrate 1 in the element formation region.
Is formed, and a gate electrode 7 having a predetermined pattern made of polycrystalline silicon is formed on the gate oxide film 6 in the element formation region. Further, a cap insulating film 22 is formed on the upper surface of the gate electrode 7, and a sidewall protective film 2 which is an insulating film is formed on the side surface.
3 are formed, and the gate electrode 7 is covered with a cap insulating film 22 and a side wall protective film 23.

Then, n-type impurities are introduced on both sides of each gate electrode 4 on the silicon semiconductor substrate 1 to form a pair of impurity diffusion layers 24 serving as source / drain diffusion layers, and the gate electrode 7 and the pair of impurities are formed. A MOS transistor is constituted by the diffusion layer 24.

Further, in order to ease the positional accuracy when forming a contact hole for each impurity diffusion layer 24, a pad for contact extraction is provided on the surface of the silicon semiconductor substrate 1 where the impurity diffusion layer 24 is formed. A polycrystalline silicon film 8 is patterned. This pad polycrystalline silicon film 8 forms a cap insulating film 22 covering gate electrode 7.
And extends from the side wall protective film 23 to the field shield element isolation structure 21 or between the cap insulating film 22 and the side wall protective film 23 covering each gate electrode 7. Side wall protective film 23
Or on the field shield element isolation structure 21.

Further, an interlayer insulating film 9 which is a silicon oxide film is formed on the entire surface, and pad polycrystalline silicon film 8 is buried in interlayer insulating film 9. The interlayer insulating film 9 includes
A contact hole 10 serving as a bit contact is formed in the interlayer insulating film 9 so that a part of the surface of the pad polycrystalline silicon film 8 formed on one of the pair of impurity diffusion layers 24 is exposed. A wiring layer 11 which fills the inside of the contact hole 10 and is arranged at substantially equal intervals on the interlayer insulating film 9 and serves as a bit line is pattern-formed. This wiring layer 11 is electrically connected to the one impurity diffusion layer 24 via the pad polycrystalline silicon film 8.

Further, the interlayer insulating film 1 is formed on the interlayer insulating film 9.
2 are formed, and the wiring layer 11 is embedded in the interlayer insulating film 12. The interlayer insulating film 12 and the interlayer insulating film 9 include:
A contact hole 13 serving as a storage contact penetrating the interlayer insulating film 12 and the interlayer insulating film 9 so that a part of the surface of the pad polycrystalline silicon film 8 formed on the other of the pair of impurity diffusion layers 24 is exposed. Are formed. A sidewall insulating film 14 which is a silicon oxide film is formed on a side surface in the contact hole 13. The storage node is formed of polycrystalline silicon which fills the contact hole 13 and has a predetermined shape on the interlayer insulating film 12. The electrode 15 is patterned. This storage node electrode 1
Reference numeral 5 is electrically connected to the other impurity diffusion layer 24 via the pad polycrystalline silicon film 8, and is electrically insulated from the wiring layer 11 by the sidewall insulating film 14.

Then, a dielectric film 16 made of, for example, an NO composite film is formed so as to cover storage node electrode 15, and cell plate electrode 1 is formed on dielectric film 16.
7 are formed. Here, the storage capacitor is constituted by the storage node electrode 15 and the cell plate electrode 17 sandwiching the dielectric film 16.

As described above, the MOS transistor, the memory capacitor, the respective wiring layers, the interlayer insulating films, and the like are formed to form the DRAM in the memory cell region.

On the other hand, as shown in FIG. 1B, the filter capacitor in the peripheral circuit region has three electrode films, namely, a lower electrode layer 11a, an intermediate electrode layer 15a and an upper electrode layer 17a.
a, and each of the dielectric films 14a and 16a, and the lower electrode layer 11 is disposed below the intermediate electrode layer 15a via the dielectric film 14a.
a, an upper electrode layer 17a is disposed above the intermediate electrode layer 15a via a dielectric film 16a, and the lower electrode layer 11a and the upper electrode layer 17a are electrically connected at one end thereof. Thus, capacitors C1 and C2 are formed.

Here, in the capacitors C1 and C2,
Each layer constituting the capacitors C1 and C2 is formed at substantially the same hierarchical position as each corresponding layer of the DRAM in the memory cell region.

That is, the filter capacitor is
First, the silicon oxide film 2, the shield plate electrode 3, and the silicon oxide film 4, which are the respective layers constituting the field shield element isolation structure 21 in the peripheral circuit region, are formed on the silicon semiconductor substrate 1 and have substantially the same hierarchical position. A silicon oxide film 2a, a polycrystalline silicon film 3a, and a silicon oxide film 4a are formed in layers on the silicon oxide film 4a. Further, on the uppermost silicon oxide film 4a, the same material and the same layer position as the interlayer insulating film 9 are used. , An interlayer insulating film 9a is formed by lamination.

On the silicon oxide film 4, a lower electrode layer 11a is pattern-formed at substantially the same hierarchical position as the wiring layer 11 in the memory cell region, and a part of the surface of the lower electrode layer 11a is partially removed. An opening 18 is formed by patterning so as to be exposed, and the interlayer insulating film 1 of the DRAM is formed.
2 and an interlayer insulating film 1 at substantially the same hierarchical position
2a is patterned.

Further, on the interlayer insulating film 12a and the opening 18
Inside, a dielectric film 14a made of the same material as the above-described sidewall insulating film 14 in the memory cell region is formed. At this time, the surface of the dielectric film 14a has a concave shape on the lower electrode layer 11a following the shape of the interlayer insulating film 12a.

Further, on the dielectric film 14a, an intermediate electrode layer 15a is pattern-formed at substantially the same hierarchical position with the same material as the storage node electrode 15 in the memory cell region described above. At this time, in the intermediate electrode layer 15a, similarly to the dielectric film 14a, a concave portion is formed on the surface according to the shape of the dielectric film 14a.

Further, on the intermediate electrode layer 15a, a dielectric film 16a is formed of the same material as the above-described dielectric film 16 in the memory cell region at substantially the same hierarchical position. At this time, in the dielectric film 16a, similarly to the intermediate electrode layer 15a, a concave portion is formed in the surface shape following the shape of the intermediate electrode layer 15a.

Further, the dielectric film 16a and the dielectric film 14a
And a contact hole 19 penetrating through the interlayer insulating film 12a to expose a surface portion at one end of the lower electrode layer 11a, and a dielectric film 16a including the contact hole 19 is formed.
Above, the cell plate electrode 17 in the memory cell region described above
And the upper electrode layer 17 at substantially the same hierarchical position with the same material as
a is formed. At this time, in the upper electrode layer 17a, similarly to the dielectric film 16a, a concave portion is formed in the surface shape following the shape of the dielectric film 16a, and the upper electrode layer 17a is formed in the contact hole 19. The conductive material is filled, and the upper electrode layer 17a and the lower electrode layer 11a are electrically connected.

As described above, the capacitor C1 is formed by the intermediate electrode layer 15a and the lower electrode layer 11a sandwiching the dielectric film 14a, and the capacitor C2 is formed by the intermediate electrode layer 15a and the upper electrode layer 17a sandwiching the dielectric film 16a. Each is formed to form a filter capacitor.

As described above, in the DRAM of the present embodiment, the filter capacitor in the peripheral circuit region has three electrode layers, and the three electrode layers include the lower electrode layer 11a and the upper electrode layer 17a. Are capacitively coupled to the intermediate electrode layer 15a to form two capacitors C1 and C2. That is, two capacitors C1 and C2 are formed in an area occupied by one capacitor, and these capacitors C1 and C2 are electrically connected to the lower electrode layer 11a and the upper electrode layer 17a through the contact holes 19. Connected in parallel, it is possible to secure a sufficient capacitance even if the area occupied by the filter capacitor is significantly reduced.

Further, since the intermediate electrode layer 15a, the dielectric film 16a, and the upper electrode layer 17a constituting the capacitor C2 each have a concave portion on the surface, the intermediate electrode layer 15a
And the upper electrode layer 17a are opposed to each other on the entire inner surface including the concave portion, and the facing area between the intermediate electrode layer 15a and the upper electrode layer 17a is larger than in the case where the surface of each layer is flat. The capacitance will be obtained.

In the present embodiment, the field shield element isolation structure 21 is exemplified as the element isolation structure. Instead of this field shield element isolation structure 21, a field oxide film is formed by a so-called LOCOS method as an element isolation structure. May be formed.

Hereinafter, a method of manufacturing the DRAM of the present embodiment will be described. 3 to 11 and 12 to 18
2A to 2D are schematic cross-sectional views showing a process of forming a memory cell region of the DRAM in the order of steps. FIGS. 3 to 11 correspond to the cross section shown in FIG. 1A, and FIGS. It corresponds to the cross section shown. FIGS. 19 (a) to 19 (f)
FIG. 4 is a schematic cross-sectional view showing a process of forming a filter capacitor formed in a peripheral circuit region of the DRAM in the order of steps.
The reference numerals shown in FIGS. 3 to 19 are described so as to correspond to the reference numerals shown in FIGS.

First, as shown in FIGS. 3, 12, and 19A, a field shield element isolation structure 21 is formed on the surface of the p-type silicon semiconductor substrate 1 on the memory cell region side and the peripheral circuit region side. Each element formation region is defined by these field shield element isolation structures 21.

That is, first, a silicon oxide film 2a, a polycrystalline silicon film 3a, and a silicon oxide film 4a are sequentially formed on the silicon semiconductor substrate 1 in the memory cell region and the peripheral circuit region.

Thereafter, in the memory cell region, the silicon oxide film 2a, the polycrystalline silicon film 3a, and the silicon oxide film 4a are patterned by photolithography and subsequent dry etching and the like, and are selectively removed to form an element formation region. Define.

Thereafter, the remaining silicon oxide film 2a,
After forming a silicon oxide film on the entire surface so as to cover the polycrystalline silicon film 3a and the silicon oxide film 4a, the silicon oxide film and the polycrystalline silicon film are anisotropically dry-etched by RIE or the like. Then, the sidewall protective film 5 is formed while leaving the silicon oxide only on the sidewalls of the silicon oxide film.

Thus, in the memory cell region and the peripheral circuit region, a field shield element isolation provided with a shield plate electrode 3 made of a polycrystalline silicon film surrounded by the silicon oxide film 2, the silicon oxide film 4, and the side wall protection film 5 The structure 21 is formed (in the peripheral circuit region, the side wall protective film 5 is formed at a position outside the figure).

Next, as shown in FIGS. 4 and 13, in the memory cell region, the surface of the silicon semiconductor substrate 1 is subjected to thermal oxidation, or a gate oxide film 6 is formed by a vacuum deposition method such as CVD. Further, after a polycrystalline silicon film is deposited and formed on the entire surface of the gate oxide film 6 by a vacuum deposition method such as CVD, the polycrystalline silicon film is patterned by photolithography and subsequent dry etching to form a gate electrode on the gate oxide film 3. 7 is formed.

Next, in the memory cell region, a silicon oxide film is deposited and formed on the entire surface by a vacuum deposition method such as CVD so as to cover the gate electrode 7, and then the entire surface of the silicon oxide film is anisotropically dried by RIE or the like. Etching is performed to form a cap insulating film 22 and a side wall protective film 23 covering the gate electrode 7 while leaving the silicon oxide film only on the upper surface and side surfaces of the gate electrode 7.
The gate oxide film 6 between the gate electrode 7 and the field shield element isolation structure 21 is removed, and the surface of the silicon semiconductor substrate 1 at these portions is exposed.

Subsequently, CVD is performed in the memory cell region.
A polycrystalline silicon film is deposited and formed on the entire surface by a vacuum deposition method such as that described above, and is patterned by photolithography and subsequent dry etching to form the polycrystalline silicon film on the cap insulating film 22 and the field shield element isolation structure 21. Remove the film. At this time, it is electrically connected to the surface of the silicon semiconductor substrate 1 between the respective gate electrodes 7 and between the gate electrode 7 and the field shield element isolation structure 21, each of which is on the cap insulating film 22 or the field shield element isolation structure 21. Each pad polycrystalline silicon film 8 electrically separated above is formed.

Subsequently, in the memory cell region, ions of arsenic (As) or the like are implanted into the silicon semiconductor substrate 1 through the pad polycrystalline silicon film 8 using the cap insulating film 22 of the gate electrode 7 as a mask. A pair of impurity diffusion layers 24 serving as source / drain diffusion layers of the MOS transistor are formed.

Next, as shown in FIG. 5, FIG. 14 and FIG. 19B, a silicon oxide film is deposited on the entire surface of the memory cell region and the peripheral circuit region by a vacuum deposition method such as CVD and the like. Is to deposit and form an interlayer insulating film 9 and an interlayer insulating film 9a in the peripheral circuit region, and flatten the surface by subjecting the interlayer insulating film 9 and the interlayer insulating film 9a to etch back or the like.

Subsequently, as shown in FIGS. 6 and 15, in the memory cell region, the interlayer insulating film 9 is subjected to photolithography and subsequent dry etching to form an interlayer insulating film on one of the impurity diffusion layers 24. A contact hole 10 is formed in the film 9 to expose a part of the surface of the pad polycrystalline silicon film 8 electrically connected to one of the impurity diffusion layers 24.

Next, as shown in FIG. 7, FIG. 16 and FIG. 19 (c), a polycrystalline silicon film
A W silicide film of about Å is sequentially formed to form a polycide layer. At this time, the lower electrode layer 11a made of the polycide layer is formed on the interlayer insulating film 9 in the peripheral circuit region.

Subsequently, in the memory cell region, the polycide layer is subjected to photolithography and subsequent dry etching to fill the contact hole 10 and to form the one impurity diffusion layer via the pad polycrystalline silicon film 8. The wiring layer 11 which is electrically connected to the wiring 24 and becomes a bit line (and other wiring) on the interlayer insulating film 9 is formed in a predetermined pattern. On the other hand, in the peripheral circuit region, the lower electrode layer 11a having a predetermined pattern is formed by subjecting the polycide layer to photolithography and subsequent dry etching.

Next, a silicon oxide film is deposited on the entire surface of the memory cell region and the peripheral circuit region by a vacuum deposition method such as CVD so as to have a thickness of about 1000 to 1500 °, and the surface is flattened by performing etch back or the like. At this time, in the memory cell region, an interlayer insulating film 12 made of the silicon oxide film covering the wiring layer 11 is formed.

Subsequently, as shown in FIGS. 8 and 19D, a contact hole 13 is formed in the memory cell region, and an opening 18 is formed in the peripheral circuit region. That is, the surface of the silicon semiconductor substrate 1 in the memory cell region and the peripheral circuit region is covered with a resist mask, and the resist mask is dry-etched using a mask patterned by photolithography.

At this time, in the memory cell region, the two wiring layers 11 above the pad polycrystalline silicon film 8 are also dry-etched as a mask, and the other impurity diffusion is performed by piercing the interlayer insulating films 9 and 12. A contact hole 13 for exposing a part of the surface of the pad polycrystalline silicon film 8 electrically connected to the layer 24 is formed in a self-aligned manner with a width formed at an interval between the two wiring layers 11. As described above, by using the wiring layer 11 as a mask, even if the opening pattern of the resist mask is slightly displaced, the contact hole 13 can always be formed at an accurate position, and the mask alignment of the resist mask can be slightly performed. Can be done roughly.

On the other hand, in the peripheral circuit region, the silicon oxide film deposited in the peripheral circuit region is dry-etched using a mask obtained by patterning the above-described resist mask by photolithography, so that a part of the silicon oxide film is removed. An opening 18 that is removed to expose a part of the surface of the lower electrode layer 11a is formed to form an interlayer insulating film 12a.

Subsequently, the resist mask on the surface of the silicon semiconductor substrate 1 in the memory cell region is removed by performing an ashing process or the like, and silicon oxide is formed on the entire surface of the memory cell region and the peripheral circuit region by a vacuum deposition method such as CVD. Film thickness 5
Deposit about 00-1000 °. At this time, the contact hole 13 is filled in the memory cell region, and the silicon oxide is formed on the interlayer insulating film 12a and on a part of the surface of the lower electrode layer 11a exposed through the opening 18 in the peripheral circuit region. Dielectric film 14a composed of a film
Is formed.

Next, as shown in FIG. 9, with the surface of the silicon semiconductor substrate 1 in the peripheral circuit area covered with a resist mask, the entire surface of the silicon oxide film deposited on the interlayer insulating film 12 in the memory cell area. Is anisotropically dry-etched by RIE or the like to form a sidewall insulating film 14 leaving the silicon oxide film only on the side surfaces of the contact holes 13.

Subsequently, as shown in FIG. 19E, the resist mask on the surface of the silicon semiconductor substrate 1 in the peripheral circuit region is removed by performing an ashing process or the like, and the entire surface of the memory cell region and the peripheral circuit region is removed. Then, a polycrystalline silicon film is deposited to a thickness of about 5000 to 6000 by a vacuum deposition method such as CVD.

Next, as shown in FIGS. 10 and 17,
In the memory cell region, a part of the polycrystalline silicon film is removed by subjecting the polycrystalline silicon film formed on the interlayer insulating film 12 to photolithography and subsequent dry etching or the like, so that the contact hole 13 is formed. A storage node electrode 15 having a predetermined pattern to be filled is formed. On the other hand, in the peripheral circuit region, the interlayer insulating film 12
By performing photolithography and subsequent dry etching on the polycrystalline silicon film formed on the dielectric film 14a and the dielectric film 14a, an intermediate electrode layer 15a having a predetermined pattern is formed.

Subsequently, FIG. 11, FIG. 18 and FIG.
As shown in FIG. 1, an oxide film, a nitride film and an oxide film are sequentially formed on the entire surface of the memory cell region and the peripheral circuit region.
An NO film is formed. Here, 3 which constitutes this ONO film
The lowermost oxide film (natural oxide film) is 10 自然 thick.
Hereinafter, a nitride film is formed to a thickness of about 45 ° to 65 °, and an uppermost oxide film is formed to a thickness of about 5 ° to 10 °.
At this time, a dielectric film 16 is formed to cover storage node electrode 15 in the memory cell region, and a dielectric film 16a is formed to cover intermediate electrode layer 15a in the peripheral circuit region.

Subsequently, with the surface of the silicon semiconductor substrate 1 in the memory cell region covered with a resist mask, the dielectric film 16a, the dielectric film 14a and the interlayer insulating film 12a are pierced in the peripheral circuit region to form the lower electrode layer 11a. A contact hole 19 for exposing the surface of one end of the contact hole 19 is formed.

Subsequently, a polycrystalline silicon film is deposited on the entire surface of the memory cell region and the peripheral circuit region by a vacuum deposition method such as CVD so as to have a thickness of about 500 to 800 °. here,
This polycrystalline silicon film is preferably formed as thin as possible. At this time, a cell plate electrode 17 made of the polycrystalline silicon film is formed on the dielectric film 16 in the memory cell region.

Then, with the surface of the silicon semiconductor substrate 1 in the memory cell area covered with a resist mask, in the peripheral circuit area, the polycrystalline silicon film formed on the dielectric film 16a is subjected to photolithography and subsequent dry lithography. By performing etching or the like, contact hole 1
9 to form an upper electrode layer 17a having a predetermined pattern that is electrically connected to the lower electrode layer 11a.

Thereafter, the resist mask on the surface of the silicon semiconductor substrate 1 in the memory cell region is removed by performing an ashing process or the like, and a predetermined post-process is performed, so that the DRAM memory cell is removed in the memory cell region. In the peripheral circuit area, a filter capacitor including the capacitors C1 and C2 is completed.

As described above, in the DRAM manufacturing method of the present example, the filter capacitors in the peripheral circuit region are formed with good matching using the respective materials for forming the DRAM memory cells in the memory cell region. At this time, as the filter capacitor, the lower electrode layer 11a and the upper electrode layer 17a are capacitively coupled to the intermediate electrode layer 15a, respectively, and the lower electrode layer 11a and the upper electrode layer 17a are connected in parallel via the contact hole 19. Capacitor C
1, C2 will be formed. Therefore, two capacitors are formed in the area occupied by one capacitor, and even if the area occupied by the filter capacitor is significantly reduced, it is possible to obtain substantially the same capacitance as that of the related art.

[0074]

According to the present invention, the noise elimination function of the filter capacitor is sufficiently ensured while the area occupied by the peripheral circuit, for example, the chip occupied by the filter capacitor is reduced, and the matching between the semiconductor element and the filter capacitor is ensured. A well-formed semiconductor memory device can be realized.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a DRAM according to one embodiment of the present invention.

FIG. 2 is a schematic sectional view showing a memory cell of the DRAM according to one embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view showing a method for manufacturing a memory cell of the DRAM according to one embodiment of the present invention;

FIG. 4 is a schematic sectional view showing a method for manufacturing a memory cell of the DRAM according to one embodiment of the present invention;

FIG. 5 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 6 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 7 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 8 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 9 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 10 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 11 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 12 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 13 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 14 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 15 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 16 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 17 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 18 is a schematic sectional view showing the method for manufacturing the memory cell of the DRAM according to one embodiment of the present invention;

FIG. 19 is a schematic cross-sectional view showing a method of manufacturing the filter capacitor of the DRAM according to the embodiment of the present invention in the order of steps.

[Explanation of symbols]

 Reference Signs List 1 p-type silicon semiconductor substrate 7 gate electrode 8 pad polycrystalline silicon film 9, 12, 9a, 12a interlayer insulating film 10, 13, 19 contact hole 11 wiring layer 11a upper electrode layer 14 sidewall insulating film 14a dielectric film 15 storage Node electrode 15a Intermediate electrode layer 16, 16a Dielectric film 17, 17a Upper electrode layer 18 Opening 21 Field shield element isolation structure 22 Cap insulating film 23 Side wall protective film 24 Impurity diffusion layer

Claims (4)

[Claims] 1. A semiconductor memory device having a memory cell region and a peripheral circuit region including a capacitor, wherein the capacitor includes a first electrode layer, and a capacitor dielectric film on an upper surface and a lower surface of the first electrode layer, respectively. And a second electrode layer opposed to the semiconductor memory device via the intervening second electrode layer. 2. A recess is formed on the upper surface of the first electrode layer, and the first electrode layer faces the second electrode layer via the capacitor dielectric film on the entire inner surface including the side surface of the recess. 2. The semiconductor memory device according to claim 1, wherein: 3. A semiconductor memory device in which each memory cell includes an access transistor and a memory capacitor, wherein the memory capacitor is formed at a position substantially above a bit line in the memory cell region. The first electrode layer of the capacitor in the peripheral circuit region is formed of a conductive film of the same material as the lower electrode formed at a hierarchical position corresponding to a lower electrode that is a storage node of the memory capacitor; The second electrode facing the lower surface of the first electrode layer of the capacitor
A portion of the electrode layer is formed of a conductive film of the same material as the bit line formed at a hierarchical position corresponding to the bit line in the memory cell region, and a portion of the first electrode layer of the capacitor in the peripheral circuit region; The portion of the second electrode layer facing the upper surface is formed of a conductive film of the same material as the upper electrode formed at a hierarchical position corresponding to the upper electrode which is a cell plate of the memory capacitor. 3. The semiconductor memory device according to claim 1, wherein: 4. A step of forming an access transistor forming a memory cell in a region to be a memory cell region of a semiconductor substrate; and forming an interlayer insulating film on an entire surface of the semiconductor substrate in the memory cell region and the peripheral circuit region. Forming a first opening reaching the one diffusion layer of the access transistor in the first insulating film; and forming the first opening including an inside of the first opening. Forming a first conductive film over the entire surface of the first insulating film; processing the first conductive film into a bit line shape in the memory cell region; and forming the first conductive film in the peripheral circuit region. Processing a film into a predetermined pattern; forming a second insulating film to be an interlayer insulating film on the entire surface of the semiconductor substrate in the memory cell region and the peripheral circuit region; In the memory cell region, a second opening for making contact with the other diffusion layer of the access transistor is formed in the second insulating film and the first insulating film, and the second opening is formed in the peripheral circuit region. Forming a third opening in the second insulating film on the first conductive film in the pattern; forming a third insulating film on the entire surface including the inside of the second and third openings; And anisotropically etching the third insulating film in the memory cell region by masking the peripheral circuit region, and forming a sidewall insulating film made of the third insulating film on a side surface of the second opening. Forming a film, forming a second conductive film over the entire surface including the inside of the second and third openings, and applying the second conductive film to the lower electrode of a memory capacitor in the memory cell region. When processed into the shape of In both cases, a step of processing the second conductive film into a shape of a first electrode of a capacitor in the peripheral circuit region; and forming a fourth conductive film on the second conductive film in the memory cell region and the peripheral circuit region. Forming an insulating film; forming a third conductive film on the entire surface of the semiconductor substrate in the memory cell region and the peripheral circuit region; And forming the third conductive film in the peripheral circuit region into the shape of the second electrode of the capacitor.