JPH10108077A - Output circuit for slid-state image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To allow the circuit to generate a timing pulse with high timing accuracy whose pulse width is set arbitrarily. SOLUTION: A pulse generating circuit 13 is a drive circuit for a CCD preamplifier 12, receives a reset pulse and generates drive pulses SP1, SP2 with required delay times and pulse widths based on the reset pulse. A capacitor 14 is charged gradually from a reset circuit 80, in response to the reset pulse and a constant current power supply 15 for an off-time (t) of the pulse 100, and is reset for the on-time of the pulse 100 and an analog signal triangle wave 110 is generated. Comparators 16, 17 compare the signal 110 received at their non-inverting inputs (+) with reference voltage V1, V2 received at their inverting input (-) respectively and provide an output of pulses PV1, PV2 respectively. An arithmetic circuit 18 calculates the pulses PV1, PV2 and the reset pulse 100 to provide an output of the drive pulses SP1, SP2. The drive pulses SP1, SP2 with a desired timing are obtained by selecting the capacitance of the capacitor 14 and a voltage of the reference voltages. Since the setting and the selection above are conducted before the summing points of the analog signal and the reference voltages, the drive pulses are variably adjusted and continuously, which has been difficult in the case with a digital signal, high timing accuracy is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a charge-coupled device.
The present invention relates to an output circuit for a solid-state imaging device to which an output signal read from a solid-state imaging device such as a CCD (CCD) is input and which removes noise to generate a video signal.

[0002]

2. Description of the Related Art As is well known, when a solid-state imaging device, for example, a charge-coupled device, scans an imaging cell array horizontally, a CCD output signal consisting of a reset component, a feedthrough signal, and a pixel signal in one pixel period, for example, 9 to
And outputs the signal rate 14MH _Z. The output circuit for the solid-state imaging device which receives the CCD output signal and outputs a video signal with minimized noise is provided with a correlated double output which outputs a video signal in which noise correlated with a feedthrough signal included in a pixel signal is removed. There is an integral type CDS method that outputs a video signal by removing high frequency noise by sampling (CDS) method and integration method. With respect to the output circuit of the correlated double sampling system, for example, there are Japanese Patent Application Nos. 06-137296, 07-123482 and 07-214297 by the same applicant as the present applicant.

[0003]

In the CDS system, an output circuit for a solid-state imaging device requires two types of sampling pulses to extract a feedthrough signal and a pixel signal from an output signal of the solid-state imaging device. In addition, integrating CD
In the S system, a sampling pulse for generating an integrated waveform and extracting a signal of the integrated waveform is added to these sampling pulses, and four types of pulses are required. Each pulse requires high precision in timing, must have the same period as the output signal of the solid-state imaging device, and must be a pulse delayed by a certain delay time with respect to this. Therefore, in a conventional output circuit for a solid-state imaging device,
Strict timing adjustment was required.

Therefore, according to the conventional method, the resistance is adjusted by selecting the resistance and the parasitic capacitance inserted in the clock line of the clock pulse generated from the system clock generated from the free-running crystal oscillator. , CDS
By adjusting to the subtle timing of the system, accuracy was obtained.
In addition, such a fine timing adjustment may be achieved by specially creating a timing generation circuit suitable for an output circuit system for each solid-state imaging device.
Further, the clock pulse generated from the crystal oscillator has a constant pulse width, and only has a pulse width equal to a multiplication thereof. In contrast, the integral CDS method
Pulses for extracting signals from the CCD output signal require various pulse widths, so high-precision timing can be obtained with the integral CDS method that requires various pulse widths and strict timing accuracy. There were no shortcomings.

Further, when an output circuit for a solid-state imaging device of the integral type CDS system is formed into an integrated circuit (IC), values of circuit elements such as resistors and capacitors in a manufacturing process vary among individual products. This variation directly appears as a gain variation of the output video signal. The gain is proportional to the capacitance of the capacitor of the integration circuit and the width of the integration pulse, and is inversely proportional to the resistance. For example, the gain variation of the output video signal is -17% to + 25% due to an error of ± 20% of the resistance value. This was a disadvantage inherent in the integral CDS method.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an output circuit for a solid-state imaging device which solves such disadvantages of the prior art and generates a timing pulse having high timing accuracy and capable of arbitrarily setting a pulse width.

Another object of the present invention is to provide an output circuit for a solid-state imaging device in which the influence of circuit element errors due to the IC manufacturing process is minimized and the gain is stable.

[0008]

According to the present invention, an output signal output from a solid-state imaging device in response to a first timing signal for driving the solid-state imaging device is received, and a pixel unit of the output signal is used. An output circuit for a solid-state imaging device including a noise removal unit that extracts a feedthrough signal and a pixel signal, removes noise from the pixel signal, and outputs a continuous video signal in pixel units, has a first timing signal. A first analog signal that is input and repeats a voltage increase and decrease in synchronization with a first timing signal is generated, and the first analog signal is compared with a first plurality of reference voltages that intersect with the first analog signal. Generating at least one second timing signal having a predetermined timing for extracting the feed-through signal and the pixel signal, and generating the second timing signal. Comprising a first pulse signal generating means for supplying's removal means.

[0009] At least the noise removing means is formed on an integrated circuit chip, and the output circuit of the video signal includes a gain in which the error coefficient of the integrated circuit resistance is in reverse phase.
A feedback resistor formed on the integrated circuit chip, an operational amplifier formed on the integrated circuit chip, having an input / output terminal connected to the feedback resistor, and having an error coefficient of the feedback resistor in a gain; And a reference resistor which is connected in series to the input of the integrated circuit chip and is provided outside the integrated circuit chip, and a correction means for canceling the error coefficient is provided, and the video signal may be inputted to the reference resistor.

Further, the noise removing means and the first pulse signal generating means may be formed on a common integrated circuit chip. Thus, the error coefficient of the negative phase of the integrated circuit resistance and the capacitance of the capacitor included in the gain of the first pulse signal generating means is canceled by the error coefficient of the integrated circuit resistance and the capacitance of the capacitor during the integration period of the second timing signal. You.

According to the present invention, in the output circuit for a solid-state imaging device, the second timing pulse can be continuously variably adjusted to a desired timing, and a highly accurate pulse can be obtained. In an output circuit for an integrated solid-state imaging device integrated into an integrated circuit, a variation in gain due to an error coefficient of an integrated circuit resistor and a capacitor is canceled by a correction unit.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an output circuit for a solid-state imaging device according to the present invention; First, referring to FIG. 3, an embodiment in which an output circuit for a solid-state imaging device according to the present invention is applied to a charge-coupled device (CCD) is shown in FIG. This is a solid-state imaging system that removes noise with a preamplifier 12 and outputs the noise as a video signal 103. The drive pulse such as the reset pulse 100 and the horizontal transfer pulse 101 is input from the timing generation circuit (TG) 11 to the charge-coupled device 10, and when the imaging cell array is horizontally scanned, one pixel period T becomes a reset component a, a feed-through signal This is a solid-state imaging device that continuously outputs a CCD output signal 102 composed of a pixel b and a pixel signal c (FIG. 2). The CCD preamplifier 12, to which the CCD output signal 102 is input, receives the control pulse (CP) generated by the pulse generation circuit 13.
In response, the CCD output signal 102 is correlated double sampled.
This is a noise elimination circuit that performs processing by the (CDS) method or the integral type CDS method to minimize noise and continuously outputs the video signal 103 of one pixel unit. The details of the noise removal by the CDS method or the integral CDS method are not directly related to the understanding of the present invention, and will not be described. See the aforementioned three patent applications for details.

FIG. 1 shows an embodiment of the pulse generation circuit 13, and FIG. 2 is a time chart of the pulse generation circuit 13 of this embodiment. The charge-coupled device 10 is driven by a reset pulse 100 and a horizontal transfer pulse 101 generated by the timing generation circuit 11. Therefore, the CCD output signal 102 from the charge coupled device 10 has the same period T as the reset pulse 100. The pulse generation circuit 13 is a preamplifier
12 constitutes a CCD output circuit and generates sample and hold pulses SP1 and SP2. The sample-and-hold pulses SP1 and SP2 are, as shown in FIG. 2, from the start of one pixel period T to the rise of the pulses d1 and d2 to extract the feedthrough signal b and the pixel signal c from the CCD output signal 102. Exact delay time t1
And t2, and those pulses have the exact pulse widths d1 and d2.

As shown in FIG. 1, the pulse generation circuit 13
Has two comparators 16 and 17 and their non-inverting inputs (+)
Is connected to a capacitor (C) 14, a constant current source (S) 15, and a reset circuit 80. The reset circuit 80 connects the voltage V7 to the capacitor 14 in response to a reset pulse 100 generated by the timing generation circuit 11. As a result, the capacitor 14 is charged to the voltage V0 from the constant current source 15 at the off time t of the reset pulse 100, and is rapidly discharged at the on time to produce a triangular wave 110 of an analog signal as shown in FIG.
Occurs. The charge / discharge gradient of the triangular wave 110 depends on the capacitance C of the capacitor 14, the characteristics of the constant current source 15, and the time constant of the charge / discharge circuit system. An example of the configuration of the constant current source 15 is shown in FIG. This will be described in detail later.

One comparator 16 converts the triangular wave signal 110 input to the non-inverting input (+) into a reference voltage V1 of the inverting input (-).
Is a rectangular wave forming circuit that outputs a pulse PV1 as shown in FIG. The other comparator 17 also has a non-inverting input
This is a rectangular wave forming circuit that compares the triangular wave signal 110 input to (+) with the reference voltage V2 of its inverted input (−) and outputs a pulse PV2 as shown in the figure. These outputs PV1 and PV
2 is connected to the input of an arithmetic circuit (LC) 18 as shown.

The arithmetic circuit 18 has two pulses PV1 and PV1
2 and also a reset pulse 100, and is a logical operation circuit that outputs sample and hold pulses SP1 and SP2 by the following operation. That is, SP1 = PV1 AND to PV2 AND to 100, and SP2 = PV2 AND to 100. Here, the symbol “〜” indicates signal inversion. As can be seen, by selecting the values of the capacitor 14 and the reference voltages V1 and V2, sample and hold pulses SP1 and SP2 having desired pulse widths d1 and d2 and delay times t1 and t2, respectively, are obtained. More specifically, the characteristics of the sample and hold pulses SP1 and SP2 are
Since this is set at the cross point between the triangular wave 110 of the analog signal and the reference voltages V1 and V2, in this embodiment, it is possible to continuously adjust the timing, which is generally difficult with a digital signal. Can be generated.

In this embodiment, a reset pulse 100 for resetting the charge-coupled device 10 is used as a timing pulse for generating a triangular wave 110. However, the present invention
The present invention is not limited to this, and any signal may be used as long as the signal is synchronized with the output signal 102 from the charge-coupled device 10. Intermediate pulses PV1 and PV2 are generated from the triangular wave 110 and the two threshold voltages V1 and V2, and two sample and hold pulses SP1 and SP2 are generated by these and the timing pulse 100.

The characteristics of the sample and hold pulses SP1 and SP2, for example, the delay times t1 and t2, and the pulse width
d1 and d2 can be adjusted by the values of the reference voltages V1 and V2. Further, if it is necessary to adjust the timing of the timing pulse, which is the basic pulse, for example, the reset pulse 100, a fine adjustment circuit as shown in FIG. 14 may be used. This fine adjustment circuit 82
The configuration example of the fine adjustment circuit of SP1 is shown. In this circuit, a capacitor C and an adjustment resistor R are connected to the non-inverting input (+) of the operational amplifier 130.
Are connected as shown, and a reference voltage Vref is connected to the inverted input (−). As can be seen from the time chart of FIG. 15, when the reset pulse 100 is input to the circuit 82, the reset pulse 100 becomes a waveform 180 shown in FIG. Input to inverted input (+). The operational amplifier 130 converts the input signal 180 to the reference voltage Vr
In comparison with ef, a pulse 100a delayed by the delay time d from the rising of the pulse 100 until the level of the waveform 180 exceeds the reference voltage Vref is output. This pulse 100a is the charging circuit 80
And to the arithmetic circuit 18. As a result, fine adjustment of the delay times t1 and t2 of the sample and hold pulses SP1 and SP2 and the pulse widths d1 and d2 of FIG. 2 is possible as a result.

FIG. 4 shows a main part of an embodiment in which the CCD preamplifier 12 is realized by the CDS system, and FIG. 5 is a time chart thereof. CCD preamplifier 12 to which CCD output signal 102 is input
Are supplied with sample and hold pulses SP1 and SP2 from the pulse generation circuit 13 in FIG. The sample and hold pulses SP1 and SP2 have predetermined timings, that is, delay times t1 and t2, and pulse widths d1 and d2, and
D is a pulse for extracting a feedthrough signal b and a pixel signal C following the reset component a of the output signal 102. This preamplifier 12 has three sample and hold circuits
(SH) 21, 22, and 23, and the CCD output signal 102 is input to the sample and hold circuits 21 and 23 through the amplifier 20.

As shown in FIG. 5, a sample hold circuit
21 extracts and holds the feed-through signal b in response to the pulse SP1, and the subsequent sample-and-hold circuit 22
This signal b is held in response to the pulse SP2. Further, the sample hold circuit 23 holds the pixel signal C in response to the pulse SP2. Outputs of the sample and hold circuits 22 and 23 are connected to a non-inverting input (+) and an inverting input (-) of the differential amplifier 24, respectively. The differential amplifier 24 removes the reset noise included in the pixel signal C from the sample-and-hold circuit 23 by the feed-through signal b including the same reset noise from the sample-and-hold circuit 22, and sequentially outputs the video signal 103 for one pixel. Output.

FIG. 6 shows a main part of an output circuit in which the CCD preamplifier 12 is realized by an integral CDS system, and FIG. 7 shows a signal waveform appearing in each part. In the CCD preamplifier 12 of this integral type CDS system, a CCD output signal 102 is input to gate circuits (GT) 32 and 33 through an amplifier 31. One gate circuit 32
Extracts the feedthrough signal b by the gate pulse GP1 and outputs it to the non-inverting input (+) of the differential amplifier 34. The other gate circuit 33 extracts the pixel signal C by the gate pulse GP2 and outputs Output to the inverted input (-). The differential amplifier 34 outputs a pixel signal 300 (FIG. 7) for each pixel to the integration circuit 30 at the reference level L. The integrating circuit 30 includes the resistor 3
5, an operational amplifier 36, a capacitor 37 and an integration reset switch 38 are connected as shown in the figure. The switch 38 responds to an integration reset pulse 100b, which will be described later, and opens at the off time t to remove the high-frequency noise from the input pixel signal 300 and output an integrated output signal 301 of the pixel signal.
The integrated output signal 301 is input to the sample and hold circuit 39, and the sample and hold circuit 39 extracts a video portion of the integrated output signal 301 by another sample and hold pulse SP. This sample hold pulse SP can be generated by a pulse generation circuit 13 described later. The extracted video portion is input to the amplifier 40, and the amplifier 40
Outputs 3.

FIG. 8 shows another embodiment of the pulse generating circuit 13, which is an integral type CDS type preamplifier 12 shown in FIG.
It is advantageously applied to: In the following drawings, the same elements as those described above are denoted by the same reference numerals. The pulse generation circuit 13 of this embodiment is the same as the integration type CCD shown in FIG.
The gate pulses GP1 and GP2 of the preamplifier 12 and the sample hold pulse SP are generated. FIG. 9 is a time chart of the pulse generation circuit 13 shown in FIG. The pulse generating circuit 13 of the embodiment shown in FIG. 8 has a capacitor 14, a constant voltage power supply 15 of a voltage V0, and a reset circuit 80 similarly to the pulse generating circuit 13 of FIG. ,
It is input to the non-inverting inputs (+) of the comparators 43, 44 and 45.
The comparators 43, 44, and 45 have their inverting inputs (-) connected to reference voltages V3, V4, and V5, respectively.
3. The pulses PV3, PV4 and PV5 resulting from the comparison with V4 and V5 are output to the arithmetic circuit 46. The arithmetic circuit 46 outputs a pulse
PV3 to PV5 and the reset pulse 100 are input, and gate pulses GP1 and GP2, a sample hold pulse SP, and an integral reset pulse 100b are output by the following calculation. That is, SP1 = PV3 AND〜PV4 AND 100 SP2 = PV3 AND〜100 SP3 = PV5 AND〜100 100b = 100 where the symbol “〜” indicates signal inversion. Reset pulse
100b drives the switch 38 of the integration circuit 30. As can be seen, capacitor 14 and reference voltages V3, V4 and V5
, Gate pulses GP1 and GP2 and a sample-and-hold pulse SP having a desired pulse width and delay time, respectively, are obtained.

Also in this embodiment, the timing pulse for generating the triangular wave 110 is the output signal 1 from the charge-coupled device 10.
Any signal may be used as long as it is a signal synchronized with 02. Intermediate pulses PV3, PV4 and PV5 are generated from the triangular wave 110 and the three threshold voltages V3, V4 and V5.
GP1, GP2, SP and 100b are generated.

In the preamplifier of the CCD readout signal output circuit based on the integration method, drive pulses of various pulse widths are required. In the pulse generator of the conventional system, even these pulses need to be narrower than the pulse width of the system clock. In addition, it is necessary to strictly control the relationship between the end of integration, sample hold, integration reset, and the pulse. However, in this embodiment, it is possible to form a drive pulse whose timing is strictly adjusted from one kind of triangular wave.

In the pulse generating circuit 13 of the embodiment shown in FIGS. 1 and 8, two or three reference voltages are set. However, if more types of reference voltages are provided, fine timing adjustment is possible. Becomes In addition to the triangular wave, a simple time constant curve of charge and discharge by a resistor and a capacitor can be used. Furthermore, another triangular wave can be generated by using the pulse generated by the triangular wave and the bias voltage in this manner, and a group of driving pulses can be generated from these and a further threshold voltage. In other words, the pulse generation circuit
13 can be sequentially connected in cascade to generate a plurality of drive pulses. These one group of drive pulses are:
For example, it can be used as a drive pulse for driving each of a plurality of preamplifiers (not shown) similar to the preamplifier 12 provided corresponding to the three primary color component signals of the color video signal.

In an application example in which an analog / digital (A / D) converter is provided at the output 103 of the preamplifier 12, the A / D
Driving pulses required for driving the converter and driving pulses for the sample-and-hold circuit can also be generated from the above-described triangular wave at strict timing.

As described above, according to the embodiment of the present invention, various drive pulses of the output circuit for the solid-state imaging device are generated from one type of timing pulse synchronized with the reading of the output signal of the solid-state imaging device. Therefore, the configuration of the system is simplified. In addition, since a synchronous waveform such as a triangular wave is generated from such a single type of timing pulse, and a cross-point is adjusted from this and a set value of the threshold voltage to generate a preamplifier driving pulse, driving pulses of various timings are generated. Can be formed. Further, since a plurality of drive pulses are generated from a single type of timing pulse, even a pulse with strict timing accuracy can be easily formed.

Further, the adjustment of the timing is realized by a simple level adjustment of the threshold value. Therefore, it is not necessary to perform a complicated operation such as adjusting the delay time using the external resistor and the parasitic capacitance of the integrated circuit and adjusting the output timing of the timing generator as in the related art. Also, if various drive pulses are generated using a reference pulse synchronized with the output signal of the solid-state imaging device, for example, a CCD reset pulse, the generated pulse is strictly synchronized with the CCD output signal. Noise due to noise can be minimized.

FIG. 10 shows an integral type CCD preamplifier shown in FIG.
FIG. 12 is a block diagram conceptually showing an integration path of a pixel signal in FIG. When the preamplifier 12 is integrated, the constant values of the circuit elements such as the resistor R and the capacitor C vary during the manufacturing process, and the gain C / R * t of the integrating preamplifier is changed.
Fluctuates greatly. Here, * represents multiplication, and t represents the width of the integration pulse, that is, the integration time. FIG. 11 is a signal waveform appearing in each section of the preamplifier 12 shown in FIG. In the figure, dotted lines 183 to 186 indicate gain fluctuations.

FIG. 12 conceptually shows a configuration example of a single-output integrated preamplifier integrated in a circuit. An integrated circuit (IC) chip 50 conceptually indicated by a chain line is an integrating preamplifier 51.
And a correction circuit 52. The integrating preamplifier 51 includes, for example, an integrating CDS type preamplifier 12 shown in FIG.
And peripheral circuits such as a pulse generation circuit 13 shown in FIG. In the correction circuit 52, the operational amplifier 53 includes an integrated circuit resistor R1 and an off-chip reference resistor R2. The variation in the feedback resistor R1 formed as an integrated circuit resistor in the manufacturing process of the integrated circuit is uniform throughout the integrated circuit. That is, the circuit elements formed on the same integrated circuit chip vary in the same direction (absolute variation). Therefore, the error of the entire integrated circuit can be represented by an error coefficient α as a ratio to a reference value. This value α is, for example, about 0.8 to 1.2. An integrating preamplifier 51 is an amplifier having a center gain G,
It consists of a resistor and a capacitor, and its gain is 1 / αG
Can be represented by In the correction circuit 52, the operational amplifier 53 and the resistors R1 and R2 form an antiphase amplifier. Therefore, the final gain of the correction circuit 52 including the operational amplifier 53 is-
α * R1 / R2.

More specifically, the voltage vi of the CCD output signal 102 input to the integrated circuit chip 50 and the output signal vo of the correction circuit 52
The relationship is as follows.

Vo = 1 / α * G * vi * (− α * R1 / R2) = − G * R1 / R2 * vi Therefore, vo / vi = −G * R1 / R2 Since the gain of the correction circuit 52 includes α in the opposite phase with respect to the output of (1), the correction circuit 52 is connected in series to the preamplifier 51 to eliminate the error coefficient α, that is, the fluctuation due to the variation in the resistance is canceled. A predetermined gain can be obtained.

FIG. 13 shows an example of the configuration of a differential output integrated preamplifier integrated in an integrated circuit. The integrated circuit chip 60 includes a differential output integrating preamplifier 61, an operational amplifier 62, a correction circuit 64 including off-chip reference resistors R1 and R3, and integrated circuit resistors R3 and R4. The differential input / output between these amplifiers has the effect of canceling noise such as power supply noise. In this embodiment, as in the embodiment shown in FIG. 12, a preamplifier 61 formed on the same integrated circuit chip is used.
The correction circuit 63 has a uniform resistance variation throughout the integrated circuit. CCD output signal input to the integrated circuit chip 60
There is the following relationship between the voltage vi of 102 and the correction output vo.

[0034]

Vo = α * R2 / (R1 + α * R2) * vp * (R3 + α * R4) / R3-α * R4 / R3 * vn If R1 = R3 and R2 = R4, vo = α * R4 / R3 * (vp-vn) = R4 / (α * R3) * [1 / α * G * vi-(-1 / α * G * vi)] = 2 * G * R4 / R3 * vi where , Vp = 1 / α * G * vi, vn = -1 / α * G * vi Therefore, vo / vi = 2 * G * R4 / R3, and the resistance variation α
To obtain a predetermined gain.

As described above, according to the present embodiment, it is possible to minimize the gain variation of the integration type preamplifier due to the process variation of the resistance. According to this method, there is no need to add a new terminal for correction or a new additional circuit such as a correction circuit, and it can be easily realized simply by externally connecting a resistor. Accordingly, the power consumption and the scale of the circuit can be reduced. Furthermore, since the gain adjustment stage is in the form of an amplifier including an operational amplifier, circuit stabilization and high-speed operation are realized. In addition, if the external reference resistor having the temperature dependency is selected in consideration of the directionality of the temperature characteristic of the gain of the integration type preamplifier, the temperature dependency of the system gain can be canceled at the same time.

By the way, for example, the integration method shown in FIG.
In the case of the CCD preamplifier 12, the pulse generation circuit 13 shown in FIG.
Are formed on an integrated circuit chip (not shown) common to the CCD preamplifier 12 to control the timing of the control pulses GP1, GP2 and SP due to the variation in the manufacturing process of the integrated circuit resistance and capacitor capacitance included therein. Variations can be effectively offset. Less than,
An example will be specifically described.

FIG. 16 shows a configuration example of the constant current circuit 15 in the pulse generation circuit 13 shown in FIG. The constant current circuit 15 is configured such that the output of an operational amplifier 72 is connected to the base of a transistor 71 as shown. Non-inverting input of operational amplifier
(+) Is connected to the reference voltage Vr, and the inverting input (-) and the emitter of the transistor are connected to another reference voltage Vc through the resistor Rc.
Connected to Vcc. The output current Ic is
Obtained from collectors. The slope of the triangular wave 110 depends on the constant current circuit 15, but the output current Ic of the constant current circuit 15 is directly affected by the variation of the resistor Rc included in the constant current circuit 15. Therefore, in order to explain the fluctuation of the output current Ic of the constant current circuit 15, the pulse generation circuit 13 of FIG. 1 is simplified and shown in FIG. FIG. 19 is a time chart showing signal waveforms appearing in various parts of the control pulse generation circuit 13.

The control pulse generating circuit 13 shown in FIG. 18 has an arithmetic circuit 70. The arithmetic circuit 70 compares the triangular waveform 110 generated by the reset circuit 80, the capacitor 14 and the constant current circuit 15 with the comparators 16 and 17. The output of the result of comparison with the reference voltages V1 and V2 is calculated to generate an integration pulse 641 for integrating the pixel signal of the CCD output signal 102 as shown in FIG.

FIG. 17 shows the triangular wave signal 110 and the integration pulse of FIG. 19 generated by the variation of the resistance Rc of the constant current circuit 15.
641 are shown by dotted lines 191-194.
Dotted lines 191 and 192 show the case where the resistance varies in the positive direction, and dotted lines 193 and 194 show the case where the resistance varies in the negative direction. The constant current output Ic = (Vcc-Vr) / (α * Rc) = 1 / α * Ico is obtained from the transistor 71 and the operational amplifier 72. However, Ico = (Vcc-Vr) / Rc The integration period of the integration pulse 641 shown in FIG. 17, that is, the pulse width T is as follows.

T = C * (V2-V1) / Ic = C * (V2-V1) * α / Ico = αTo where To = C * (V2-V1) / Ico.

Here, the gain of the integration type preamplifier 13 can be expressed by 1 / α * G. Since the gain is proportional to the integration period T, the variation coefficient α is canceled by both. Therefore, it is possible to realize a system that is not affected by variations in the resistance Rc.

In an integrated circuit, there is variation in the capacitance C of the capacitor as well as variation in the resistance. Assuming that the variation coefficient of the capacitance C of the capacitor is β, the overall gain of the preamplifier 13 of the integration method can be expressed by 1 / (α * β) * G. The integration time T is T = β * C * (V2-V1) / Ic = β * C * (V2-V1) * α / Ico = α * β * To where To = C * (V2-V1) / Ico. In this manner, also in the constant current circuit 15, the variation coefficients α and β are canceled out, and a system that is not affected by the variation in the resistance and the capacitance of the capacitor can be realized. The above effect is obtained by utilizing the property that the integration type preamplifier 12 and the integration pulse generation circuit 13 are formed on the same integrated circuit chip, and the direction and magnitude of the variation coefficients α and β are the same. Needless to say, it is possible.

In this embodiment, as described above, it is possible to suppress the gain variation of the integration type preamplifier due to the process variation. In particular, variations in both the resistor and the capacitor can be completely minimized. In addition, the pulse generation circuit may be configured so that the width of the integration pulse has temperature dependency in consideration of the directionality of the temperature characteristic of the preamplifier of the integration method. By doing so, the temperature dependence of the gain of the system can be canceled at the same time.

According to the present invention, the present invention is not limited to the integration type preamplifier, but can be applied to any application in which a gain variation caused by a process variation of a resistor in an integrated circuit is corrected. Further, it is possible to correct not only an application example of the integrated circuit but also any system having a gain variation due to a variation in resistance or capacitance.

[0045]

As described above, according to the present invention, in the output circuit for the solid-state imaging device, the cross point between the voltage gradient of the analog signal generated from the timing pulse synchronized with the output signal of the solid-state imaging device and the reference voltage is: Since it is continuously variable, the desired timing of the preamplifier drive pulse can be set with high accuracy. Therefore, a special pulse generator is not required, and the present invention can easily realize a minute timing adjustment in which a digital pulse generated from a stem clock is inferior as in the related art.
Further, since a timing pulse synchronized with the output signal of the solid-state imaging device is used, noise contamination due to jitter can be prevented. In an integrated CCD preamplifier integrated into an integrated circuit,
A gain variation due to an error coefficient of an integrated circuit resistor and a capacitor can be corrected by incorporating a correction circuit.

[Brief description of the drawings]

FIG. 1 is a functional circuit diagram showing a configuration example of a pulse generating circuit in an embodiment in which the present invention is applied to a CDS type CCD preamplifier.

FIG. 2 is a time chart showing signal waveforms appearing in various parts of the pulse generation circuit of the embodiment shown in FIG.

FIG. 3 is a functional block diagram showing a configuration example of a CCD preamplifier of the embodiment and its related circuits.

FIG. 4 is a functional block diagram showing a configuration example of a CDS type CCD preamplifier.

FIG. 5 is a time chart showing signal waveforms appearing in various parts of the CCD preamplifier shown in FIG.

FIG. 6 is a functional circuit diagram showing a circuit example of a CCD preamplifier of the integral type CDS system.

FIG. 7 is a time chart showing signal waveforms appearing at various parts of the CCD preamplifier shown in FIG.

FIG. 8 is a functional circuit diagram showing a configuration example of a pulse generation circuit in an embodiment applied to the integral type CDS system of the present invention.

FIG. 9 is a time chart showing signal waveforms appearing in various parts of the embodiment shown in FIG. 8;

FIG. 10 is a block diagram conceptually showing an integration path of the integration type CCD preamplifier shown in FIG.

FIG. 11 is a waveform chart for explaining a gain variation of a signal waveform appearing in each part of the preamplifier in FIG. 10;

FIG. 12 is a functional configuration diagram showing an embodiment in which the present invention is applied to a single-output integrated-type integrated preamplifier.

FIG. 13 is a functional block diagram showing an embodiment in which the present invention is applied to a differential output integrated circuit integrated preamplifier.

FIG. 14 is a functional circuit diagram showing an example of a circuit for finely adjusting a timing pulse in the embodiment shown in FIG. 1;

FIG. 15 is a timing chart showing signal waveforms appearing at various parts of the fine adjustment circuit shown in FIG. 14;

FIG. 16 is a functional circuit diagram showing a configuration example of a constant current circuit in the embodiment shown in FIG. 1;

FIG. 17 is a waveform chart showing an example of a change in a triangular wave signal generated due to a variation in resistance in the constant current circuit shown in FIG.

18 is a functional circuit diagram showing a conceptual configuration of an integration pulse generation circuit useful for understanding a correction circuit for correcting a variation in resistance in the constant current circuit shown in FIG.

19 is a time chart showing signal waveforms appearing at various parts of the integration pulse generation circuit shown in FIG.

[Explanation of symbols]

 10 Charge coupled device 11 Timing generation circuit 12 CCD preamplifier 13 Pulse generation circuit 15 Constant current circuit

Claims (9)

[Claims] 1. An output signal output from a solid-state imaging device in response to a first timing signal for driving the solid-state imaging device, and a feedthrough signal and a pixel signal are extracted for each pixel of the output signal. An output circuit for a solid-state imaging device including a noise removing unit that removes noise from the pixel signal and outputs a continuous video signal in pixel units, wherein the circuit receives a first timing signal, Generating a first analog signal that repeats a voltage increase / decrease in synchronization with a first timing signal; comparing the first analog signal with a first plurality of reference voltages intersecting the first analog signal; Generating at least one second timing signal having a predetermined timing for extracting a signal and a pixel signal, and converting the second timing signal to the noise Output circuit for a solid-state imaging device which comprises a first pulse signal generating means for supplying the removed by means. 2. The circuit according to claim 1, wherein said circuit further includes a second pulse signal generating means, wherein said second pulse signal generating means receives a second timing signal, and outputs a second pulse signal. Generating a second analog signal that repeats increasing and decreasing the voltage in synchronization with the timing signal; comparing the second analog signal with a second plurality of reference voltages that intersect the second analog signal; An output circuit for a solid-state imaging device, wherein at least one third timing signal having a predetermined timing for extracting a pixel signal is generated, and the third timing signal is supplied to the noise removing unit. . 3. The output circuit for a solid-state imaging device according to claim 1, wherein the first analog signal includes a triangular waveform signal and a waveform signal due to charging and discharging. 4. The circuit according to claim 1, wherein the first timing signal includes a reset pulse and a horizontal transfer pulse for driving the solid-state imaging device, and wherein the first pulse generating means includes a reset pulse and a horizontal transfer pulse. An output circuit for a solid-state imaging device, wherein a first analog signal is generated in response to at least one of transfer pulses. 5. The output circuit for a solid-state imaging device according to claim 1, wherein said noise removing means is of a correlated double sampling type. 6. The output circuit for a solid-state imaging device according to claim 1, wherein said noise removing means is of an integral type correlated double sampling system. 7. The circuit according to claim 6, wherein at least the noise removing unit is formed on an integrated circuit chip, and the video signal output circuit includes a gain and an error coefficient of an integrated circuit resistance in opposite phases. The circuit further includes correction means for canceling the error coefficient, wherein the correction means includes a feedback resistor formed on the integrated circuit chip, and a feedback resistor formed on the integrated circuit chip and connected to the feedback resistor. An operational amplifier having an input / output terminal and including an error coefficient of the feedback resistor in a gain; and a reference resistor connected in series to an input of the operational amplifier and external to the integrated circuit chip. An output circuit for a solid-state imaging device, which receives a video signal and thereby cancels the error coefficient. 8. The circuit according to claim 6, wherein the noise elimination means and the first pulse signal generation means are formed on a common integrated circuit chip. An error coefficient of a negative phase of the integrated circuit resistance and the capacitance of the capacitor included in the gain is offset by the error coefficient of the integrated circuit resistance and the capacitance of the capacitor during the integration period of the second timing signal. Output circuit. 9. A solid-state imaging device that outputs an output signal representing an image in response to a first timing signal, and receives the output signal and extracts a feed-through signal and a pixel signal for each pixel of the output signal. And a noise removing unit that removes noise from the pixel signal and outputs a continuous video signal in pixel units, wherein the device comprises: a timing signal generating unit that generates a first timing signal; Generating an analog signal that repeatedly increases and decreases the voltage in synchronization with the first timing signal, compares the analog signal with a plurality of reference voltages intersecting the analog signal, and extracts the feedthrough signal and the pixel signal. Generating at least one second timing signal having a predetermined timing, and supplying the second timing signal to the noise removing means. The solid-state imaging device which comprises a pulse signal generating means.