JPH1011049A - Overlay display method and display overlay device - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To improve the horizontal resolution of an overlay video signal by increasing the vertical resolution and realize a good overlay display without image quality deterioration. When a 4-dot / 3-dot overlay video signal is displayed at 4 dots per pixel in an 8.6-dot overlay window, the horizontal pixel row of line 1 of the overlay video signal has an odd number of pixels (a, c). And even-numbered pixels (b,
d) It is divided into two pixel groups. Odd pixels are
The pixels are displayed on the corresponding horizontal line of the overlay window, and the even-numbered pixels are displayed on the subsequent horizontal lines. In this manner, in the 8 × 6 dot overlay window, odd and even pixels in each horizontal pixel row of the overlay video signal are displayed over two consecutive lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an overlay display method and a display overlay apparatus, and more particularly to an overlay display method and a display overlay for displaying an overlay video signal superimposed on a display screen of an image display device such as a computer display monitor. Related to the device.

[0002]

2. Description of the Related Art As a technique for embedding and displaying other video data such as a TV image on an image display device such as a CRT display used as a display monitor of a computer, an overlay display technique (screen ov) is used.
erlay) are known. As one of the methods, an analog overlay display method is known. In this analog overlay display method, an area (overlay window) on which a video output is superimposed and displayed on a display screen of a computer is set to a specific color called a chroma key or the like, and a video signal to be overlaid is analog-displayed in that part. This is a method of combining images and displaying them. FIG. 8 shows a configuration of a conventional display overlay display device using this analog overlay display method.

As shown in FIG. 8, a display overlay display device 4 is provided between a display controller 2 of a computer 1 and an analog CRT display 3. An input circuit 5 for generating an overlay video signal (ODATA);
DATA) and the analog video signal (DDATA) from the display controller 2 to switch the analog CR.
And a selector 6 for outputting to the T display 3. The horizontal / vertical synchronization signals (HSYNC, VSYNC) from the display controller 2 are sent to the analog CRT display 3 as they are. As a result, the analog CRT display 3 displays the analog video signal (D
(DATA).

In recent years, the resolution of an image display device of a computer has been increased, and accordingly, the frequency of a dot clock (DCLK) for defining a time required for displaying one pixel of an analog video signal (DDATA) has been increased. Is also getting higher. For example, when displaying a screen at 1600 × 1280 dots, a dot clock (DCLK) of about 220 MHz is used. The display controller 2 is configured to operate in synchronization with the dot clock (DCLK).

On the other hand, many display overlay display devices 4 operate in synchronization with a relatively low frequency, usually 60 MHz, dot clock (OCLK) which conforms to a standard corresponding to a TV video signal such as NTSC. It is configured as follows. The minimum output time interval of the analog overlay video signal (ODATA) to the analog CRT display 3 is defined by the dot clock (OCLK).

Therefore, when overlaying on a high-resolution display screen, it is necessary to reduce the horizontal resolution of the analog overlay video signal (ODATA) by performing pixel thinning or interpolation processing. This is shown in FIG.

FIG. 9A shows an analog video signal (DD) when the display screen of the CRT display 3 has a low resolution.
ATA) and analog overlay video signal (ODATA)
FIG. 9 (b) shows the relationship between the output timings.
The relationship between the output timing of the analog video signal (DDATA) and the output timing of the analog overlay video signal (ODATA) when the display screen of the T display 3 has a high resolution is shown.

As can be seen from FIG. 9B, the frequency of the dot clock (DCLK) on the display screen is 220 MHz, which is about four times the 60 MHz dot clock (OCLK) for the analog overlay video signal (ODATA). In this case, the same one pixel of the analog overlay video signal (ODATA) is displayed on the CRT display 3 over a display period of 4 dots that are continuous in the horizontal direction of the display screen.
Will be output to In this case, if the number of dots in one horizontal line of the overlay window is the same as the number of pixels in the horizontal direction of the analog overlay video signal (ODATA), the analog overlay video signal (ODATA) that can be displayed on one horizontal line of the overlay window is used. ) Is １ ／ of the number of horizontal pixels of the original image of the analog overlay video signal (ODATA). For this reason, the resolution in the horizontal direction is reduced to ４, and the image quality of the overlay video signal (ODATA) is deteriorated. This situation is shown in FIGS. 10 (a) and 10 (b).

Here, an overlay video signal (ODAT)
The size of A) is 720/480 dots, and
72 specified on the display screen of 600/1280 dots
A case where the image is displayed in an overlay window of 0.480 dots is shown. In this case, the horizontal resolution is 1 /
As a result, the effective resolution of the overlay video signal (ODATA) displayed in the overlay window becomes 180.480 dots.

[0010]

Therefore, recently, when a video signal such as a TV is displayed on such a high-resolution display screen as an overlay, an overlay video signal (OD) is required.
In order to reduce the deterioration of the image quality of the overlay video signal (ODAT), as shown in FIG.
An overlay window having a size about twice as large as the original image size is used, and an overlay video signal (O
DATA) is displayed. In this case, the number of pixels of the analog overlay video signal (ODATA) displayed on one horizontal line of the overlay window is 360 (= 720 ×
(1/4) · 2). Therefore, an overlay video signal (ODATA) displayed in the overlay window
The effective resolution in the horizontal direction is 360 dots, and in the horizontal direction, the image quality deterioration of the overlay video signal (ODATA) can be reduced to half.

However, in this method, in the vertical direction, pixels on the same line of the overlay video signal (ODATA) are simply displayed repeatedly over two lines. For this reason, regarding the size of the overlay window in the vertical direction, the overlay video signal (ODATA)
However, there is a problem that the image quality is not effectively used at all for reducing the image quality deterioration.

The present invention has been made in view of such a point, and makes it possible to compensate for the deterioration of the horizontal resolution of an overlay video signal by increasing the vertical resolution, thereby making the vertical size of the overlay window effective. Use it,
An object of the present invention is to provide an overlay display method and a display overlay display device capable of realizing good overlay display without image quality deterioration.

[0013]

According to the present invention, an output timing is specified by a clock having a frequency lower than a dot clock frequency necessary for displaying the display screen on an overlay window on a display screen of an image display device. In an overlay display method of displaying an overlay video signal in a superimposed manner, each horizontal pixel column of the overlay video signal is divided into a plurality of pixel groups in units of the number of pixels that can be output on one horizontal line of the overlay window, and The plurality of pixel groups belonging to a pixel column are successively displayed on a plurality of vertically adjacent horizontal lines on the overlay window, and one horizontal pixel column of the overlay video signal is displayed by the plurality of horizontal lines. It is characterized by displaying.

In this overlay display method, each horizontal pixel row of the overlay video signal is divided into a plurality of pixel groups in units of the number of pixels that can be output on one horizontal line of the overlay window. In this case, the number of group divisions of each horizontal pixel column of the overlay video signal is determined by the ratio of the dot clock frequency required for display on the display screen to the clock frequency that defines the output timing of the overlay video signal, and the original image of the overlay video signal. It can be determined by the ratio between the size and the window size of the overlay window. For example, an overlay window is used which has a dot clock frequency required for displaying the display screen four times the clock frequency that defines the output timing of the overlay video signal and has a window size twice the original image size of the overlay video signal. In this case, each horizontal pixel column of the overlay video signal is divided into two pixel groups such as odd pixels and even pixels.

One of the plurality of pixel groups belonging to the same horizontal pixel column is displayed on a corresponding horizontal line of the overlay window, and the remaining pixel groups are sequentially displayed on subsequent horizontal lines. As a result, one horizontal pixel column of the overlay video signal can be continuously displayed on a plurality of vertically adjacent horizontal lines on the overlay window without thinning.
Therefore, one horizontal pixel column of the overlay video signal is displayed by the plurality of horizontal lines,
The deterioration of the horizontal resolution of the overlay video signal can be compensated for by increasing the vertical resolution. Therefore, the size of the overlay window in the vertical direction can be effectively used, and good overlay display without image quality degradation can be realized.

Further, by displaying the display start positions of a plurality of pixel groups displayed on a plurality of adjacent horizontal lines shifted from each other in the horizontal direction, an overlay display closer to the original image can be realized.

For example, when each horizontal pixel row of the overlay video signal is divided into odd-numbered pixels and even-numbered pixels and displayed on two adjacent horizontal lines, the display start position of the even-numbered pixels is determined by the display position of the overlay video signal. By delaying by half the number of dots required for one-pixel display, the relationship between the display positions of the odd-numbered pixels and the even-numbered pixels can be made similar to the pixel arrangement of the original image. In this case, by further determining the value of each pixel by interpolation processing, it is possible to perform an overlay display closer to the image of the original image.

Further, according to the present invention, an overlay window on a non-interlaced display screen of an image display device is provided.
In an overlay display method for displaying an overlay video signal of an interlaced scan in which output timing is specified by a clock having a frequency lower than a dot clock frequency required for display of the display screen, the horizontal pixel row of the overlay video signal is displayed. Is divided into a plurality of pixel groups in units of the number of pixels that can be output on one horizontal line of the overlay window, and during the display period of the first screen of the display screen, each horizontal pixel corresponding to an odd field of the overlay video signal is Columns are continuously displayed on the corresponding odd-numbered line on the overlay window and on even-numbered lines adjacent thereto on a pixel group basis, and the overlay image is displayed during a display period of a second screen subsequent to the first screen. Each horizontal pixel column corresponding to the even field of the signal is represented by the pixel group. The display is performed continuously on the corresponding even-numbered line on the overlay window and the odd-numbered line adjacent thereto, and the odd-numbered field and the even-numbered field of the overlay video signal are alternately displayed on the same horizontal line. Features.

In this overlay display method, the odd field and the even field of the overlay video signal are separately divided into pixel groups and displayed on a plurality of horizontal lines, whereby the odd field and the even field of the overlay video signal are displayed. The fields and the fields are displayed alternately with some being superimposed on the same horizontal line. Therefore, while the size of the overlay window in the vertical direction is reduced, the deterioration of the horizontal resolution of the overlay video signal can be compensated for by increasing the vertical resolution.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. First, the principle of an overlay display method according to an embodiment of the present invention will be described with reference to FIG. In this overlay display method, an area (overlay window) on which a video output is superimposed and displayed on a display screen of a computer is set to a specific color called a chroma key or the like, and a video signal to be overlaid is analog-displayed in that part. In this case, as in the case of FIG. 10, the overlay video signal (O
DATA) is 720.480 dots, and the principle of the overlay display will be described by exemplifying a case in which this is displayed in a 720.480 dot overlay window defined on a 1600.1280 dot display screen.

As described above, the frequency of the dot clock (DCLK) that defines the time required to display one pixel on the display screen of 1600 × 1280 dots is 220M.
Hz and a dot clock (OC) of an overlay video signal conforming to a standard corresponding to a TV video signal such as NTSC.
LK) is 60 MHz. In this case, 720
Since the number of pixels of the overlay video signal that can be displayed on one horizontal line of the 480 dot overlay window is 360, each horizontal pixel row of the overlay video signal is divided into two groups of an odd pixel group and an even pixel group. Divided. The odd-numbered pixel group belonging to the first horizontal pixel column of the overlay video signal is displayed on the first horizontal line of the overlay window over four consecutive dots of the overlay window per pixel. The even-numbered pixel group belonging to the first horizontal pixel column of the overlay video signal is also displayed on the second horizontal line of the overlay window over four consecutive dots of the overlay window per pixel. In this way,
Each horizontal pixel column of the overlay video signal is displayed on two consecutive horizontal lines of the overlay window.

Therefore, the effective resolution in the horizontal direction of the overlay video signal (ODATA) displayed in the overlay window is 360 dots, but in the vertical direction, 960 different pixel columns are displayed. . In this case, the effective resolution of the overlay video signal (ODATA) displayed in the overlay window is 360/960 dots. Further, since 720 dots forming one horizontal pixel row of the overlay video signal (ODATA) are displayed on two consecutive horizontal lines of the overlay window, two consecutive lines of the overlay window are displayed.
If the horizontal line is regarded as one horizontal pixel column of the overlay video signal (ODATA), the overlay video signal (ODAT)
The effective resolution of A) is 720/480 dots.

Therefore, it is possible to compensate for the deterioration in the horizontal resolution of the overlay video signal by increasing the vertical resolution, and to realize an overlay display with no image quality result by effectively utilizing the vertical size of the overlay window.

Next, a specific configuration of a display overlay display device to which the overlay display method is applied will be described with reference to FIG. The display overlay display device 14 is provided between the display controller 12 of the computer 11 and the analog CRT display 13, and as shown in FIG.
1, a switching timing generation circuit 142, an overlay video signal input circuit 143, an overlay video signal generation circuit 144, a frame buffer control circuit 145, and a frame buffer 147.

The selector 141 receives the analog overlay video signal (ODATA) and the display controller 12
The switching timing is controlled by the logic 1 and 0 of the switching signal (SELECT) from the switching timing generation circuit 142. The switching timing generation circuit 142 receives the horizontal / vertical synchronization signals (HSYNC, VSYNC) and the video signal (DDATA) from the display controller 12, and generates a switching signal (SELECT) from these signals. That is, the switching timing generation circuit 142 detects the presence or absence of a chroma key from the video signal (DDATA) every horizontal display period, and outputs an overlay video signal (ODATA) in an overlay window designated by the chroma key. In the area, the logic of the switching signal (SELECT) is switched and controlled so that the analog video signal (DDATA) from the display controller 12 is output. The switching timing generation circuit 142 operates in synchronization with the dot clock (OCLK) of the overlay video signal, and the switching of the logic of the switching signal (SELECT) is performed in synchronization with the dot clock (OCLK).

The overlay video signal input circuit 143 is
An overlay video signal (ODATA) from the outside is input in synchronization with the dot clock (OCLK), and the overlay video signal (ODATA) is input to the frame buffer 1 via the frame buffer control circuit 145.
47. Overlay video signal generation circuit 143
Are the overlay video signals (O
DATA) is input via the frame buffer control circuit 145, and is converted into an RGB signal or the like, and then output to the selector 141 in synchronization with the dot clock (OCLK).

The frame buffer control circuit 145 outputs an overlay video signal (OD) to the frame buffer 147.
ATA) to control writing and reading, and here a memory address control circuit 146 is built-in. This memory address control circuit 146
Each horizontal connected column of the overlay video signal (ODATA) is continuously displayed on a plurality of vertically adjacent horizontal lines on the overlay window in units of the number of pixels that can be output on one horizontal line of the overlay window. The write address or read address of the frame buffer 147 is scanned to
47, the image storage format of the overlay video signal or the sequence of reading the pixels of the overlay video signal from the frame buffer 147 is controlled.

In this case, the overlay video signal (ODAT
A) The number of group divisions of each horizontal pixel column is the ratio of the dot clock frequency (DCLK) required for display on the display screen to the dot clock (OCLK) that defines the output timing of the overlay video signal, and the ratio of the overlay video signal. It can be determined by the ratio between the original image size (overlay video resolution) and the window size of the overlay window (overlay window resolution). For example,
As described with reference to FIG. 1, the frequency of the dot clock (DCLK) required for displaying the display screen is 220 MHz, and the dot clock (OCLK) that defines the output timing of the overlay video signal (ODATA) from the overlay video signal generation circuit 144 ) Is 60 MHz and the original image size of the overlay video signal (ODATA) is 2
When an overlay window having a double window size is used, an overlay video signal (ODATA)
Is divided into two pixel groups of odd-numbered pixels and even-numbered pixels, and the image storage format of the overlay video signal on the frame buffer 147 so that they are displayed continuously on two horizontal lines. Alternatively, the order of reading the pixels of the overlay video signal from the frame buffer 147 is controlled.

Next, the operation of the display overlay display device 14 will be specifically described with reference to FIGS. Here, the frequency of the dot clock (OCLK) is 1/4 of the dot clock (DCLK), and as shown in FIG.
TA) is assumed to be displayed in an overlay window of 8 dots × 6 dots. Also, here
4 dot x 3 dot overlay video signal (ODAT
A) is the frame buffer 14 with the pixel arrangement with the original image.
7, a case where an image of an overlay window is obtained by controlling the pixel reading order of the overlay video signal from the frame buffer 147 will be described.

As shown in FIG. 4, the video signal (DDATA) from the display controller 12 is sent to the selector 141 in synchronization with the dot clock (DCLK). The horizontal / vertical synchronization signals (HSYNC, VSYNC) from the display controller 12 are sent to the analog CRT display 13 as they are.

The selector 141 selects the video signal (ODAT) up to the second dot on the third horizontal line.
As a result, the video signal (DDATA) is displayed on the screen as an overlay video. 3rd of 3rd horizontal line
From the dot, the selector 141 changes the output signal from the video signal (DDATA) to the overlay video signal (ODAT).
Switch to A). In this case, the overlay video signal (ODATA) is output in the order of pixels read from the frame buffer 147 by the memory address control circuit 146.
Is sent to the analog CRT display 13 and displayed over 4 dots per pixel.

The memory address control circuit 146 updates the read address by +2 while the frame buffer 14
7, an overlay video signal (ODATA) is read.
Thus, during the display period from the third dot to the sixth dot of the third horizontal line, the overlay video signal (ODAT) is displayed.
The pixel a of A) is output from the selector 141, and the pixel c of the overlay video signal (ODATA) is output from the selector 141 during the display period from the seventh dot to the tenth dot on the third horizontal line.

The selector 141 again outputs the video signal (DDATA) up to the second dot on the fourth horizontal line.
Is selected. During the subsequent display period from the third dot to the sixth dot, the pixel b of the overlay video signal (ODAT) is output from the selector 141, and the pixel b of the fourth horizontal line is output.
During the display period from the dot to the tenth dot, the pixel d of the overlay video signal (ODATA) is output from the selector 141.

In this way, as shown in FIG. 3, in the overlay window of 8 dots × 6 dots,
Odd and even pixels in each horizontal pixel column of the overlay video signal (ODATA) are displayed over two consecutive lines, and two consecutive horizontal lines of the overlay window can be regarded as one horizontal pixel column of the overlay video signal (ODATA). For example, the effective resolution of the overlay video signal (ODATA) is the same as the original image, ie, 4 dots / 3 dots.

FIG. 5 shows a second display form of the overlay video. This display mode is the same as FIG. 3 in that odd pixels and even pixels in each horizontal pixel column of an overlay video signal (ODATA) are displayed over two continuous lines, but pixels vertically arranged on an overlay window are displayed. The display start position of the column is shifted by 2 dots.
As a result, the display start position of the even-numbered pixels (b, d, f, h) is delayed by half of the four dots required for displaying one pixel of the overlay video signal, and the odd-numbered pixels (a, c, e, g, i, k) )
And the display position of the even-numbered pixels (b, d, f, h) can be in a form close to the pixel arrangement of the original image.

FIG. 6 shows a third display mode of the overlay video. This display mode is the same as FIG. 5 in that the display start positions of the pixel columns displayed on two adjacent horizontal lines are shifted from each other in the horizontal direction.
Here, each display pixel is further obtained by interpolation. This interpolation processing is performed based on the original pixel arrangement of the original image of the overlay video signal.

That is, considering the original pixel arrangement of the original image of the overlay video signal, the pixel a is located at the third and fourth dots on the third and fourth lines of the display screen, respectively. Pixel b in the eyes,
The pixel c is arranged at the seventh and eighth dots, and the pixel d is arranged at the ninth and tenth dots.
In the four dots from the third dot to the sixth dot of the line, (a + b) / 2 which is a value obtained by interpolating the pixels a and b, which should be originally displayed, is added to the fourth dot. (C + d) / 2, which is a value obtained by interpolating the pixels c and d, which should be originally displayed there, is displayed in the four dots from the dot to the tenth dot.
Further, in the fourth line of the display screen, the four dots from the fifth dot to the eighth dot are the values obtained by interpolating the pixels b to be originally displayed there and the pixels b (b + c). / 2 is displayed, and pixels a and d are displayed as they are in the preceding four dots and the subsequent four dots, respectively.

In this way, by obtaining the value of each pixel to be displayed in the overlay by interpolation, it is possible to perform display closer to the original image. FIG. 7 shows a fourth display mode of the overlay video.

This display mode is an example of a display in which an interlaced overlay video signal is overlaid on a non-interlaced overlay video. Here, the ratio of the dot clock is 1/2, and the ratio of 4.4 dots is set. An overlay window is used.

In the first display screen, the odd pixels a and c of the line 1 of the overlay video signal are displayed on the second horizontal line of the display screen, and the even pixels b of the line 1 of the overlay video signal are displayed on the third horizontal line. , D are displayed. Also,
On the fourth horizontal line, odd-numbered pixels i and k of line 3 of the overlay video signal are displayed, and on the fifth horizontal line, even-numbered pixels j and l of line 3 of the overlay video signal are displayed.

In the second display screen thereafter, odd pixels e and g of line 2 of the overlay video signal are displayed on the third horizontal line of the display screen, and the fourth horizontal line is displayed on the second horizontal line of line 2 of the overlay video signal. The even pixels f and h are displayed.

As described above, by separately dividing a pixel group and displaying on a plurality of horizontal lines separately for the odd field and the even field of the overlay video signal, the odd field and the even field of the overlay video signal are the same. A part of the screen is superimposed on the horizontal line and displayed alternately for each screen. Therefore, it is possible to increase the vertical resolution of the overlay video signal while saving the size of the overlay window in the vertical direction.

[0043]

As described above, according to the present invention, the deterioration of the horizontal resolution of the overlay video signal can be compensated for by increasing the vertical resolution, thereby making it possible to effectively reduce the size of the overlay window in the vertical direction. It is possible to achieve good overlay display without image quality degradation by utilizing the present invention.

[Brief description of the drawings]

FIG. 1 is a view for explaining the principle of an overlay display method according to an embodiment of the present invention.

FIG. 2 is an exemplary block diagram showing an example of a specific configuration of a display overlay device to which the overlay display method of the embodiment is applied.

FIG. 3 is an exemplary view showing a first example of an overlay display mode according to the overlay display method of the embodiment;

FIG. 4 is a timing chart for explaining the operation of the display overlay device of FIG. 2 corresponding to the overlay display mode of FIG. 3;

FIG. 5 is an exemplary view showing a second example of an overlay display mode according to the overlay display method of the embodiment.

FIG. 6 is an exemplary view showing a third example of an overlay display mode according to the overlay display method of the embodiment.

FIG. 7 is an exemplary view showing a fourth example of an overlay display mode according to the overlay display method of the embodiment;

FIG. 8 is a block diagram showing a configuration of a conventional display overlay display device.

FIG. 9 is a timing chart illustrating the operation of a conventional display overlay display device.

FIG. 10 is a diagram for explaining the principle of overlay display by a conventional display overlay display device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Computer, 12 ... Display controller, 13 ... CRT display, 14 ... Display overlay display device, 141 ... Selector, 142 ... Switching timing generation circuit, 143 ... Overlay video signal input circuit, 144 ... Overlay video signal generation circuit, 14
5: Frame buffer control circuit, 147: Frame buffer.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁶ Identification code Agency reference number FI Technical display location H04N 5/45 G06F 15/72 K

Claims (8)

[Claims] 1. An overlay video signal whose output timing is specified by a clock having a frequency lower than a dot clock frequency required for displaying the display screen is superimposed and displayed on an overlay window on a display screen of an image display device. In the overlay display method, each horizontal pixel column of the overlay video signal is divided into a plurality of pixel groups in units of the number of pixels that can be output on one horizontal line of the overlay window, and the plurality of pixels belonging to the same horizontal pixel column An overlay, wherein groups are displayed continuously on a plurality of vertically adjacent horizontal lines on the overlay window, and one horizontal pixel column of the overlay video signal is displayed by the plurality of horizontal lines. Display method. 2. The number of group divisions of each horizontal pixel column of the overlay video signal is defined by a ratio of a dot clock frequency required for display on the display screen to a clock frequency defining output timing of the overlay video signal, and The overlay display method according to claim 1, wherein the overlay display method is determined by a ratio between an original image size of the overlay video signal and a window size of the overlay window. 3. The vertical size of the overlay window is at least twice the vertical size of the overlay video signal, and each horizontal pixel column of the overlay video signal is divided into an odd pixel group and an even pixel group. 2. The display according to claim 1, wherein the odd-numbered pixel groups and the even-numbered pixel groups belonging to the same horizontal pixel column are successively displayed on two vertically adjacent horizontal lines on the overlay window. Overlay display method. 4. The overlay display method according to claim 1, wherein display start positions of said plurality of pixel groups displayed on said plurality of adjacent horizontal lines are shifted from each other in a horizontal direction. 5. The display start position of the even-numbered pixel group is delayed from the display start position of the odd-numbered pixel group by half the number of dots required for displaying one pixel of the overlay video signal. Described overlay display method. 6. An interpolating process between the pixels of the overlay video signal based on a relationship between a pixel array of an original image of the overlay video signal and a pixel array displayed in the overlay window. 6. The overlay display method according to claim 4, wherein the displayed pixels are displayed in the overlay window. 7. An interlaced scanning overlay video signal whose output timing is specified by a clock having a frequency lower than a dot clock frequency required for displaying the display screen on an overlay window on a non-interlaced display screen of an image display device. In the overlay display method of superimposing and displaying, the respective horizontal pixel columns of the overlay video signal are divided into a plurality of pixel groups in units of the number of pixels that can be output on one horizontal line of the overlay window. During a display period of one screen, each horizontal pixel column corresponding to an odd field of the overlay video signal is
The display is continuously performed on the corresponding odd-numbered line on the overlay window and the even-numbered line adjacent thereto in the pixel group unit, and during the display period of the second screen following the first screen, the even number of the overlay video signal is displayed. Each horizontal pixel column corresponding to a field is continuously displayed on the corresponding even-numbered line on the overlay window and the odd-numbered line adjacent thereto in the pixel group unit, and the odd field and the even field of the overlay video signal are displayed. Overlaid on the same horizontal line and displayed alternately. 8. An overlay video signal whose output timing is specified by a clock having a frequency lower than a dot clock frequency required for displaying the display screen is superimposed on an overlay window on a display screen of the image display device. A frame buffer in which the overlay video signal is stored; means for reading out the overlay video signal from the frame buffer and displaying the overlay video signal on an overlay window; In order to continuously display a plurality of vertically adjacent horizontal lines on the overlay window in units of the number of pixels that can be output on one horizontal line of the window,
Means for scanning a write address or a read address of the frame buffer to control an image storage format of the overlay video signal on the frame buffer or a pixel reading order of the overlay video signal from the frame buffer. Display overlay device characterized by the following.