JPH10112504A - Wiring delay adjustment circuit, semiconductor integrated circuit, and wiring delay adjustment method - Google Patents

Abstract

(57) [Problem] To provide a technique for easily adjusting a wiring delay. SOLUTION: A delay adjustment line (10, 20, 30) laid out near a signal transmission path (17).
A wiring delay adjusting circuit including a switch (Q1, Q2, Q3) capable of selectively supplying a reference voltage level to the delay adjusting line, and a programmable link for determining the ON / OFF state of the switch To form
By determining the ON / OFF state of the switch using a programmable link, the delay adjustment line laid out near the signal transmission path and the capacitance formed between the delay adjustment line can be selectively adjusted. And thereby facilitate the wiring delay adjustment.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring delay adjusting technique, and more particularly to a technique effective when applied to delay adjustment of a clock signal transmission path in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art When designing the layout of a semiconductor integrated circuit (LSI), elements such as transistors and capacitors are mounted on a chip to reduce the time and labor required for the design and to facilitate various verifications. Rather than laying out one by one, it is necessary to arrange these functional blocks and wire between them after completing layout design for each functional block, that is, for each functional block. General.

In recent years, as the degree of integration of semiconductor integrated circuits has increased and the size thereof has increased, the length of wiring within the semiconductor integrated circuit, particularly the wiring for supplying clock signals to each functional block, has become longer. The delay of the clock signal cannot be ignored. That is, if the phase of the clock signal commonly supplied to a plurality of functional blocks is shifted between the functional blocks due to the wiring delay, the operation of the semiconductor integrated circuit as a whole is hindered. Becomes

As a technique for knowing the timing shift of a clock signal, as described in Japanese Patent Application Laid-Open No. 64-2334, each of the same branched signal or each signal having a predetermined phase relationship is disclosed. A technique is known in which buffer means is provided at the end of a signal line for supplying the signal to each circuit block, the signals output from the buffer means are compared, and the phase difference between the signals is detected based on the comparison result.

[0005]

When a clock signal supplied from outside a semiconductor integrated circuit is distributed to various parts of the semiconductor integrated circuit, clock skew (clock phase shift) at an end of a clock transmission path is reduced. For this reason, the wiring is arranged and wired so that the lengths of the clock transmission paths from the external terminal for clock input to the above-mentioned parts become equal.

However, in practice, an undesired capacitance is formed between the clock transmission path and a signal transmission path arranged near the clock transmission path, and the wiring delay of the clock transmission path deviates from a designed value. There is. If the clock skew cannot be suppressed to a negligible level at the end of the clock transmission path, in many cases, a test after the completion of the semiconductor chip is determined to be a delay defect, which affects the yield of the semiconductor integrated circuit.

An object of the present invention is to provide a technique for easily adjusting a wiring delay.

Another object of the present invention is to improve the yield of semiconductor integrated circuits by enabling wiring delay adjustment.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, the delay adjusting lines (10, 20,...) Laid out near the signal transmission path (17).
30) and switches (Q1, Q2, Q3) capable of selectively supplying a reference voltage level to the delay adjustment line
And a programmable link (F1, F2, F3) for determining the ON / OFF state of the switch, to form a wiring delay adjustment circuit.

When a semiconductor integrated circuit including a logic circuit (FF) and a signal transmission path (17) for transmitting a signal to the logic circuit is formed, a delay laid out near the signal transmission path is formed. Adjustment line (10, 2
0, 30) and semiconductor switches (Q1, Q2) that can selectively supply a reference voltage level to this delay adjustment line.
, Q3) and a programmable link (F1, F2, F2) for determining the ON / OFF state of the semiconductor switch.
3) is provided.

At this time, the delay adjustment line is
Lines (1) formed parallel to the signal transmission path at the minimum pitch of the wiring layout in the automatic placement and routing.
1, 12). A first external terminal (T1, T2, T3) for receiving a signal capable of controlling the operation of the semiconductor switch from outside the semiconductor integrated circuit irrespective of the state of the programmable link;
Can be provided. Further, a logic inversion circuit (81) for performing signal inversion, and a ring oscillator forming switch (82) capable of forming a ring oscillator including the logic inversion circuit and the signal transmission path (17) are formed. A second external terminal (T82) that enables measurement of the oscillation frequency of the ring oscillator can be included. In order to efficiently perform fine adjustment of the wiring delay, a plurality of lines may be formed as a plurality of delay adjustment lines, and the length ratio of the plurality of lines may be set to 1: 2: 4: 8.

A delay adjusting line (10, 20, 30) laid out near the signal transmission path, and switches (Q1, Q2, Q3) capable of selectively supplying a reference voltage level to the delay adjusting line. When performing a wiring delay adjustment using a wiring delay adjusting circuit including programmable links (F1, F2, F3) for determining the ON / OFF state of the switch, a desired wiring is controlled by controlling the operation of the switch. The delay state is detected (S2, S3, S4), and the link state of the programmable link is set based on the detection result (S2).
5).

A logic circuit (FF), a signal transmission path (17) for transmitting a signal to the logic circuit, and delay adjustment lines (10, 20, 30) laid out near the signal transmission path. A semiconductor switch (Q1, Q2, Q3) capable of selectively supplying a reference voltage level to the delay adjustment line;
Programmable link (F
1, F2, F3), a desired wiring delay state is detected by controlling the operation of the switch (S2, S3).
S4) The link state of the programmable link is set based on the detection result (S5).

A logic circuit (FF), a signal transmission path (17) for transmitting a signal to the logic circuit, and delay adjustment lines (10, 20, 30) laid out near the signal transmission path; A semiconductor switch (Q1, Q2, Q3) capable of selectively supplying a reference voltage level to the delay adjustment line;
Programmable link (F
1, F2, F3) and a first external terminal (T0) for receiving a signal capable of controlling the operation of the semiconductor switch from outside the semiconductor integrated circuit irrespective of the state of the programmable link. When performing the wiring delay adjustment in the integrated circuit, a desired wiring delay state is detected by controlling the operation of the switch based on an operation control signal supplied from outside via the first external terminal (S2, S
3, S4), based on the detection result, sets the link state of the programmable link (S5).

A logic circuit (FF), a signal transmission path (17) for transmitting a signal to the logic circuit, and delay adjustment lines (10, 20, 30) laid out near the signal transmission path. A semiconductor switch (Q1, Q2, Q3) capable of selectively supplying a reference voltage level to the delay adjustment line;
Programmable link (F
1, F2, F3), a first external terminal (T0) for taking in a signal capable of controlling the operation of the semiconductor switch from outside the semiconductor integrated circuit irrespective of the state of the programmable link, and a signal inversion. Logic inversion circuit (81), a ring oscillator forming switch (82) capable of forming a ring oscillator including the logic inversion circuit and the signal transmission path, and external measurement of the oscillation frequency of the formed ring oscillator When performing wiring delay adjustment in a semiconductor integrated circuit including a second external terminal (T82) that enables the operation of the switch based on an operation control signal supplied from outside through the first external terminal. Each time, the oscillation frequency of the ring oscillator is measured via the second external terminal (S2, S3), and based on this measurement result, For information for link status setting log llama Bull link (S4), it sets the link state of the programmable link based on this information (S5).

According to the above-mentioned means, the on / off state of the switch is determined by the programmable link, so that the delay adjustment line laid out near the signal transmission path, the signal line and the delay adjustment line The capacitance formed between them can be selectively involved in the wiring delay adjustment, which facilitates the wiring delay adjustment. By enabling such wiring delay adjustment, delay defects can be reduced, and the yield of semiconductor integrated circuits can be improved.

[0019]

FIG. 7 shows an example of a semiconductor integrated circuit according to the present invention.

The semiconductor integrated circuit 71 shown in FIG. 7 includes, but is not limited to, a plurality of flip-flop circuits FF, and is formed on one semiconductor substrate such as a single crystal silicon substrate by a known semiconductor integrated circuit manufacturing technique. You. The plurality of flip-flop circuits FF are operated in synchronization with a clock signal supplied from outside via a clock input external terminal T72 of the semiconductor integrated circuit.

In order to reduce the skew of the clock signal transmitted to the plurality of flip-flop circuits FF, the clock signal supplied from the clock input external terminal T72 is transmitted to the center of the semiconductor integrated circuit 71. From there it is distributed radially. That is, by automatically arranging and wiring the clock transmission paths 17 from the central part of the semiconductor integrated circuit to the clock input terminals of the plurality of flip-flop circuits FF, the wiring delay on the transmission paths is reduced. They are aligned.

However, in practice, an undesired capacitance is formed between the clock transmission path 17 and a signal transmission path arranged near the clock transmission path 17, and the wiring delay of the clock transmission path 17 deviates from the design value. Sometimes.

Therefore, the clock skew is reduced at the end of the clock transmission path by adjusting the wiring delay as follows.

FIG.
In the main part of the clock transmission path shown in FIG. 1, a delay adjustment line coupled to a semiconductor switch composed of an n-channel MOS transistor is laid out adjacent to the clock transmission path.

FIG. 1A shows a part of the clock transmission path 17 shown in FIG. 7 and a delay adjustment line laid out in the vicinity thereof. In FIG. 1A, a first delay adjustment line 10, a second delay adjustment line 20, and a third delay adjustment line 30 are representatively shown as the delay adjustment lines. Although not particularly limited, the first delay adjustment line 10, the second delay adjustment line 20, and the third delay adjustment line 3
0 have the same configuration as each other. For example, the first delay adjustment line 10 is located near the clock transmission path 17,
The first line 11 laid out in parallel with the clock transmission path 17, the second line 12 disposed opposite the first line 11 via the clock transmission path 17, the end of the first line 11, And a third line 13 laid out to join the end of the second line 12. When the clock transmission path 17, the first line 11, and the second line 12 are formed by first-layer metal wiring, the third line 13 avoids electrical contact with the clock transmission path 17. Therefore, the first
The second metal wiring is a wiring layer different from the layer metal wiring. The first line 11 and the third line 13, and the third line 13 and the second line 1
2 are electrically connected to each other by through holes TH. Note that the second delay adjustment line 20 and the third delay adjustment line
The delay adjustment line 30 also has the same configuration as the first delay adjustment line 10 described above.

A clock transmission path 17 is provided between each of the first delay adjustment line 10, the second delay adjustment line 20, and the third delay adjustment line 30, and the clock transmission path 17.
A predetermined capacitance C is formed as shown in FIG. This capacitance C functions for adjusting the wiring delay in the clock transmission path 17.

FIG. 2A is a plan view of the clock transmission path 17 and the first line 11 laid out in the vicinity thereof, and FIG.
A sectional view taken along line A 'is shown. In FIG. 2A, the insulating films CVD and SOG are omitted.

Clock transmission path 17 and first line 11
Is indicated by “a”, the parallel wiring length between the clock transmission path 17 and the first line 11 is indicated by “b”, the distance between the clock transmission path 17 and the first line 11 is indicated by “d”, When the dielectric constant between the transmission path 17 and the first line 11 is represented by ε, the clock transmission path 17 and the first line 11
And C = ε · S / d = ε · a · b / d.

The distance d between the clock transmission path 17 and the first line 11 is made equal to the minimum wiring pitch in the automatic placement and routing. Since the wiring pitch is fixed in the process,
The value of the capacitance C is adjusted according to the parallel wiring length b. Note that the distance between the clock transmission path 17 and the second line 12 is also the minimum wiring pitch in the automatic placement and routing.

In FIG. 1A, a first delay adjusting line 10, a second delay adjusting line 20, and a third
The delay adjustment line 30 includes the reference voltage 18
N-type MOS transistors Q1, Q2, Q3 for setting to the level of. The drain electrodes of the n-channel MOS transistors Q1, Q2, and Q3 are connected to the second line 12 of the first delay adjustment line 10, the second delay adjustment line 20, and the third delay adjustment line 30, respectively. They are connected via a line 14 made of metal wiring. n-channel type MO
The reference voltage 18 is supplied to the source electrodes of the S transistors Q1, Q2, Q3. Although the reference voltage 18 is not particularly limited, it is not limited to the ground potential of the circuit (for example,
ss level). Furthermore, n-channel type MOS
Delay adjustment signals φ1, φ2, φ3 are input to the gate electrodes of the transistors Q1, Q2, Q3. When the delay adjustment signal φ1 is asserted to the high level, the first delay adjustment line 10 is set to the ground potential of the circuit, and when the delay adjustment signal φ2 is asserted to the high level, the second delay adjustment line 20 is set to the circuit potential. When the delay adjustment signal φ3 is asserted to a high level, the third delay adjustment line 30 is set to the circuit ground potential. By setting the delay adjustment line to the ground potential of the circuit, the clock transmission path 17 and the first delay adjustment line 10, the second delay adjustment line 20, and the third delay adjustment line 30 are connected. The capacitance C formed therebetween acts to delay the clock transmitted through the clock transmission path 17. Since the delay amount increases as the value of the capacitance C increases, in the example shown in FIG.
When all of the OS transistors Q1, Q2, and Q3 are turned on, the delay amount is the largest, and the smaller the number of n-channel MOS transistors that are turned on, the smaller the delay amount. Therefore, the wiring delay at the n-channel type MOS transistors Q1, Q2, Q3 can be finely changed by the combination of ON and OFF.

FIG. 5 shows the delay adjustment signals φ1 to φ3.
Is shown. This switch control circuit 50 is mounted on the semiconductor integrated circuit 71 shown in FIG.

As shown in FIG. 5, the switch control circuit 50 includes, but is not limited to, fuses F1, F2, F3 as an example of a programmable link, and a selector 5
1, 52, and 53, and resistors R1, R2, R3, and R4. The selectors 51, 52, and 53 each have an input terminal I
N1, IN2, output terminal OUT, and select input terminal SE
I, and the input logic from the input terminals IN1 and IN2 is selectively changed to the output terminal O by the selector switching signal SEL input through the external terminal T0 of the semiconductor integrated circuit.
The data is output from the UT.

The input terminal IN1 of the selector 51 is
The input terminal IN of the selector 52 is coupled to the low-potential power supply Vss via the pull-down resistor R1 and to the high-potential power supply Vcc via the fuse F1.
1 is a low-potential-side power supply Vs via a pull-down resistor R2.
s, is coupled to the high-potential power supply Vcc via the fuse F2, and the input terminal IN1 of the selector 53 is coupled to the low-potential power supply Vss via the pull-down resistor R3. The power supply is connected to the high-potential-side power supply Vcc. Selector 51,
The selection input terminals SEI of 52 and 53 are coupled to the low-potential-side power supply Vss via the pull-down resistor R4, and are commonly connected to an external terminal T0 for taking in the selector switching signal SEL.

For example, when the select signal SEL is at a high level, the input logic from the input terminal IN1 is output to the output terminal OUT. When the select signal SEL is at a low level, the input logic from the input terminal IN2 is changed to the input logic. Output terminal O
Output to UT. In the test mode of the semiconductor integrated circuit 71, the select signal SEL is set to the low level, and the selectors 51, 52, and 53 control the MOS transistors respectively input via the external terminals T1, T2, and T3 of the semiconductor integrated circuit. Signals CON1 and CO
N2 and CON3 are selected. In this state, the MOS transistor control signals CON1, CON2, and CON3 input from outside the semiconductor integrated circuit respectively cause the signals shown in FIG.
N-channel MOS transistors Q1, Q shown in FIG.
2 and Q3.

In the actual use state of the semiconductor integrated circuit 71, the select signal SEL is always set to the high level, and the selectors 51, 52, and 53 select the input logic from the input terminal IN1. In this case, the fuses F1, F
2, selector 3 depending on whether F3 is melted or not.
Output logics from the output terminals OUT of 1, 52 and 53 are different. For example, if the fuse F1 is not blown, the delay adjustment signal φ1 output from the output terminal OUT is set to a high level. If the fuse F1 is blown, the delay adjustment signal φ1 output from the output terminal OUT is changed. The signal φ1 is at a low level.

FIG. 8 shows a connection state in the wiring delay adjustment of the semiconductor integrated circuit 71.

Clock transmission path 17 from clock input external terminal T72 to one flip-flop circuit FF
In FIG. 8, a plurality of delay adjustment lines are laid out. In FIG. 8, only the first delay adjustment line 10 is representatively shown. Further, an inverter (logic inversion circuit) 81 and a switch 82 for forming a ring oscillator including the clock transmission path 17 are provided.
In a state where the switch 82 is turned on, a ring oscillator is formed, and when one clock signal is input from the clock input external terminal T72, the oscillation operation of the ring oscillator is started. The oscillation frequency is basically determined by the amount of wiring delay in the clock transmission path 17. Therefore, by connecting a frequency measurement counter or an LSI tester to the external terminal T82 for frequency measurement, the oscillation frequency of the ring oscillator can be measured.

FIG. 6 shows a flowchart of the wiring delay adjustment.

First, the select signal SEL is set to low level, and the selectors 51, 52 and 53 are switched to external inputs (step S1). In this state, externally applied MOS transistor control signals CON1, CON2, CON2
CON3 allows n-channel MOS transistor Q
1, Q2, Q3 can be turned on / off. In this state, n-channel MOS transistors Q1, Q
2, on / off control of Q3 is performed (step S2),
The switch 82 is turned on for each combination of on / off of the n-channel MOS transistors Q1, Q2, Q3 to form a ring oscillator, and the oscillation frequency of the ring oscillator connected to the external terminal T82 for frequency measurement is changed. Measured. The frequency measurement is similarly performed on the clock transmission path from the clock input external terminal T72 to another flip-flop circuit FF.

Then, a fuse processing pattern is determined so that the oscillation frequencies of the ring oscillators are equal in different clock transmission paths (step S4). This fuse processing pattern is used to turn on / off the n-channel MOS transistors Q1, Q2, Q3 shown in FIG.
This corresponds to the combination of OFF.

After the fuse processing pattern is created in step S4, the corresponding fuse is blown based on the fuse processing pattern (step S5). Whether or not the fuse has been blown correctly according to the fuse processing pattern can be confirmed by switching the selectors 51, 52, 53 to the fuse side and measuring the oscillation frequency of the ring oscillator again in that case (step). S6). When the selectors 51, 52 and 53 are switched to the fuse side and the value obtained by measuring the oscillation frequency of the ring oscillator again in this case is equal to the value of the previously measured oscillation frequency, the fuse is blown correctly according to the fuse processing pattern. It will be done.

In the actual use state of the semiconductor integrated circuit 71, the select signal SEL is always set to the high level, and the selectors 51, 52 and 53 select the input logic from the input terminal IN1. In the actual use state, it is not necessary to form a ring oscillator, so the switch 82 is turned off.

According to the above example, the following functions and effects can be obtained.

(1) A first delay adjustment line 10, a second delay adjustment line 20, and a third delay adjustment line 30 laid out in the vicinity of the clock transmission path 17; N-channel MOS transistors Q1, Q2, and Q3 capable of supplying a reference voltage level to each other, and a fuse F for determining the ON / OFF state of the n-channel MOS transistor
1, F2, and F3, the capacitances formed between the delay adjustment lines 10, 20, and 30 and the clock transmission path 17 and the delay adjustment lines 10, 20, and 30 are selectively provided. It is possible to be involved in the wiring delay adjustment, whereby the wiring delay adjustment can be easily performed. By enabling such wiring delay adjustment, it is possible to reduce delay defects,
Further, the yield of semiconductor integrated circuits can be improved.

(2) In general automatic placement and routing,
A space for one wiring line is secured between the clock transmission path 17 and a wiring line adjacent thereto. This is to prevent formation of an undesired capacitance between the clock transmission path 17 and the wiring line adjacent thereto. On the other hand, in the above example, since the capacitance is positively formed, the distance between the clock transmission path 17 and the first line 11 and the distance between the clock transmission path 17 and the second line 12 are different from those in the automatic placement and routing. It is made equal to the minimum wiring pitch. Therefore, even when the first line 11 and the second line are formed using the same wiring layer as the clock transmission path 17, the size of the semiconductor chip is not affected. Also, when the first line 11 and the second line are set to the ground potential, the first line 11 and the second line act to shield the clock transmission path 17, so that the first line 11 and the second line are connected to other signal lines. This is advantageous in preventing crosstalk between the two.

(3) First with respect to the clock transmission path 17
The capacitance C for delay adjustment is obtained by laying out the line 11 and the second line 12 in parallel, and such capacitance formation is different from, for example, the case of using the gate capacitance of a MOS. Does not need to be affected. Even from this, the wiring delay adjustment described above can be easily performed.

Although the invention made by the inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist of the invention. No.

For example, as shown in FIG. 3, when the clock transmission path 17 is formed by a first layer metal wiring, a wiring delay adjustment line is formed by a second layer metal wiring, and the wiring delay adjustment line is formed. A capacitor C for adjusting the wiring delay may be formed between the clock transmission path 17 and the clock transmission path 17.

As described above, the capacitance for adjusting the wiring delay can be adjusted by the length of the parallel wiring b.
For example, as shown in FIG. 4, the length ratio of the plurality of adjustment lines 41, 42, 43, 44 used for delay adjustment is set to b: 2b: 4b: 8b = 1: 2: 4: 8. If set, the capacitance C for adjusting the wiring delay can be finely adjusted in 16 steps from 0 to 15 by a combination thereof.

In the above example, the wiring delay of the clock transmission path is adjusted. However, the present invention can be applied to the wiring delay adjustment of the signal transmission path for transmitting signals other than the clock.

The selectors 51 and 5 shown in FIG.
Instead of 2 and 53, a 2-input OR (OR) gate can be applied. In this case, the input terminal IN1 is made to correspond to one input terminal of the OR gate, and the input terminal IN
2 corresponds to the other input terminal of the OR gate, and the output terminal OUT corresponds to the output terminal of the OR gate. As described above, when the two-input OR is applied, it is not necessary to take in the select signal SEL from outside, so that the required number of external terminals can be reduced accordingly.

Further, as the reference voltage 18, a high-potential-side power supply Vcc or a half voltage Vcc / 2 may be supplied.

In the above description, the invention made by the present inventor has been mainly described with respect to the adjustment of the wiring delay inside the semiconductor integrated circuit, which is the application field in which the invention is based.
The present invention is not limited to this, and can be applied to, for example, wiring delay adjustment of a signal transmission path formed so as to mutually connect a plurality of semiconductor integrated circuits on a printed circuit board on which a plurality of semiconductor integrated circuits are mounted.

The present invention can be applied on condition that at least a signal transmission path is included.

[0055]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, by the programmable link,
By determining the ON / OFF state of the switch, the delay adjustment line laid out near the signal transmission path and the capacitance formed between the delay adjustment line are selectively involved in the wiring delay adjustment. It is possible,
Thereby, the wiring delay adjustment can be easily performed. By making such wiring delay adjustment possible, delay defects can be reduced, and the yield of semiconductor integrated circuits can be improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an example of a wiring delay adjustment circuit according to the present invention.

FIG. 2 is a diagram showing a plane of a main part of the wiring delay adjustment circuit and a cross section thereof.

FIG. 3 is a cross-sectional view illustrating another example of forming the wiring delay adjustment circuit.

FIG. 4 is an explanatory diagram of another layout example of the wiring delay adjustment circuit.

FIG. 5 is a circuit diagram illustrating a configuration example of a switch control circuit included in the wiring delay adjustment circuit;

FIG. 6 is a flowchart of wiring delay adjustment using the wiring delay adjustment circuit.

FIG. 7 is an overall explanatory diagram of a semiconductor integrated circuit to which the wiring delay adjustment circuit is applied.

FIG. 8 is a circuit diagram of a ring oscillator formed in wiring delay adjustment using the wiring delay adjustment circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1st delay adjustment line 20 2nd delay adjustment line 30 3rd delay adjustment line 11 1st line 12 2nd line 13 3rd line 17 Clock transmission path 71 Semiconductor integrated circuit T0, T1, T2, T3, T72 , T82 External terminals Q1, Q2, Q3 n-channel MOS transistor C capacitance

Claims (10)

[Claims] 1. A wiring delay adjusting circuit for adjusting a wiring delay of a signal transmission path, wherein a delay adjustment line laid out near the signal transmission path and a delay adjustment line are selectively referred to. A wiring delay adjustment circuit, comprising: a switch capable of supplying a voltage level; and a programmable link for determining an on / off state of the switch. 2. A semiconductor integrated circuit formed on one semiconductor substrate including a logic circuit and a signal transmission path for transmitting a signal to the logic circuit, wherein a delay laid out near the signal transmission path A semiconductor comprising: an adjustment line; a semiconductor switch capable of selectively supplying a reference voltage level to the delay adjustment line; and a programmable link for determining an on / off state of the semiconductor switch. Integrated circuit. 3. The delay adjustment line includes a line formed in parallel with the signal transmission path at a minimum pitch of a wiring layout in automatic placement and routing.
A semiconductor integrated circuit as described in the above. 4. The semiconductor integrated circuit according to claim 2, further comprising a first external terminal for receiving a signal capable of controlling the operation of the semiconductor switch from outside the semiconductor integrated circuit irrespective of the state of the programmable link. circuit. 5. A logic inversion circuit for performing signal inversion, a ring oscillator forming switch capable of forming a ring oscillator including the logic inversion circuit and the signal transmission path, and an oscillation frequency of the formed ring oscillator. The semiconductor integrated circuit according to claim 2, further comprising: a second external terminal that enables measurement. 6. A plurality of lines are formed for a plurality of delay adjustments, and the length ratio of the plurality of lines is 1: 1:
6. The semiconductor integrated circuit according to claim 2, wherein the ratio is set to 2: 4: 8. 7. A delay adjustment line laid out near a signal transmission path, a switch capable of selectively supplying a reference voltage level to the delay adjustment line, and an on / off state of the switch A wiring delay adjustment method using a wiring delay adjustment circuit comprising: a first step of detecting a desired wiring delay state by controlling the operation of the switch; and a detection in the first step. Setting a link state of the programmable link based on the result. 8. A logic circuit, a signal transmission path for transmitting a signal to the logic circuit, a delay adjustment line laid out near the signal transmission path, and a reference selectively to the delay adjustment line. A wiring delay adjustment method in a semiconductor integrated circuit, comprising: a semiconductor switch capable of supplying a voltage level; and a programmable link for determining an on / off state of the semiconductor switch. A first step of detecting the wiring delay state, and a second step of setting a link state of the programmable link based on a result of the detection in the first step. 9. A logic circuit, a signal transmission path for transmitting a signal to the logic circuit, a delay adjustment line laid out near the signal transmission path, and a reference selectively to the delay adjustment line. A semiconductor switch capable of supplying a voltage level; a programmable link for determining the on / off state of the semiconductor switch; separately from the programmable link, an operation control signal of the semiconductor switch is taken in from outside the semiconductor integrated circuit. A method of adjusting a wiring delay in a semiconductor integrated circuit, comprising: a first external terminal that enables the first external terminal; and a control circuit that controls the operation of the switch based on an operation control signal that is externally supplied through the first external terminal. A first step of detecting the wiring delay state of the above, and based on the detection result in the first step, Wiring delay adjustment method characterized by comprising a second step of setting the link status of the programmable link. 10. A logic circuit, a signal transmission path for transmitting a signal to the logic circuit, a delay adjustment line laid out near the signal transmission path, and a reference selectively to the delay adjustment line. A semiconductor switch capable of supplying a voltage level; a programmable link for determining the on / off state of the semiconductor switch; and a semiconductor integrated circuit for transmitting a signal capable of controlling the operation of the semiconductor switch regardless of the state of the programmable link. A first external terminal for taking in the signal from outside, a logic inversion circuit for inverting a signal, a ring oscillator forming switch capable of forming a ring oscillator including the logic inversion circuit and the signal transmission path, A second external terminal that allows an external measurement of the oscillation frequency of the ring oscillator provided. A method of adjusting a wiring delay in a conductor integrated circuit, comprising: for each operation control of the switch based on an operation control signal supplied from outside via the first external terminal, changing the oscillation frequency of the ring oscillator to the second external A first step of measuring via a terminal; and a second step of obtaining information for setting a link state of the programmable link based on the measurement result in the first step.
And a third step of setting a link state of the programmable link based on the information obtained in the second step.