JPH10270644A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To ensure the operational speed by a simple method and to increase its accuracy by providing a first and second ring oscillators wherein a plurality of logic gates are connected with metallic distributing wires in the shape of a first wiring pattern which influences a delay characteristic and a second wiring pattern which does not. SOLUTION: The oscillation frequency of a ring oscillator 2 is determined by the delay times of elements constituting a NAND gate 6 and the logic gates of inverters 7-10, and delay times caused by the wiring resistances and wiring capacitance of wiring patterns 11-14 for connecting individual logic gates. And it becomes possible to judge to what extent the wiring capacitance and wiring resistances exert influence on the operational speed, by measuring the oscillation frequency of the ring oscillator 2, after measuring the oscillation frequency of a ring oscillator 3 and judging whether or not the element characteristic is a disired one. Accordingly, it becomes possible to estimate the operational speed of an internal circuit easily, by measuring the oscillation frequencies of the ring oscillators 2, 3 of different wiring pattern shapes, and confirming the element characteristics and the degrees of influence of the wiring capacitance and the wiring resistances on the operational speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a built-in ring oscillator.

[0002]

2. Description of the Related Art The operating speed of semiconductor integrated circuit devices has been increasing year by year, and it is becoming difficult to guarantee the operating speed in the manufacturing process. In particular, ASICs such as gate arrays and cell-based ICs that include user-designed circuits
cation specific integrated circuit), a circuit designed by the user and a verification pattern created by the user are not necessarily suitable for measuring the operation speed, and thus an indirect operation speed guarantee method has been studied.

As a typical indirect operating speed guarantee method, a method of measuring the oscillation frequency of a ring oscillator has been more often used than ever since it is simple. This method uses the correlation between the oscillation frequency of the ring oscillator and the operating speed of the internal circuit.By measuring the oscillation frequency of the ring oscillator, the internal circuit indirectly achieves the desired operating speed. It is determined whether or not. In other words, if the oscillation frequency of the ring oscillator in the semiconductor integrated circuit device manufactured through the manufacturing process is within a predetermined range, it is a proof that the element characteristics of the transistor and the like are manufactured within a desired range. The determination method is such that an internal circuit configured by using similar elements will naturally satisfy a desired operation speed.

As a concrete structure, for example, Japanese Patent Laid-Open No. Hei 3
In the semiconductor integrated circuit device, a ring oscillator as described in page 14, upper right column, line 14 to lower right column, line 11 of JP-A-228353 is arranged in advance and its oscillation frequency is measured. There are things to do.

A conventional example of a semiconductor integrated circuit device including a ring oscillator will be described with reference to the drawings. FIG. 8 is a circuit diagram showing a configuration of a ring oscillator arranged in a conventional semiconductor integrated circuit device.

The circuit shown in FIG. 8 has a control signal input terminal 31.
And output terminal 32, NAND gate 33 and inverter 34
˜37, the oscillation is started when power is supplied and a high level signal is applied to the control signal input terminal 31, and the NAND gate 33 and the inverters 34 to 37 propagate signals to the output terminal 32. An oscillation signal having a frequency equal to the reciprocal of the sum of delay times is obtained. Since the signal propagation delay times of the NAND gate 33 and the inverters 34 to 37 are determined by the characteristics of the transistors that form them, the quality of the transistors can be known by measuring this oscillation frequency, and the internals formed using similar transistors. The operating speed of the circuit can be estimated.

[0007]

In the above-mentioned prior art, the operation speed is guaranteed using a ring oscillator. However, since the oscillation frequency of the ring oscillator is determined only by the element characteristics such as transistors, In the case of a semiconductor integrated circuit device in which the operating speed of the internal circuit is greatly affected by the wiring resistance and the wiring capacitance, there is a problem that the indirect operating speed cannot be guaranteed only by measuring the oscillation frequency of the ring oscillator.

Particularly, in a CMOS type semiconductor integrated circuit device using a fine pattern of 0.5 μm or less, the wiring resistance and the wiring capacitance greatly affect the signal propagation delay time of the logic gate. The operating speed of the internal circuit cannot be determined only by the oscillation frequency of the ring oscillator.

For example, a 2-input NA under standard conditions in a semiconductor integrated circuit device adopting a 0.35 μm CMOS process.
The signal propagation delay time of the ND gate is 150 psec when the wiring length of the metal wiring connected to the output terminal is 0 mm.
In contrast, the average wiring pattern shape has a wiring length of 1
When mm is connected, it becomes 450 psec, and the signal propagation delay time greatly differs depending on whether or not a wiring is connected to the output terminal. If the signal propagation delay time is so large, in a ring oscillator composed of only logic gates with almost no metal wiring connected to the output terminal,
It is difficult to estimate the operating speed of an internal circuit configured by using a lot of metal wiring.

The present invention has been made in view of the problems of the above-mentioned conventional technique, and guarantees the operating speed of a semiconductor integrated circuit device having an internal circuit which uses a lot of metal wiring by a simple method. However, it is an object of the present invention to realize a semiconductor integrated circuit device whose accuracy can be improved.

[0011]

A semiconductor integrated circuit device of the present invention includes a first ring oscillator in which a plurality of logic gates are connected by a metal wiring having a first wiring pattern shape which affects delay characteristics, Different from the first wiring pattern shape, between the plurality of logic gates, the second wiring pattern does not affect the delay characteristic.
And a second ring oscillator connected by a metal wiring having the wiring pattern shape described above.

The difference between the first wiring pattern shape and the second wiring pattern shape is the wiring length, the wiring width, the distance between adjacent wirings, the crossing area with the upper and lower wiring layers, and the like. Any of them may be selected or may be combined.

In any of the above cases, a multiplexer circuit may be provided which uses the output signals of the first and second ring oscillators as input signals.

[0014] Further, it is also possible to have a multiplexer circuit using the output signals of the first and second ring oscillators as an input signal, and a frequency dividing circuit for dividing the output signal of the multiplexer circuit.

[0015]

In the embodiment constructed as described above,
Since a ring oscillator whose wiring pattern shape affects the delay characteristics and a ring oscillator whose wiring pattern shape does not affect the delay characteristics are provided, by measuring the oscillation frequency of each ring oscillator, the oscillation frequency of the device characteristics can be reduced. The fluctuation and the fluctuation of the oscillation frequency due to the wiring capacitance and the wiring resistance can be detected together. Therefore, the operating speed of the semiconductor integrated circuit device having an internal circuit that uses a lot of metal wiring can be guaranteed by a simple method.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic plan view showing a configuration of a semiconductor integrated circuit chip as one embodiment of the present invention, and FIG.
FIG. 2 is a circuit diagram showing a configuration of a ring oscillator 2 in the middle.

The semiconductor integrated circuit chip 1 shown in FIG. 1 incorporates ring oscillators 2 and 3 having different wiring pattern shapes between logic gates. Although the configuration of the ring oscillator 2 is shown in FIG. 2 as described above, the circuit configuration of the ring oscillator 3 which differs from the ring oscillator 2 in the wiring pattern between logic gates is the same as that of the conventional example shown in FIG. Is omitted.

The ring oscillator 2 has a control signal input terminal 4, an output terminal 5, and an NA provided in series between the terminals.
The ND gate 6 and the inverters 7 to 10, and wiring patterns 11 to 14 connecting the respective logic gates. NAND gate 6 receives the output of inverter 10 and the input signal to control signal input terminal 4, and the output of inverter 10 fed back to NAND gate 6 is output to output terminal 5.

Next, the operation of the embodiment of the present invention will be described with reference to FIGS. 1, 2 and 8. The oscillation frequency of the ring oscillator 3 having the circuit configuration shown in FIG. 8 has a short wiring length for connecting each logic gate and hardly affects the delay time.
It is determined only by the delay time of the elements constituting the 37 logic gates.

On the other hand, the oscillation frequency of the ring oscillator 2 having the circuit structure shown in FIG. 2 is the delay time of the elements forming the logic gates of the NAND gate 6 and the inverters 7 to 10, and the wiring pattern 11 connecting the respective logic gates. ~ 14
It is determined by the delay time determined by the wiring capacitance and the wiring resistance. If the oscillation frequency of the ring oscillator 2 is measured after measuring the oscillation frequency of the ring oscillator 3 and determining whether the element characteristics show the desired characteristics,
It is possible to determine how much the wiring capacitance and wiring resistance affect the operating speed.

Therefore, by measuring the oscillation frequencies of the ring oscillators 2 and 3 having different wiring pattern shapes, it is possible to confirm the degree of influence of the element characteristics, the wiring capacitance, and the wiring resistance on the operating speed, and as a result. The operation speed of the internal circuit can be easily estimated.

Specifically, it is previously known how much the oscillation frequency of the ring oscillator 3 changes depending on the element characteristics, and how much the oscillation frequency of the ring oscillator 2 changes due to the wiring capacitance and the wiring resistance. From these data, and the oscillation frequency measurement data of the ring oscillators 2 and 3 in the semiconductor integrated circuit chip 1 that have been completed through the manufacturing process, the performance of the chip's element characteristics, wiring capacitance, and wiring resistance are estimated. The operating speed of the internal circuit is estimated.

[0024]

Embodiments of the present invention will now be described in detail with reference to the drawings.

The semiconductor integrated circuit chip 1 shown in FIG.
It was fabricated as a CMOS type semiconductor integrated circuit chip using a 0.35 μm manufacturing process. For the ring oscillators 2 and 3 incorporated in the semiconductor integrated circuit chip 1 and having different wiring pattern shapes between the logic gates, the channel length of the MOS transistor forming each logic gate is set to 0.3.
It was manufactured with 5 μm and a channel width of 9 μm.

FIG. 3 is a top view showing the shapes of the wiring patterns 11 to 14 in FIG.

The signal transmission wiring pattern 17 shown in FIG.
Wiring pattern input terminal 15 and wiring pattern output terminal 16
Wiring width 20 is formed between them, and wiring space is 2 on both sides.
Adjacent wiring patterns 18 and 19 connected to the ground terminals 23 and 24 with the reference numerals 1 and 22 are provided.

Here, the wiring length of the signal transmission wiring pattern 17 is 1 mm, the wiring width 20 is 0.8 μm, and the wiring intervals 21 and 22 between the adjacent wiring patterns 18 and 19 are 0.8 μm.

On the other hand, in the ring oscillator 3, the length of the wiring connecting the logic gates is almost 0 mm, and the influence of the wiring on the delay time is at a level that can be ignored. For this reason, the circuit pattern of FIG. 8 does not intentionally represent a wiring pattern.

Next, the operation of this embodiment will be described with reference to FIGS. 1 to 3 and 8.

In the CMOS type semiconductor integrated circuit device 1 according to the present embodiment, when manufactured through a normal manufacturing process, the oscillation frequency f1 of the ring oscillator 3 is increased under the conditions of a power supply voltage of 3.3 V and an ambient temperature of 25 ° C. Data measured in advance indicates a frequency within the range of 1500 MHz ± 30%.
On the other hand, the oscillation frequency f2 of the ring oscillator 2 is f1 / 3
Indicates an oscillation frequency within the range of ± 15%.

Further, a CMOS type semiconductor integrated circuit device 1
It has also been confirmed that if the oscillation frequency of the ring oscillators 2 and 3 is within the above range, the operating speed of the internal circuit satisfies the desired standard.

Here, it is assumed that the oscillation frequency f1 of the ring oscillator 3 in the CMOS semiconductor integrated circuit device 1 manufactured with a certain manufacturing variation is 1200 MHz and the oscillation frequency of the ring oscillator 2 is 320 MHz. The oscillation frequency of the ring oscillator 3 is 1500
Since it is within the range of MHz ± 30%, it can be determined that there is no problem in the element characteristics of the MOS transistor. On the other hand, the oscillation frequency f2 of the ring oscillator 2 is 340 of f1 / 3 ± 15%.
It exceeds the range of ４460 MHz. Therefore, one or both of the wiring capacitance and the wiring resistance can be estimated to be abnormal, and it can be determined that the operation speed of the internal circuit cannot be guaranteed.

As abnormalities in the wiring capacitance and the wiring resistance, abnormalities in the wiring material, the wiring film pressure, the wiring width, and the wiring interval can be considered.
In the present embodiment, these abnormalities can be detected in the form of the oscillation frequency of the ring oscillator. In this example, the power supply voltage is 3.3 as a condition for measuring the oscillation frequency.
V and ambient temperature were limited to the oscillation frequency under the condition of 25 ° C.

As described above, only by measuring the oscillation frequencies of two types of ring oscillators having different wiring pattern shapes,
It has a feature that the operating speed of the internal circuit can be guaranteed very easily.

Next, a second embodiment of the present invention will be described.

In the first embodiment described above, the wiring pattern of the ring oscillator 2 has the shape shown in FIG. 3, but in the present embodiment, the wiring pattern shown in FIG. 4 is employed. .

In the wiring pattern shown in FIG. 4, the wiring pattern input terminal 25 and the wiring pattern output terminal 26 are connected by the signal transmission wiring pattern 27. Since the signal transmission wiring pattern 27 intersects with the plurality of upper layer wiring patterns 28, an abnormality in wiring capacitance due to an abnormal crossing area with the upper layer wiring pattern 28 and an interlayer insulating film pressure is called an abnormal oscillation frequency of the ring oscillator 2. It can be detected in the form.

Also in the case of the present embodiment, in order to guarantee the operating speed of the internal circuit, the oscillation frequencies f1 and f2 of the ring oscillators 2 and 3 within the normal manufacturing variation range are within what range. In that case, it is necessary to confirm whether the operating speed of the internal circuit satisfies the standard.

In each of the embodiments described above, the case where the number of ring oscillators incorporated is two, which is the smallest, is shown. However, even if two or more ring oscillators having different wiring pattern shapes between logic gates are incorporated. As a matter of course, the same effect as that of each of the embodiments described above can be obtained.

Further, when the oscillation frequency of the ring oscillator is very high and it is difficult to measure the oscillation frequency, the same effect can be obtained by using a technique of providing a frequency dividing circuit and dividing the frequency to a frequency that is easy to measure.

FIGS. 5A and 5B are diagrams showing the configuration of an embodiment in which the above-described frequency dividing circuit is provided. FIG. 5A is a top view and FIG. 5B is a circuit diagram.

As shown in FIG. 5A, the output of each ring oscillator is input to the semiconductor integrated circuit chip 101 of this embodiment together with the ring oscillators 2 and 3 similar to the embodiment shown in FIG. A multiplexer circuit 102 for selecting and outputting any one of the multiplexer circuits 102
A frequency dividing circuit 103 for dividing the output is provided.

As shown in FIG. 5B, the multiplexer circuit 102 comprises a control signal input terminal 105 and a multiplexer 106, and the frequency dividing circuit 103 includes a plurality of flip-flops 103 ₁ , 103 ₂ , ..., 103. It is composed of _n and an output terminal 104. Multiplexer 106
Are output terminals 5 of the ring oscillators 2 and 3,
Upon receiving the output from 32 (see FIG. 2 and FIG. 8), one of them is sent to the frequency dividing circuit 103 according to the control signal input to the control signal input terminal 105. In the frequency dividing circuit 103,
The input signal is divided by a ratio determined by the number of flip-flops 103 _{1 to} 103 _n and output to the output terminal 104.

In the present embodiment configured as described above, it is possible to measure a ring oscillator composed of a small number of gate elements and having a high oscillation frequency. Therefore, a ring oscillator composed of a small number of gate elements is used. Can be used. When a plurality of ring oscillators are provided, an area corresponding to the number is required, but since only one multiplexer circuit and frequency dividing circuit for selecting and dividing the output of the ring oscillator are required, a semiconductor integrated circuit chip is provided. The area of the ring oscillator is dominant in the area above. In the present embodiment, since the ring oscillator can be made smaller, it is suitable for downsizing the semiconductor integrated circuit chip.

Regarding the reduction of the circuit area, the ring oscillators 2 and 3 may use a common control signal input terminal 201 as shown in FIG.

Further, as shown in FIG. 7, the frequency dividing circuit 103 may be omitted from the embodiment shown in FIG. In this case, since the frequency division is not performed, each of the ring oscillators 2, 3
Is output to the output terminal 301 as it is, but the area of the semiconductor integrated circuit chip is the smallest.

Further, in each of the embodiments, the CMOS type semiconductor integrated circuit device which is relatively susceptible to the wiring capacitance and the wiring resistance has been described, but the same effect can be obtained even if the elements used such as bipolar, BiCMOS and compound semiconductor are changed. can get.

[0049]

Since the present invention is constructed as described above, it has the following effects.

A ring oscillator in which the wiring pattern shape affects the delay characteristics and a ring oscillator in which the wiring pattern shape does not affect the delay characteristics are provided. By measuring the oscillation frequency thereof, fluctuations in the oscillation frequency due to element characteristics, Since the fluctuation of the oscillation frequency due to the wiring capacitance and the wiring resistance can be detected together, the operation speed of the semiconductor integrated circuit device having the internal circuit that heavily uses the metal wiring can be guaranteed by a very simple method. There is.

[Brief description of the drawings]

FIG. 1 is a schematic plan view showing a configuration of a semiconductor integrated circuit chip according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a ring oscillator 2 in FIG.

FIG. 3 is a plan view showing a wiring pattern shape of the ring oscillator 2 shown in the circuit diagram of FIG.

FIG. 4 is a plan view showing a wiring pattern shape of a ring oscillator as another embodiment of the invention.

FIG. 5 is a diagram showing a configuration of another embodiment of the present invention;
(A) is a top view and (b) is a circuit diagram.

FIG. 6 is a diagram showing a configuration of another embodiment of the present invention.

FIG. 7 is a diagram showing the configuration of another embodiment of the present invention.

FIG. 8 is a circuit diagram of a ring oscillator showing a conventional example and an embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit chip 2, 3 Ring oscillator 4, 31 Control signal input terminal 5, 32 Output terminal 6, 33 NAND gate 7-10, 34-37 Inverter 11-14 Wiring pattern 15, 25 Wiring pattern input terminal 16, 26 Wiring pattern output terminal 17,27 Signal transmission wiring pattern 18,19 Adjacent wiring pattern 20 Wiring width 21,22 Wiring interval 23,24,29 Ground terminal 28 Upper layer wiring pattern

Claims (7)

[Claims] A first ring oscillator connected between a plurality of logic gates by a metal wiring having a first wiring pattern shape affecting a delay characteristic; and a first wiring pattern shape between the plurality of logic gates. And a second ring oscillator connected with a metal wiring having a second wiring pattern shape that does not affect the delay characteristic. 2. The semiconductor integrated circuit device according to claim 1, wherein the difference between the first wiring pattern shape and the second wiring pattern shape is a wiring length. 3. The semiconductor integrated circuit device according to claim 1, wherein the difference between the first wiring pattern shape and the second wiring pattern shape is a wiring width. . 4. The semiconductor integrated circuit device according to claim 1, wherein a difference between the first wiring pattern shape and the second wiring pattern shape is a distance between adjacent wirings. A semiconductor integrated circuit device. 5. The semiconductor integrated circuit device according to claim 1, wherein a difference between the first wiring pattern shape and the second wiring pattern shape is an intersecting area with the upper and lower wiring layers. A semiconductor integrated circuit device characterized by the above-mentioned. 6. The semiconductor integrated circuit device according to claim 1, further comprising a multiplexer circuit that uses output signals of the first and second ring oscillators as input signals. Integrated circuit device. 7. The semiconductor integrated circuit device according to claim 1, wherein the multiplexer circuit receives an output signal of the first and second ring oscillators as an input signal, and an output signal of the multiplexer circuit. And a frequency dividing circuit for dividing frequency.