JPH1011386A - Memory data transfer device and transfer method thereof - Google Patents

Abstract

(57) [Summary] A method called a direct memory access transfer method in which data is transferred between a memory 2 and a memory 3 by a direct memory access controller. ,
Implement data transfer at discontinuous addresses. A gate circuit (9) is provided between an address bus (8) and a data bus (7) and a direct memory access controller (4).
Between the memory and the memory 3, an address from the direct memory access controller 4 can be fetched, data corresponding to the address can be connected as an address of the memory 3, and a conversion memory in which data is connected as data from the central processing unit 1. Add 5 to control the gate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to an apparatus employing a system called a direct memory access transfer system.

[0002]

2. Description of the Related Art As shown in FIG. 2, a conventional system using a system called a direct memory access transfer system has a central processing unit 1 which executes normal data transfer and processing, and saves data. Memory 2 and memory 3 for performing a data transfer between the memory 2 and the memory 3, a direct memory access controller 4 for executing data transfer instead of the central processing unit 1, and a data bus as a path of data 7, an address bus 8 for indicating a destination (address) of data on the data bus 7
It was a device composed of:

In this configuration, when data is transferred between the memory 2 and the memory 3, as shown in FIG. 3, the transfer start address i of the memory 2, the transfer start address j of the memory 3, and the transfer data number The direct memory access controller 4 that executes data transfer between the memory 2 and the memory 3 only with the information of n can perform only data transfer of continuous addresses.

Therefore, when data transfer at discontinuous addresses is performed, the central processing unit 1 itself must execute data transfer without using the direct memory access controller 4, and the central processing unit 1 However, the advantage of the direct memory access controller 4 in reducing the burden on the user cannot be utilized.

[0005]

As described above, in the conventional method called the direct memory access transfer method, due to the restriction of the direct memory access controller 4,
Only data transfer of continuous addresses could be performed.

Therefore, the present invention enables the direct memory access controller 4 to execute data transfer at discontinuous addresses without the intervention of the central processing unit 1.

[0007]

As shown in FIG. 1, a gate circuit 9 and a control circuit 6 for controlling ON / OFF of the gate circuit 9 are provided between an address bus 8 and a data bus 7 in the configuration of FIG. An address from the direct memory access controller 4 is fetched as an address between the direct memory access controller 4 and the memory 3, data corresponding to the address can be connected as an address of the memory 3, and data is transmitted from the central processing unit 1. Is provided with a conversion memory 5 which is connected as data.

When the address of the memory 3 corresponding to the address of the memory 2 is stored in the conversion memory 5 as data by the central processing unit 1 in advance, the data of the conversion memory 5 becomes the address of the memory 3. Thus, data transfer at discontinuous addresses is possible.

[0009]

FIG. 3 shows an embodiment of the present invention.

The apparatus shown in this embodiment comprises a central processing unit 1 which normally executes data transfer and processing, a memory 2 and a memory 3 for storing data, and a memory 3 between the memory 2 and the memory 3. When performing data transfer, the central processing unit 1
, The addresses from the direct memory access controller 4 and the direct memory access controller 4 for executing data transfer are taken in as addresses.
Data corresponding to the address can be connected as an address of the memory 3, and the conversion memory 5 from which data is connected as data from the central processing unit 1, an address bus 8 and a data bus 7 between the above-described devices. Gate 19a, gate 29b, gate 3 for switching connection
9c, its gates 1 to 3 are constituted by a control circuit 6 for controlling the on / off of the gates 9a to 9c. The connection of addresses and data between the devices is provided by an address bus 8 as an address terminal of the central processing unit 1, Address terminal of memory 2, address terminal of memory 3, gate 19a, gate 29
b, the control circuit 6 is connected, and the data bus 7 is connected to the data terminal of the central processing unit 1, the data terminal of the memory 2, the data terminal of the memory 3, and the gate 39c. The other end of the gate 19a is connected to the address terminal of the direct memory access controller 4 and the address terminal of the conversion memory, and the other end of the gate 29b and the other end of the gate 39c are connected to the data terminal of the conversion memory 5. A control line for switching on / off of the gates 1 to 39a to c from 6 is connected to the gates 1 to 39a to c.

In this apparatus, the control circuit 6 as shown in Table 1 shows the on / off logic of the gates 1 to 39a to c for switching the connection of the address and data between the devices.
The central processing unit 1 previously writes a relative address with respect to the memory 2 into the conversion memory 5 as address data of the memory 3 so that the direct memory access controller 4
Is output to the memory 3 as an address of the conversion memory 5 and data in the conversion memory 5 corresponding to the address is connected as an address of the memory 3. The transferred data can be transferred to the memory 3 as a discontinuous address without data and address collision.

[0012]

[Table 1]

The lower part of FIG. 3 shows the contents of each memory when rearrangement (4 words) is performed according to this configuration.

[0014]

According to the present invention, by providing the conversion memory 5 and the gate circuit 9, not only conventional data transfer of a continuous address block but also data transfer of a discontinuous address can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic example of the present invention.

FIG. 2 is a block diagram of a conventional technique.

FIG. 3 is a block diagram showing one embodiment of the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Central processing unit, 2,3 ... Memory, 4 ... Direct memory access controller, 5 ... Conversion memory, 6 ... Control circuit, 7 ... Data bus, 8 ... Address bus, 9 ... Gate circuit.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiharu Kataoka 3-2-1 Sachimachi, Hitachi City, Ibaraki Prefecture Within Hitachi Engineering Co., Ltd. (72) Inventor Takeshi Sugiyama 3-2-2 Sachimachi, Hitachi City, Ibaraki Prefecture 1 Hitachi Engineering Co., Ltd. (72) Inventor Tadashi Osone 5-2-1 Omika-cho, Hitachi City, Ibaraki Pref. Hitachi, Ltd. Omika Plant

Claims (3)

[Claims] 1. A central processing unit for executing transfer and processing of memory data, a first memory and a second memory for storing data, and a direct memory for executing data transfer between the first memory and the second memory. A memory access controller, a central processing unit, the first memory, the second memory,
A memory data transfer device comprising a data bus as a data path between the direct memory access controllers and an address bus indicating a destination of data, wherein the data bus and the address bus, the first memory, and the second memory A gate circuit and a circuit for controlling the on / off of the gate circuit are provided between the direct memory access controller, and a conversion memory is provided between the direct memory access controller and the second memory. Memory data transfer device. 2. The conversion memory according to claim 1, wherein a continuous address of the second memory corresponding to the address of the first memory from the central processing unit is converted in an arbitrary order and stored in the conversion memory in advance. A memory data transfer method using the data of (1) as an address of the second memory. 3. The gate circuit according to claim 1, wherein, when data is transferred between said first memory and said second memory, said conversion memory is specified instead of directly specifying a transfer address of said second memory. Method of transferring memory data that controls switching of