JPH10126401A - Clock recovery circuit - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a clock recovery circuit which can return to the frequency correction of a recovered clock at a high speed with less power consumption without acquiring synchronization again when power is turned on, when power is momentarily cut off, or when noise or fading occurs. provide. A digital PLL with a learning correction function for performing frequency correction for maintaining synchronization with a base station by a received signal.
17, a power-on detection circuit 12 for detecting power-on,
An instantaneous interruption detection circuit 13 for detecting an instantaneous power interruption, a frequency counter for detecting a frequency error of a received signal due to noise and fading, a memory 19 for holding a convergence value of learning data used for frequency correction of a reproduced clock, and a learning data The control circuit 18 controls the convergence value of the learning data stored in the memory when the power is turned on, when the power is interrupted during a call, or when noise or fading occurs. Set to PLL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit for a TDMA type mobile station typified by a PDC (Personal Digital Cellular) type digital mobile phone, and more particularly to learning data at the time of convergence of frequency correction. Is stored in the memory, and when the learning data for correcting the frequency of the reproduction clock due to noise or fading at the time of turning on the power, during a call, or noise or fading to the received signal (IF) is largely incorrect, the data is stored in the memory. The present invention relates to a circuit for correcting the frequency of a reproduced clock at a higher speed than before using the learning data.

[0002]

2. Description of the Related Art As a conventional clock recovery circuit, one described in Japanese Patent Application Laid-Open No. 5-41703 is known.
This is because the received signal (I
F: fixed frequency division is performed because no intermediate frequency signal is input, and a high-precision TCXO (temperature-compensated crystal oscillator) is used as a source oscillation to maintain a phase with a transmission clock from a base station. Needed.

A clock recovery circuit with a learning correction function capable of correcting a recovered clock as shown in FIGS. 6 and 7 has been filed as a prior application. FIG. 6 is a block diagram showing a configuration of a conventional clock recovery circuit with a learning correction function capable of correcting a recovered clock in a non-receiving section. FIG. 7 is a configuration of a digital PLL (phase locked loop) with a learning correction function shown in FIG. It is a block diagram which shows in detail.

First, a configuration of a conventional clock recovery circuit with a learning correction function capable of correcting a recovered clock will be described with reference to FIG. 6, reference numeral 11 denotes a temperature-compensated crystal oscillator (hereinafter referred to as TCXO), and reference numeral 14 denotes a received signal (IF).
A demodulation unit 17 for generating demodulated data and a clock reference 21 from the output of the TCXO 11 during a reception period, generating a reproduced clock (bit clock, symbol clock) synchronized with the clock reference 21 during the reception period, and generating an error of the TCXO 11 during a non-reception period. This is a digital PLL with a learning correction function for generating and holding a learning value for correcting a frequency shift of a reproduced clock due to the above.

Next, the operation of the conventional clock recovery circuit with a learning correction function capable of correcting the recovered clock will be described with reference to FIG. First, the demodulator 14 receives the received signal (I
A clock reference 21 for synchronizing with the base station clock is generated from F). During the reception period, the digital PLL 17 with the learning correction function divides the TCXO 11 and generates a reproduced clock synchronized with the clock reference 21 to perform phase tracking with the base station transmission clock, and at the same time, detects the frequency error of the TCXO 11. . During the non-reception section, the frequency of the reproduction clock is corrected using the learning data (corresponding to the TCXO frequency error) detected during the reception section so that a phase shift from the base station transmission clock does not occur.

Next, a digital PLL with a learning correction function will be described in detail with reference to FIG. 7 to further understand the clock recovery circuit. When the phase of the symbol clock is ahead of the clock of the base station during the reception section, the digital PLL 40 of the digital PLL 17 with the learning correction function detects the edge of the clock reference by the edge detection circuit 41 (enable signal 4).
9) is output in the L level section of the symbol clock output by the digital PLL 40 itself, so that the up / down counter 42 counts down and the normal TCXO 11
Is divided by N + 1 for one cycle by the division ratio variable signal (N + 1 division) 50, and the phase of the symbol clock is delayed by that amount.

Further, when the phase of the symbol clock is behind the clock of the base station during the reception section,
The edge detection result (enable signal 49) of the clock reference by the edge detection circuit 41 is a digital PLL.
Since the signal is output in the H level section of the symbol clock output by itself, the up / down counter 42 counts up and the variable frequency divider 43, which performs N frequency division of the normal TCXO 11, transmits the frequency division ratio variable signal (N− The frequency is divided by N-1 for one cycle by (divide by 1) 51, and the phase of the symbol clock is advanced accordingly.

A detection circuit 44 generates an enable signal 52 and an up / down control signal 53 from a frequency division ratio variable signal (N + 1 frequency division) 50 or a frequency division ratio variable signal (N-1 frequency division) 51 from the digital PLL 40. Then, the load value N up / down counter A45 is controlled as described below.

When the frequency of the TCXO 11 shifts to the lower side during the reception section, the detection circuit 44
From 0, a frequency division ratio variable signal (N-1) 51 is input, and an enable signal 52 and an up / down control signal 53 (for example,
"H" (hereinafter the same) is output to the load value N up / down counter A45. Then, the load value N up / down counter A45 counts up. As a result, when the overflow signal 54 becomes active, the up / down control signal 55 is set to “H”.

When the frequency of the TCXO 11 shifts to a higher frequency, the detection circuit 44 receives the frequency division ratio variable signal (N + 1) 50 from the digital PLL 40, and outputs an enable signal 52 and an up / down control signal 53 (for example,
"L" (hereinafter the equivalent) is output to the load value N up / down counter A45. Then, the load value N up / down counter A45 counts down. As a result, when the overflow signal 54 becomes active, the up / down control signal 55 is set to "L".

When the up / down counter B46 inputs the up / down control signal 55 (L) on the up side (when the frequency of the TCXO 11 shifts to the higher side) together with the overflow signal 54 from the load value N up / down counter A45. +1 is counted up. Further, the up / down counter B46 is on the down side together with the overflow signal 54 from the load value N up / down counter A45 (when the frequency of the TCXO 11 is shifted to a lower side).
When the up-down control signal 55 (H) is input,
It is counted down by one.

The result of +1 count-up or -1 count-down is accumulated in the up-down counter B46 as frequency error data, and converges to an optimum value for correcting the frequency error of the TCXO 11 while repeating reception. Then, it is held in the up / down counter B46 as a learning value. During the non-reception section of the intermittent reception, the learning value accumulated in the up / down counter B46 is used as a correction value of the frequency error of the TCXO11.

The integrator 47 has an up / down counter B4
6 is integrated in units of symbols, and when the frequency of the TCXO 11 is shifted to a lower side, the frequency dividing ratio variable signal (N−1) is supplied to the variable frequency divider 43 that divides the TCXO 11 by N.
Divide) 57 is output, and the phase of the symbol clock is advanced accordingly. When the frequency of the TCXO 11 is shifted to a higher frequency, the frequency dividing ratio variable signal (N + 1 frequency division) 56 is output to the variable frequency divider 43 which divides the TCXO 11 by N, and the symbol clock of the symbol clock is correspondingly outputted. Delay the phase. Also, a digital PL with a learning correction function is set according to the time constant 48.
The correction frequency of L can be made variable.

[0014]

However, in the above-mentioned conventional clock recovery circuit with a learning correction function, when an instantaneous power interruption occurs during power-on or during a telephone call, an up-down clock holding the learning data is required. The center B is initialized, and the learning data is lost. In this case, there is a problem that the learning must be reworked from the beginning, and the learning data of the digital PLL with the learning correction function cannot be shifted to the intermittent reception until the convergence to some extent, so that the power consumption in the continuous reception increases.

Further, even if the received signal is deteriorated due to the influence of noise and fading added to the received signal (IF), the learning data is continuously updated by detecting the frequency error of the TCXO 11 during the receiving section, so that an error may occur. The value will be updated as learning data. In the extreme case, the clock synchronization is lost, and the operation shifts to the continuous reception operation to acquire the synchronization again. However, as described above, there is a possibility that the continuous reception section may be long, so that there is a problem that power consumption increases. .

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and the learning data for frequency correction of a reproduced clock is largely erroneous due to power-on, power-off, or noise or fading of a received signal. In such a case, the learning data held in the memory is set in the digital PLL with the learning correction function without the need to shift to the continuous reception operation for synchronization acquisition again, so that the power consumption is low and the reproduction clock of the reproduction clock is reduced. An object of the present invention is to provide a clock recovery circuit that can perform frequency correction at high speed.

[0017]

SUMMARY OF THE INVENTION A clock recovery circuit according to the present invention has a learning correction function for performing phase tracking and frequency correction to maintain synchronization with a base station by a clock reference generated from a received signal (IF). Digital P
LL, a power-on detection circuit for detecting power-on, an instantaneous power-off detection circuit for detecting an instantaneous power-off, a frequency counter for detecting a frequency error of a received signal (IF) due to noise and fading, and a frequency correction of a reproduced clock. A memory that holds the convergence value of the learning data used for communication, and a control circuit that controls the learning data. The effects of noise, fading, etc., when the power is turned on, when the power is interrupted during a call, or when the received signal (IF) is received Therefore, when the received signal is degraded and the learning data becomes erroneous, the convergence value of the learning data stored in the memory is set in the digital PLL with the learning correction function.

According to the present invention, when power-on or power-off, or when the learning data for frequency correction of the reproduced clock is largely incorrect due to noise or fading of the received signal, continuous data for synchronization acquisition is again obtained. Low power consumption and high-speed reproduction clock frequency correction by setting the optimal convergence value of the learning data stored in the memory to the digital PLL with the learning correction function without having to shift to the reception operation. Thus, a clock recovery circuit that can be used is obtained.

[0019]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention performs a phase tracking and a frequency correction of a reproduced clock so as to maintain synchronization with a base station by a clock reference generated from a received signal. Digital PLL with a learning correction function to hold the convergence value of the learning data, and power ON to detect power-on and output a power-ON detection signal
Detection means, instantaneous interruption detection means for detecting an instantaneous power interruption and outputting an instantaneous interruption return signal, demodulation means for generating demodulated data and a clock reference from a received signal, and synchronous word detection for detecting a synchronous word from the demodulated data Means, timing means for performing time management of the mobile station based on the synchronization pulse, storage means for receiving and holding a convergence value of learning data used for frequency correction of the reproduced clock from the digital PLL with the learning correction function, and power ON. Control means for receiving the detection signal or the instantaneous interruption return signal and controlling the learning data to be set in the digital PLL with the learning correction function from the storage means. Even if an instantaneous interruption occurs, the learning data at the time of convergence stored in the memory is reproduced by setting it in the digital PLL with learning correction function. It has the effect that the lock of the frequency correction can be performed at a high speed.

The invention according to claim 2 of the present invention provides:
A digital PLL with a learning correction function for performing phase tracking and frequency correction of a reproduced clock so as to maintain synchronization with a base station by using a clock reference generated from a received signal and holding a convergence value of learning data for the frequency correction;
Frequency counting means for detecting a frequency error of a received signal due to fading and outputting a frequency NG signal; demodulating means for generating demodulated data and a clock reference from the received signal; and synchronous word detecting means for detecting a synchronous word from the demodulated data. A timing means for performing time management of the mobile station based on the synchronization pulse; a storage means for receiving and holding a convergence value of learning data used for frequency correction of the reproduced clock from the digital PLL with the learning correction function;
A control means for receiving a signal and controlling the learning data from the storage means to be set in the digital PLL with the learning correction function.
Even if the received signal deteriorates due to the influence of noise and fading on F), the frequency of the reproduction clock can be corrected at high speed by setting the convergence learning data stored in the memory to the digital PLL with the learning correction function. Has the effect of being able to.

Hereinafter, based on the attached drawings and FIGS. 1 to 5,
An embodiment of the present invention will be described in detail. FIG. 1 is a block diagram illustrating a configuration of a clock recovery circuit according to a first embodiment of the present invention, FIG. 2 is a block diagram illustrating a configuration of a clock recovery circuit according to a second embodiment of the present invention, and FIG. 1 shows a timing when a power-on detection signal is generated from a power-on detection circuit in FIG. 1, FIG. 4 shows a timing when an instantaneous power-off recovery signal is generated from the instantaneous interruption detection circuit in FIG. 1, and FIG. FIG. 4 is a diagram showing timing when a frequency NG signal is generated from the frequency counter in FIG.

(Embodiment 1) First, referring to FIG.
The configuration of the clock recovery circuit according to the first embodiment of the present invention will be described. In FIG. 1, reference numeral 11 denotes a temperature-compensated crystal oscillator (hereinafter referred to as TCXO), and reference numeral 12 denotes a power-on detection circuit for detecting power-on. Reference numeral 13 denotes an instantaneous interruption detection circuit that detects an instantaneous interruption of power during a call, 14 denotes a demodulation unit that generates demodulated data 23 and a clock reference 21 from a received signal (IF), and 15 denotes demodulated data 23 generated by the demodulation unit 14.
A synchronization word detection circuit 16 detects a synchronization word and outputs a synchronization pulse, and 16 is a timer for managing the time of the mobile station based on the synchronization pulse output from the synchronization word detection circuit 15. The power ON detection circuit, instantaneous interruption detection circuit, demodulation unit,
The synchronization word detection circuit and the timer correspond to power ON detection means, instantaneous interruption detection means, demodulation means, synchronization word detection means and timing means, respectively.

Reference numeral 17 generates a reproduction clock (bit clock, symbol clock) synchronized with the clock reference 21 from the output of the TCXO 11 during a reception period, and corrects a frequency deviation of the reproduction clock due to a frequency error of the TCXO 11 during a non-reception period. Digital P with learning correction function
Reference numerals LL and 19 denote memories for holding a convergence value of learning data used for correcting the frequency of the reproduced clock. Reference numeral 18 denotes a digital PLL 17 with a learning correction function based on signals from the power ON detection circuit 12, the instantaneous interruption detection circuit 13, and the timer 16. This is a control circuit for controlling learning data with the memory 19. Note that the memory and the control circuit correspond to a storage unit and a control unit, respectively.

Next, before describing the operation of the clock recovery circuit in the present embodiment, the digital PLL 17 with a learning correction function will be described in detail. First, referring to FIG. 7, a digital PLL with a learning correction function shown in FIG.
17 will be described.

In FIG. 7, reference numeral 40 denotes a digital PLL, which is a variable frequency divider 43 for dividing the TCXO 11 by N to generate a symbol clock and a bit clock, and an edge of a clock reference generated from a received signal (IF). And a variable frequency divider that counts up or down by using the enable signal 49 from the edge detecting circuit 41 or the symbol clock from the variable frequency divider 43. Variable frequency division ratio signal (N + 1 frequency division) for 43
An up / down counter 42 that outputs 0 or a variable frequency division ratio signal (N-1 frequency division) 51 is provided.

A detection circuit 44 outputs an enable signal 52 and an up / down control signal (L or H) 53 from the frequency division ratio variable signals 50 and 51 from the digital PLL 40, and a reference numeral 45 denotes an enable signal 52 and an up / down control signal. An overflow signal 54 for controlling the frequency division ratio of the variable frequency divider 43 and an up / down counter A, 46 for outputting an up / down control signal (L or H) 55 under control of the overflow signal 54 and the up / down control Up / down counters B and 47 for accumulating the signal 55 as frequency error data accumulate the output values from the up / down counter B and control the frequency division ratio of the variable frequency divider 43 (N + 1 frequency division). 56 is an integrator that outputs a frequency division ratio signal 56 and a frequency division ratio variable signal (N−1 frequency division) 57.

Next, the operation of the digital PLL 17 with the learning correction function will be described in detail with reference to FIG. First, in the digital PLL 40 of the digital PLL 17 with the learning correction function, when the phase of the symbol clock is ahead of the clock of the base station during the reception interval, the edge detection result of the clock reference by the edge detection circuit 41 (enable signal 49) Is a digital PLL 40
Since the signal is output during the L level section of the symbol clock output by itself, the up / down counter 42 counts down, and the variable frequency divider 43 that normally divides the TCXO 11 by N divides the frequency by the frequency division ratio variable signal (N + 1 The frequency of the symbol clock is delayed by N + 1 for one period by the (cycle) 50, and the phase of the symbol clock is delayed by that amount.

If the phase of the symbol clock is behind the clock of the base station during the reception section,
The edge detection result (enable signal 49) of the clock reference by the edge detection circuit 41 is a digital PLL.
Since the signal is output in the H level section of the symbol clock output by itself, the up / down counter 42 counts up and the variable frequency divider 43, which performs N frequency division of the normal TCXO 11, transmits the frequency division ratio variable signal (N− The frequency is divided by N-1 for one cycle by (divide by 1) 51, and the phase of the symbol clock is advanced accordingly. The detection circuit 44 is a digital PLL.
The frequency division ratio variable signal (50: N + 1 frequency division, 51:
An enable signal 52 and an up / down control signal 53 are generated from the (N-1 frequency division), and the load value N up / down counter A45 is controlled as described below.

When the frequency of the TCXO 11 shifts to the lower side during the reception section, the detection circuit 44
From 0, a frequency division ratio variable signal (N-1) 51 is input, and an enable signal 52 and an up / down control signal 53 (for example,
"H" (hereinafter the same) is output to the load value N up / down counter A45. Then, the load value N up / down counter A45 counts up. As a result, when the overflow signal 54 becomes active, the up / down control signal 55 is set to “H”.

When the frequency of the TCXO 11 is shifted to a higher frequency, the detection circuit 44 receives the frequency division ratio variable signal (N + 1) 50 from the digital PLL 40, and outputs an enable signal 52 and an up / down control signal 53 (for example,
"L" (hereinafter the equivalent) is output to the load value N up / down counter A45. Then, the load value N up / down counter A45 counts down. As a result, when the overflow signal 54 becomes active, the up / down control signal 55 is set to "L".

When the up / down counter B46 receives the up / down control signal 55 (L) on the up side (when the frequency of the TCXO 11 is shifted to the higher side) together with the overflow signal 54 from the load value N up / down counter A45, +1 is counted up. Further, the up / down counter B46 is on the down side together with the overflow signal 54 from the load value N up / down counter A45 (when the frequency of the TCXO 11 is shifted to a lower side).
When the up-down control signal 55 (H) is input,
It is counted down by one.

The result of +1 count-up or -1 count-down is accumulated as frequency error data in the up / down counter B46, and finally converges to an optimum value for correcting the frequency error of the TCXO11 while repeating reception. Then, it is held in the up / down counter B46 as a learning value. During the non-reception section of the intermittent reception, the learning value accumulated in the up / down counter B46 is used as a correction value of the frequency error of the TCXO11.

The integrator 47 has an up / down counter B4
6 is integrated in units of symbols, and when the frequency of the TCXO 11 is shifted to a lower side, the frequency dividing ratio variable signal (N−1) is supplied to the variable frequency divider 43 that divides the TCXO 11 by N.
Divide) 57 is output, and the phase of the symbol clock is advanced accordingly. When the frequency of the TCXO 11 is shifted to a higher frequency, the frequency dividing ratio variable signal (N + 1 frequency division) 56 is output to the variable frequency divider 43 which divides the TCXO 11 by N, and the symbol clock of the symbol clock is correspondingly outputted. Delay the phase. Also, a digital PL with a learning correction function is set according to the time constant 48.
The correction frequency of L can be made variable.

Next, the operation of the clock recovery circuit according to the first embodiment of the present invention configured as described above will be described with reference to FIGS. 1, 3 and 4. First, when a synchronization word is detected by the synchronization word detection circuit 15 during a reception section, a digital PLL with a learning correction function is used.
Reference numeral 17 detects the frequency error of the TCXO 11 and learns its value while tracking the phase of the reproduced clock, as described in FIG. 7, and learns the value of the reception slot (for example, RX in FIGS. 3 to 5). At the end, the digital signal P with the learning correction function is supplied by the read signal 25 from the timer 16.
The learning data 26 is read from the LL 17 to the control circuit 18.

The learning data 26 is read every time synchronization is obtained. If the learning data 26 has the same value as the learning data one frame before, the learning data for correcting the frequency error of the TCXO 11 at the current voltage and temperature is the optimum value. And the learning data is stored in the memory 19. Even if the power is turned off in this state, the learning data converged to the optimum value is maintained in the memory 19.

When the power of the mobile station is turned on while the learning data is held in the memory 19, the clock recovery circuit (not shown) receives the PONR signal from the reset control unit.
The operation is started by an ST (power-on reset) signal. However, in this case, when the power is turned off, the up / down counter B46 holding the learning data 26 inside the digital PLL 17 with the learning correction function has already been initialized, and thus the previously learned data has been lost.

For this reason, the power ON detection circuit 12 sets the PON
When the RST signal is detected, a power-on detection signal 20 is output to the control circuit 18, and the control circuit 18 reads the learning data 26 at the time of convergence to the optimum value held in the memory 19, and sends the data to the digital PLL 17 with the learning correction function. Set.
In this way, the frequency of the reproduction clock can be corrected immediately after the power is turned on. Then, continuous reception in the reception mode is reduced.

Also, the power supply I
C to LVA (Low Voltage Alarm, Low Voltage A
(Larm) is output, a system reset is applied to the entire system.
The up / down counter B46 holding the learning data 26 inside 17 is initialized and the learning data 26 is lost. When the instantaneous interruption detection circuit 13 detects this LVA (low voltage alarm), it outputs an instantaneous interruption return signal 22 to the control circuit 18, and the control circuit 18 learns at the time of convergence to the optimum value stored in the memory 19. The data 26 is read out and set in the digital PLL 17 with the learning correction function. In this way, the frequency of the reproduced clock can be corrected immediately after the recovery from the instantaneous interruption. Then, continuous reception in the reception mode is reduced.

The learning data 2 for the digital PLL 17 with the learning correction function at the time of power ON detection described above.
The setting procedure of 6 is further clarified by the timing chart shown in FIG. In FIG. 3, when the PONRST signal (active L) is received, the intermittent reception in the reception mode is stopped, and the learning data 26 of the control circuit 18 is cleared. At this point, the learning data 26 at the time of convergence to the optimum value is already stored in the memory 19. Then, when the PONRST signal rises, the power ON detection circuit 12 turns the power ON.
The detection signal 20 is output, and the reception mode is switched to continuous reception. Then, the control circuit 18 outputs the power ON detection signal 2
0, the learning data 26 at the time of convergence to the optimum value is read from the memory 19, and the digital P with the learning correction function is read out.
Set to LL17.

The procedure for setting the learning data 26 in the digital PLL 17 with the learning correction function at the moment of a power interruption described above will be further clarified by the timing chart shown in FIG. In FIG. 4, when the LVA signal (active L) is received, the learning data 26 of the control circuit 18 is cleared. At this point, the learning data 26 at the time of convergence to the optimum value is already stored in the memory 19. Therefore, when the LVA signal rises, the instantaneous interruption detection circuit 13 outputs the instantaneous interruption return signal 22, and switches the reception mode from intermittent reception to continuous reception. Then, the control circuit 18 reads the learning data 26 at the time of convergence to the optimum value from the memory 19 at the fall of the instantaneous interruption return signal 22 and sets the learning data 26 in the digital PLL 17 with the learning correction function.

The memory used in the present embodiment can be rewritten by a program such as an EEPROM or a flash ROM, and can retain the stored content even when the power is turned off. Any memory can be used. Most of the means of the clock recovery circuit in the present embodiment can be realized by software.

As described above, according to the first embodiment of the present invention, phase tracking and frequency correction are performed to maintain synchronization with a base station by a clock reference generated from a received signal (IF). A digital PLL with a learning correction function to be performed, a power-on detection circuit for detecting power-on,
Instantaneous interruption detection circuit for detecting instantaneous interruption of power supply and received signal (IF)
A demodulation unit that generates demodulated data and a clock reference from the demodulated data, a synchronizing word detection circuit that detects a synchronizing word from the demodulated data, a timer that manages the time of the mobile station based on the synchronizing pulse, and learning that is used to correct the frequency of the recovered clock. By providing a memory for holding a data convergence value and a control circuit for controlling learning data between the digital PLL 17 with learning correction function and the memory 19, a power interruption occurs during power-on or during a call. Also, by setting the learning data at the time of convergence to the optimum value held in the memory in the digital PLL with the learning correction function, the frequency of the reproduction clock can be corrected at high speed. Then, continuous reception in the reception mode is reduced.

(Embodiment 2) Hereinafter, referring to FIG.
The configuration of the clock recovery circuit according to the second embodiment of the present invention will be described. In FIG. 2, reference numeral 10 denotes a received signal (I
F) a frequency counter for detecting the deterioration of the received signal due to the influence of noise, fading and the like added to F), 11 is a temperature-compensated crystal oscillator (hereinafter referred to as TCXO), 14 is the demodulated data 23 and clock reference from the received signal (IF). 21 is a demodulation unit that generates 21; 15 is a synchronization word detection circuit that detects a synchronization word from the demodulated data 23 generated by the demodulation unit 14 and outputs a synchronization pulse; 16 is a reference to a synchronization pulse that is output by the synchronization word detection circuit 15 Is a timer for managing the time of the mobile device. The frequency counter, the demodulation unit, the synchronization word detection circuit, and the timer correspond to a frequency counting unit, a demodulation unit, a synchronization word detection unit, and a timing unit, respectively.

Reference numeral 17 generates a reproduction clock (bit clock, symbol clock) synchronized with the clock reference 21 from the output of the TCXO 11 during a reception period, and corrects a frequency deviation of the reproduction clock due to a frequency error of the TCXO 11 during a non-reception period. Digital P with learning correction function
Reference numerals LL and 19 denote memories for holding a convergence value of learning data used for frequency correction of the reproduced clock. Reference numeral 18 denotes learning data between the digital PLL 17 with the learning correction function and the memory 19 based on signals from the frequency counter 10 and the timer 16. Is a control circuit that performs the control. Note that the memory and the control circuit correspond to a storage unit and a control unit, respectively.

Next, the operation of the clock recovery circuit according to the second embodiment of the present invention configured as described above will be described with reference to FIGS. First, the operation of loading the learning data 26 converged to the optimum value into the memory 19 is as described in the first embodiment, and further description will be omitted. In the present embodiment, a description will be given of a process performed when the received signal (IF) has a large noise and fading and the received signal has deteriorated. noise·
If the received signal deteriorates due to large fading, an erroneous value such as a clock reference output to an incorrect position is updated as learning data.

Therefore, the deterioration of the received signal is measured by the frequency counter 10, and the frequency NG signal 27 (800 MHz system: 11.1 ppm) from the frequency counter 10 set by the microcomputer managing the reception state
When the above deviation (1.5 GHz system: deviation of 7.3 ppm or more) is output, the control circuit 18
The learning data 26 at the time of convergence to the optimum value held in the step S1 is read out and set in the digital PLL 17 with the learning correction function. In this way, the state when the received signal is good can be maintained. Then, continuous reception in the reception mode is reduced.

The procedure for setting the learning data 26 in the digital PLL 17 with the learning correction function when the deterioration of the received signal is detected due to the influence of noise, fading, and the like described above will be further clarified by the timing chart shown in FIG. When the count state counted by the frequency counter 10 shifts, a digital PL with a learning correction function is provided.
L17 up-down counter B46 to control circuit 18
Is also NG data sent to the control circuit 18 by the read signal 25.

However, at this time, the learning data 26 at the time of convergence to the optimum value is already stored in the memory 19.
Further, when the frequency NG signal is output with the count state of the frequency counter 10 shifted, the intermittent reception in the reception mode is switched to the continuous reception at the rise of the frequency NG signal, and at the same time the control circuit 18 converges from the memory 19 to the optimum value. Is read and set in the digital PLL 17 with the learning correction function.

The memory used in the present embodiment may be any type of memory, such as an EEPROM, for example, as long as the stored contents can be easily rewritten and the stored contents can be retained even when the power is turned off. It may be something. Most of the means of the clock recovery circuit in the present embodiment can be realized by software.

As described above, according to the second embodiment of the present invention, phase tracking and frequency correction are performed to maintain synchronization with a base station by a clock reference generated from a received signal (IF). A digital PLL with a learning correction function and a received signal (I
F) a frequency counter for detecting deterioration of the received signal, a demodulation unit for generating demodulated data and a clock reference from the received signal (IF), a synchronous word detecting circuit for detecting a synchronous word from the demodulated data, and a sync pulse as a reference. A timer for managing the time of the mobile station, a memory for holding a convergence value of learning data used for frequency correction of the reproduction clock, and a control circuit for controlling learning data between the digital PLL 17 with the learning correction function and the memory 19. Is provided, the frequency of the received signal becomes unstable due to the deterioration of the received signal due to noise and fading to the received signal (IF). By setting the learning data at the time of convergence to the digital PLL with learning correction function, the state when the received signal is good It can be held. And
Continuous reception in the reception mode is reduced.

[0051]

The clock recovery circuit according to the present invention is configured as described above, and in particular, includes a power-on detection circuit for detecting power-on, a power-off detection circuit for detecting a power-off during a call, A frequency counter that detects the frequency error of the received signal (IF) due to fading, and a memory that stores learning data when convergence to the optimum value used for the frequency correction of the reproduced clock is provided. Alternatively, when the learning data is largely erroneous due to deterioration of the received signal due to noise or fading of the received signal (IF), the learning data at the time of convergence to the optimum value stored in the memory is set in the digital PLL with the learning correction function. As a result, it is not necessary to shift to the continuous reception operation for acquiring the synchronization again, so that the power consumption is low and the frequency of the reproduction clock is high. Correction can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a clock recovery circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a clock recovery circuit according to a second embodiment of the present invention.

FIG. 3 is a diagram showing timing when a power-on detection signal is generated from a power-on detection circuit in FIG. 1;

FIG. 4 is a diagram showing timing when an instantaneous interruption return signal is generated from the instantaneous interruption detection circuit in FIG. 1;

FIG. 5 is a diagram showing timing when a frequency NG signal is generated from the frequency counter in FIG. 2;

FIG. 6 is a block diagram showing a configuration of a conventional clock recovery circuit with a learning correction function capable of correcting a recovered clock in a non-receiving section.

FIG. 7 is a block diagram showing in detail the configuration of a digital PLL with a learning correction function shown in FIGS. 1, 2 and 6;

[Explanation of symbols]

10 Frequency Counter 11 TCXO (Temperature Compensated Crystal Oscillator) 12 Power ON Detection Circuit 13 Instantaneous Interruption Detection Circuit 14 Demodulation Unit 15 Synchronous Word Detection Circuit 16 Timer 17 Digital PLL with Learning Correction Function 18 Control Circuit 19 Memory 20 Power ON Detection Signal 21 Clock Reference 22 Instantaneous interruption return signal 23 Demodulation data 24 Synchronization pulse 25 Read signal 26 Learning data 27 Frequency NG signal 40 Digital PLL 41 Edge detection circuit 42 Up / down counter 43 Variable frequency divider 44 Detection circuit 45 Load value N up / down counter A 46 Up / down counter B 47 Integrator 48 Time constant 49 Enable signal (output of edge detection circuit) 50 Dividing ratio variable signal (N + 1) (up / down counter output) 51 Dividing ratio variable signal (N-1) (up Output of down counter) 52 Enable signal (output of detection circuit) 53 Up / down control signal (output of detection circuit) 54 Overflow signal 55 Up / down control signal (output of load value N up / down counter A) 56 Dividing ratio variable signal (N + 1) (output of the integrator) 57 Variable frequency division ratio signal (N-1) (output of the integrator)

Claims (2)

[Claims] 1. A digital device with a learning correction function for performing phase tracking and frequency correction of a reproduced clock so as to maintain synchronization with a base station based on a clock reference generated from a received signal and holding a convergence value of learning data for the frequency correction. PL
L, power-on detection means for detecting power-on and outputting a power-on detection signal, power-on detection means for detecting power-off and outputting a power-off recovery signal, and demodulated data and clock reference from the received signal. , A synchronization word detecting means for detecting a synchronization word from the demodulated data, a timing means for performing time management of the mobile station based on a synchronization pulse, and a convergence value of learning data used for frequency correction of a reproduction clock. Storage means for receiving and holding from the digital PLL with learning correction function, and control means for receiving a power-on detection signal or an instantaneous interruption return signal and controlling to set learning data from the storage means to the digital PLL with learning correction function A clock recovery circuit comprising: 2. A digital device with a learning correction function for performing phase tracking and frequency correction of a reproduced clock so as to maintain synchronization with a base station based on a clock reference generated from a received signal and holding a convergence value of learning data for the frequency correction. PL
L, frequency counting means for detecting a frequency error of the received signal due to noise and fading and outputting a frequency NG signal, demodulating means for generating demodulated data and a clock reference from the received signal, and detecting a synchronization word from the demodulated data. Synchronization word detection means, timing means for performing time management of the mobile station based on the synchronization pulse, and storage means for receiving and holding a convergence value of learning data used for frequency correction of a reproduced clock from the digital PLL with the learning correction function. And a control means for receiving the frequency NG signal and controlling the learning data from the storage means to be set in the digital PLL with the learning correction function.