JPH1012831A - Ferroelectric memory device and operation method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a ferroelectric memory device in which a ferroelectric capacitor hardly causes polarization fatigue even by reversal reversal, a long life and a high reliability can be maintained, and an operation method thereof. thing. SOLUTION: A ferroelectric capacitor CAP having a PZT thin film 4 provided between an iridium upper electrode 5 and an iridium lower electrode 3 is provided. The iridium upper electrode 5 is on the bit line 6 (BL) side, and the iridium lower electrode is on. 3 is drive line 32
A ferroelectric memory device connected to the (DL) side. A method of applying a negative voltage pulse to the iridium upper electrode 5 irrespective of the type of data of the bit line 6 (BL) when operating this memory device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a ferroelectric memory device (particularly, a nonvolatile semiconductor memory using a ferroelectric capacitor having a lead zirconate titanate (PZT) film) and a method of operating the same. .

[0002]

2. Description of the Related Art By forming a capacitor using PZT, which is a ferroelectric substance, as a dielectric film, a nonvolatile memory element having a simple structure using its remanent polarization characteristics, that is, an FRAM as a nonvolatile memory. A ferroelectric RAM (Ferroelectric Random Access Memory) referred to as a ferroelectric random access memory (RAM) can be manufactured.

Such an FRAM has already been partially put into practical use, its PZT capacitor is configured as shown in FIG. 9A, and its ferroelectric memory cell is shown in FIG.
It is configured as shown in FIG.

In the conventional PZT capacitor Cap shown in FIG. 9A, as a stack type cell capacitor, a P-type capacitor is generally provided on the Ti adhesive layer 13B as the lower electrode 13.
A Pt / Ti structure in which a t layer 13A is laminated is used,
The sol-gel method, sputtering method or CVD (C
A PZT thin film 14 is formed by a chemical vapor deposition method, and Pt is used as the upper electrode 15.

Referring to FIG. 9B, a memory cell of an FRAM having the above-described PZT capacitor Cap will be described. For example, an element region partitioned by a field oxide film 7 is formed on one main surface of a P ⁻ type silicon substrate 17. Formed here, and a transfer gate T composed of a MOS transistor
Memory cell M-cel including R and capacitor Cap
Is provided.

In the transfer gate TR, for example, an N ⁺ type source region 10 and an N ⁺ type drain region 8 are respectively formed by impurity diffusion, and a word line 9 (WL) is interposed between these two regions via a gate oxide film 11. And a bit line 16 (BL) is connected to the drain region 8 via a contact hole 18 of the insulating layer 1 such as SiO ₂ .

The capacitor Cap is of a so-called stack type, in which a polysilicon layer 20 is connected to the source region 10 through a contact hole 19 of the insulating layer 1, and the lower electrode 13 is further provided thereon. The PZT ferroelectric film 14 and the upper electrode 15 are sequentially stacked on the lower electrode.

The ferroelectric film 14 constituting the capacitor Cap is made of, for example, PZT, that is, a Pb (Zr, Ti) O ₃ film formed by a sol-gel method using a raw material solution. Further, the lower electrode 13 has a Pt layer 13A on the Ti layer 13B.
The upper electrode 15 in contact with the ferroelectric film 14 is made of Pt.

However, in the above-mentioned conventional FRAM, the reversal of the inversion during the operation of the PZT capacitor Cap (that is, the polarization inversion performed every time data is written and read out) is repeated. A phenomenon called "fatigue" tends to occur. This is a phenomenon which is a problem in the development of actual device, the residual polarization density is degraded by about 10 ⁶ times inversion,
It may be reduced to less than half of the initial value. For this reason, it has been difficult to develop a device having high reliability in repeated reading and writing.

[0010]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a ferroelectric memory device in which a ferroelectric capacitor is unlikely to cause polarization fatigue even by repeated inversion, and has a long life and high reliability. It is an object of the present invention to provide a method of operation.

[0011]

That is, the present invention relates to a ferroelectric device in which an upper and lower electrode mainly composed of iridium and a ferroelectric film (for example, a PZT film: hereinafter the same) are provided between these electrodes. A ferroelectric body, wherein the upper electrode (especially iridium upper electrode: the same applies hereinafter) is connected to the bit line side and the lower electrode (especially iridium lower electrode: the same applies hereinafter) is connected to the drive line side The present invention relates to a memory device.

Further, the present invention has an upper electrode and a lower electrode mainly composed of iridium, and a ferroelectric capacitor having a ferroelectric film provided between these electrodes, wherein the upper electrode is provided on the bit line side, When operating a ferroelectric memory device in which the lower electrode is connected to a drive line, a negative voltage pulse is applied to the upper electrode regardless of the type of data on the bit line. Is also provided.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the device of the present invention, specifically, a negative voltage pulse is applied to the iridium upper electrode regardless of the type of data of the bit line.

The ferroelectric film preferably comprises mainly lead zirconate titanate, which is suitable for being constituted as a nonvolatile memory.

In the method of the present invention, specifically, the iridium upper electrode of the ferroelectric capacitor is connected to the bit line side, and the iridium lower electrode is connected to the drive line side.

Further, a ferroelectric film mainly composed of lead zirconate titanate is used as the ferroelectric film, which is suitable for operating a nonvolatile memory.

[0017]

The present invention will be described below with reference to examples.

First, referring to FIG. 1, based on the present invention,
A semiconductor device incorporating a ferroelectric capacitor CAP having a PZT thin film, for example, a non-volatile memory FR
The configuration of the AM will be described. Here, CUB (Cell under
A (bitline) type memory cell will be described.

As shown in FIG. 1A, the PZ of this embodiment is
The T-capacitor CAP is a stack-type cell capacitor having an iridium (Ir) layer 3 as a lower electrode and a sol-gel method, a sputtering method or a CVD (Che
PZT formed by the mical vapor deposition method
It comprises a thin film 4 and an iridium (Ir) layer 5 provided thereon as an upper electrode.

Therefore, this capacitor CAP is characterized in that both upper and lower electrodes use iridium metal. Each of these electrodes 3 and 5 may be formed to a thickness of 100 to 300 nm (for example, 200 nm) by a vacuum evaporation method using an electron beam heating method. The PZT thin film 4 is composed of Pb: Zr:
It may be formed to a thickness of 300 nm with a composition of Ti = 1.1: 0.5: 0.5.

Referring to FIG. 1B, a memory cell of an FRAM having the above-described PZT capacitor CAP will be described. For example, an element region partitioned by a field oxide film 7 is formed on one main surface of a P ⁻ type silicon substrate 17. Formed here, and a transfer gate T composed of a MOS transistor
Memory cell M-CEL composed of R and capacitor CAP
Is provided.

In the transfer gate TR, for example, an N ⁺ type source region 10 and an N ⁺ type drain region 8 are respectively formed by impurity diffusion, and a polysilicon word line 9 (between these two regions via a gate oxide film 11). WL) is provided, and the bit line 6 (BL) is connected to the source region 10 via the contact hole 28 of the insulating layer 1 such as SiO ₂ .

The capacitor CAP is of a so-called stack type. The capacitor CAP is located on the word line 9, and its upper electrode 5 is drained by the wiring 2 made of aluminum or the like through the contact holes 29 and 30 of the insulating layer 1. Area 8
It is connected to the. On the other hand, the lower electrode 3 is connected to a drive line (not shown).

FIG. 2 shows an equivalent circuit diagram of the memory cell M-CEL. The Ir upper electrode 5 is connected to a bit line 6 (having a bit line capacitance C) via a transfer gate TR, and this bit line is further led to a sense amplifier circuit. The Ir lower electrode 3 is connected to a drive line 32 (DL) via a wiring 31.

Next, the operation of the capacitor CAP configured as described above and the memory cell M-CEL incorporating the capacitor CAP will be described.

First, the present inventor added ±
A bipolar pulse voltage of 5 V was applied, and the relationship between the remanent polarization density (Pr) and the number of times of polarization inversion when the polarization was inverted continuously was obtained. However, the composition of the PZT thin film 4 is Pb: Z
r: Ti = 1.1: 0.5: 0.5, thickness was 300 nm, and annealing temperature was 650 ° C.

FIG. 3 shows the respective characteristics of the PZT capacitor in which the lower electrode is Ir and the upper electrode is Ir, Pt or Au, and the upper and lower electrodes are Ir. The capacitor has substantially no decrease in the remanent polarization density (output 2Pr) in the measurement range up to 1 × 10 ⁹ times, and the remanent polarization density (Pr) at the time of polarization reversal is more stable than the other capacitors. It is clear that it is very good. This is considered to be attributed to the oxidation resistance of Ir metal and the like.

FIG. 6 shows a hysteresis curve of the remanent polarization density of the PZT thin film 4 (the same applies hereinafter).

Further, the present inventor has determined that the remanent polarization density (output 2Pr) with respect to the unipolar pulse of the capacitor CAP.
Was examined. As a result, when a unipolar pulse of a positive voltage (5 V) is applied to the Ir upper electrode 5, FIG.
As shown in FIG. 5, the remanent polarization density decreases with the number of pulses. However, when a unipolar pulse of a negative voltage (-5 V) is applied to the Ir upper electrode 5, the remanent polarization density decreases as shown in FIG. (Output 2Pr) was found to recover and increase with the number of pulses. However, the same PZT thin film 4 as in FIG. 3 was used.

Based on these findings, the Ir lower electrode 9
Is connected to the drive line 32 side and the Ir upper electrode 5 is connected to the bit line 6 side, it is possible to avoid the problem of polarization fatigue of the capacitor as described above.

As shown in FIG. 2, one MOS transistor TR and one PZT capacitor CAP
In the circuit configuration of the memory cell for the bit, the Ir lower electrode 3 of the PZT capacitor CAP is connected to the drive line 32 (DL).
And the Ir upper electrode 5 is connected to the MOS transistor TR.
Is connected to the bit line 6 (BL).

A method for writing and reading data to and from the memory cell will be described.

FIG. 7 shows the drive line 32 (D
L) and a timing chart of the bit line 6 (BL).

First, the word line 9 (WL) is set to a high potential to select a memory cell. Next, a positive voltage pulse (pulse width is t _WR : for example, 50 ns) is applied to the drive line 32 (DL) to reset the polarization state of the PZT capacitor CAP, and the polarization direction is changed from the Ir lower electrode 3 side. The Ir upper electrode 5 is aligned (at this time, a negative voltage pulse is applied to the Ir upper electrode 5). This polarization state corresponds to “0”.

Next, a positive voltage pulse (pulse width is set to t _WS : for example, 40 ns) is applied to the bit line 6 (BL) to reverse the polarization direction. This polarization state corresponds to "1".

In the above write operation, t _WR > t _ws
, A negative voltage pulse (t _{WR −tws} ) is applied to the Ir upper electrode 5 of the PZT capacitor CAP regardless of the type of data. Therefore, the result shown in FIG. As is clear from the above, the problem of polarization fatigue does not occur.

Next, FIG. 8 shows a timing chart at the time of reading. First, a word line 9 (WL) is set to a high potential to select a memory cell. Next, drive line 32 (DL)
A positive voltage pulse. At this time, when the data held in the PZT capacitor CAP is “0”, the polarization state does not change and the bit line potential hardly changes.

As described above, when reading "0" data, only a negative voltage pulse is applied to the Ir upper electrode 5 of the PZT capacitor CAP. Therefore, from the result shown in FIG. There is no polarization fatigue problem associated with operation.

On the other hand, when the held data is "1", the polarization state is inverted, a charge amount about twice as large as the residual polarization is released to the bit line 6 (BL), and the bit line potential rises. This rise in bit line potential is detected by a sense amplifier, and the bit line potential is forcibly raised to a high potential. This operation is data rewriting.

Also in this case, the time t _RS (for example, 40 ns) during which the bit line potential is forcibly raised to a high potential is represented by:
If it is set shorter than the time t _RR (for example, 50 ns) during which a positive voltage pulse is applied to the drive line 32 (DL), P
As a result, a negative voltage pulse (t _RR −t _RS ) was applied to the Ir upper electrode 5 of the ZT capacitor CAP. From the results shown in FIG. Does not occur.

As described above, the PZT capacitor using PZT, which has been considered to cause polarization fatigue, uses Ir metals 3 and 5 as its electrode material, and further has a negative electrode with respect to the Ir upper electrode 5. By connecting the upper and lower Ir electrodes 3 and 5 to the drive line 32 (DL) side and the bit line 6 (BL) side, respectively, so that a voltage pulse is applied, not only the polarization fatigue is avoided but also the reverse. It was found that a phenomenon of recovery occurred. This is an epoch-making knowledge, and it is possible to effectively realize a longer life and an improved reliability of the PZT capacitor CAP of the FRAM.

Although the embodiment of the present invention has been described above, the above-described embodiment can be further modified based on the technical idea of the present invention.

For example, the structure of the above-described PZT capacitor can be variously modified, and the thickness, pattern, manufacturing method, and the like of each layer are not limited to those described above. The iridium electrode is not limited to iridium alone, and may contain a small amount of another element.

The material of the ferroelectric film that can be used is P
In addition to ZT, PZT, PLT ((Pb, La) _x (Ti, Zr) _1-x ) obtained by adding Nb, Zr, Fe, etc. to PZT
O ₃ ).

The above-mentioned capacitor CAP is preferably, for example, a stacked capacitor as shown in FIG. 1, but is not limited to this, and is also applicable to a capacitor having a structure in which a capacitor is incorporated in a so-called trench. It is possible. Further, the present invention can be applied to uses other than the FRAM. Also,
The present invention is also applicable to a COB (Cell over Bitline) type memory cell.

[0046]

As described above, the present invention has an upper electrode and a lower electrode mainly composed of iridium, and a ferroelectric capacitor in which a ferroelectric film is provided between these electrodes. In particular, the iridium upper electrode is connected to the bit line side, and the other electrode (particularly, the iridium lower electrode) is connected to the drive line side. When operating this ferroelectric memory device, the type of data of the bit line is Irrespective of the above, since a negative voltage pulse is applied to the upper electrode, the ferroelectric capacitor is unlikely to cause polarization fatigue even by repeated inversion, and has a long life and can maintain high reliability. A memory device and an operation method thereof can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view of a PZT capacitor according to the present invention and a semiconductor device (FRAM) incorporating the same.

FIG. 2 is an equivalent circuit diagram of a memory cell of the device.

FIG. 3 is a graph comparing the relationship between the remanent polarization density and the number of times of polarization reversal (bipolar pulse voltage ± 5 V) of a PZT capacitor.

FIG. 4 is a graph showing a change in remanent polarization density with respect to a positive voltage unipolar pulse (5 V) of a capacitor having an Ir / PZT / Ir structure.

FIG. 5 is a graph showing a change in remanent polarization density with respect to a negative voltage unipolar pulse (−5 V) of a capacitor having an Ir / PZT / Ir structure.

FIG. 6 is a hysteresis curve diagram of a polarization value of the PZT thin film.

FIG. 7 is a timing chart of a write operation of a memory cell incorporating the Ir / PZT / Ir capacitor.

FIG. 8 is a timing chart of the read operation.

FIG. 9 is a schematic sectional view of a conventional PZT capacitor and a semiconductor device (FRAM) incorporating the same.

[Explanation of symbols]

2, 31 wiring 3 Ir lower electrode 4 ferroelectric film (PZT thin film) 5 Ir upper electrode 6 (BL) bit line 8 N ⁺ type drain Region 9 (WL) Word line 10 N ⁺ type source region 17 Silicon substrate 32 (DL) Drive line CAP Ferroelectric capacitor TR Transfer gate M- CEL: Memory cell

──────────────────────────────────────────────────の Continuing on the front page (51) Int.Cl. ⁶ Identification number Agency reference number FI Technical indication H01L 29/788 29/792 (72) Inventor Ken Numata 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Pref. (72) Inventor Akitoshi Nishimura 2355 Kihara, Miura-mura, Inashiki-gun, Ibaraki Prefecture Within Texas Instruments Instruments Inc.

Claims (9)

[Claims] An upper and lower electrode mainly composed of iridium, and a ferroelectric capacitor having a ferroelectric film provided between these electrodes, wherein the upper electrode is on the bit line side, and the lower electrode is A ferroelectric memory device connected to the drive line side. 2. The device according to claim 1, wherein the iridium upper electrode of the ferroelectric capacitor is connected to the bit line side, and the iridium lower electrode is connected to the drive line side. 3. The device according to claim 2, wherein a negative voltage pulse is applied to the iridium upper electrode irrespective of the type of bit line data. 4. The device according to claim 1, wherein the ferroelectric film is mainly composed of lead zirconate titanate. 5. The device according to claim 1, wherein the device is configured as a non-volatile memory. 6. An upper and lower electrode mainly composed of iridium, and a ferroelectric capacitor having a ferroelectric film provided between these electrodes, wherein the upper electrode is on the bit line side, and the lower electrode is A method of operating a ferroelectric memory device, comprising applying a negative voltage pulse to the upper electrode regardless of the type of data on the bit line when operating a ferroelectric memory device connected to a drive line. 7. The method according to claim 6, wherein the iridium upper electrode of the ferroelectric capacitor is connected to the bit line and the iridium lower electrode is connected to the drive line. 8. The method according to claim 6, wherein a ferroelectric film mainly composed of lead zirconate titanate is used as the ferroelectric film. 9. The non-volatile memory for operating a non-volatile memory.
The method according to any one of claims 1 to 8.