JPH10135342A - Clock wiring layout method - Google Patents

Abstract

(57) [Summary] [PROBLEMS] To provide a layout in which clock skew which is a problem in designing a semiconductor integrated circuit is suppressed. A wiring layer dedicated to clock wiring is provided in an uppermost layer, cells are arranged in step 1, and clock wiring up to the uppermost layer is performed in step 3. In step 4, wires other than the clock are wired using wiring layers other than the uppermost layer. In step 5, clock wiring in the uppermost layer is performed. With this method, the clock wiring is the same for all cells up to the top layer, so it is only necessary to suppress variations in wiring delay in the top layer, and change the wiring length and wiring width in the top layer. It is obtained by doing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit, and more particularly to a layout design method.

[0002]

2. Description of the Related Art As a conventional method for wiring clocks so as to suppress clock skew, Japanese Patent Laid-Open No.
There is a method by clock tree buffering as described in -152438. In this method, the skew is suppressed by arranging a plurality of clock buffers and wiring them among them with balanced wiring. As a second method, there is a method of supplying a clock to a clock input of a plurality of cells by a rectangular wiring as described in JP-A-6-85218.

[0003]

In the first conventional technique, the cell arrangement may move in order to secure a wiring area during the wiring in the channel wiring method, and the actual wiring delay deviates from the estimation. Therefore, there is a problem that clock skew occurs.

In the second conventional method, it is necessary to increase the capacity of a buffer for driving a rectangular wiring. Further, in this method, it is difficult to use a buffering method based on a clock tree, so that a delay from a clock input to a flip-flop may be large.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to provide a clock wiring layout method for a semiconductor circuit in which clock skew is suppressed.

[0006]

According to the clock wiring layout method of the present invention, the uppermost layer of the wiring layers of the multilayer wiring is used as a dedicated wiring layer for the clock, and the clock wiring from the clock terminal of each cell to the dedicated clock wiring layer is provided. Vias are piled up, and wiring other than clocks is performed, and then clock wiring in the uppermost layer is performed.

[0007]

FIG. 1 shows a processing flow of a clock wiring layout method according to an embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a cell arranging step, 2 denotes an additional arranging step of a clock tree buffer cell, 3 denotes a clock wiring step up to the uppermost layer, 4 denotes a wiring step of signals other than the clock, and 5 denotes an upper layer. Represents a clock wiring step.

[0008] As step 1, cell arrangement 1 is executed. This step is automatically arranged by a computer according to the connection information or performed manually.

As a step 2, an additional arrangement 2 of clock tree buffer cells is executed. This step can be omitted depending on the magnitude of the delay caused by the clock wiring. This is because when the number of cells to which a clock is input is small, wiring with reduced delay can be performed without adding a clock tree buffer cell.

In step 3, vias are stacked on the clock terminals of the arranged cells, and wiring 3 up to the uppermost layer is performed.
When the clock tree buffer cell is added in the step 2, the vias are also stacked for the input / output terminals of the clock tree buffer cell, and the clock wiring up to the uppermost layer is performed.

In step 4, wirings 4 for signals other than clocks are made using wiring layers other than the uppermost layer.

In step 5, clock wiring is performed using the uppermost clock-dedicated wiring layer. At this time, the wiring is changed so that the skew to each cell is reduced by changing the wiring length and the wiring width in the uppermost wiring layer. In the case where one clock tree buffer cell is added in the step 2, the wiring from the output of the buffer cell to the clock terminal of the cell arranged in the step 1 is performed in the step 5, wiring from the buffer cell to the input. Perform

The cells in the above step 1 are not limited to standard cells, but may be cells such as RAM and ROM.

FIG. 2 is a diagram in which a layout manufactured by the processing procedure of the present embodiment is separated for each layer. 2, reference numeral 6 denotes a clock wiring layer, 7 denotes a clock wiring, 8 denotes a signal wiring layer, 9 denotes a signal wiring, 10 denotes a cell configuration layer, and 11 denotes a cell. How a layout is produced in each step according to the present embodiment will be described with reference to FIG.

At the stage when the steps 1 and 2 are completed,
Up to the cell constituting layer 10 in FIG.

When the steps 3 and 4 are completed, the steps up to the signal wiring layer 8 in FIG. 2B are completed. In the step 3, only the clock wiring 7 of the signal wiring layer 8 in FIG. 2 is wired, and in the step 4, all wiring of the signal wiring layer 8 is completed. The layout of the cell constituting layer 10 and the signal wiring layer 8 is completed by the steps up to here.

In step 5, the clock wiring 7 of the clock wiring layer 6 in FIG.

Although FIG. 2 shows only one wiring layer for the signal wiring, a plurality of wiring layers for the signal wiring may be used in an actual layout.

Further, by increasing the thickness of the interlayer insulating film between the uppermost layer and the other wiring layers, the wiring capacity of the clock wiring is reduced, and the wiring delay of the clock wiring can be reduced.

[0020]

As described above, according to the clock wiring layout method of the present invention, when the clock wiring is formed in the uppermost clock wiring layer, since the other signal wiring has already been completed, the position of the cell is not increased. Has been determined. Further, since the wiring from each cell to the uppermost wiring layer is the same for all cells, skew occurs only in the uppermost wiring.
Therefore, clock skew can be suppressed only by wiring while suppressing variation in wiring delay in the uppermost wiring layer.

Further, since the clock tree buffering technique can be easily applied, it is possible to suppress the clock delay, and there is an effect that a high-capacity buffer is not required for driving the clock wiring.

[Brief description of the drawings]

FIG. 1 is a processing flowchart of a clock wiring layout method according to an embodiment of the present invention;

FIG. 2 is a view in which a layout manufactured according to the embodiment is separated for each layer;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Cell arrangement process 2 Clock tree buffer cell arrangement process 3 Clock wiring process up to uppermost layer 4 Wiring process other than clock 5 Clock wiring process in uppermost layer 6 Clock wiring layer 7 Clock wiring 8 Signal wiring layer 9 Signal wiring 10 Cell configuration layer 11 cells

Claims (1)

[Claims] In a method of laying out a semiconductor integrated circuit having a multilayer wiring structure, a first step of arranging cells and a second step of arranging vias from a clock pin of a cell to an uppermost wiring layer are performed. The second procedure, the third procedure for wiring other than the clock using the wiring layer other than the top layer, and the fourth procedure for wiring the clock using only the top wiring layer are provided. Characteristic clock wiring layout method.