JPH10145367A - Atm-to-stm conversation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an ATM/STM conversion circuit which has a simple constitution and can deal with the change of the delay variance value of cells, when the data are transferred in an ATM network. SOLUTION: Plural conversion parts (1) to (4), which have the FIFO type data memory parts 21 to store plural cells and are connected in parallel to each other, are prepared together with a distribution part 1, which decides the effective cells inputted from an ATM network and distributes in sequence only the effective cell information to the parts (1) to (4), and a multiplexing part 3 which successively fetches the cell information from those parts 2 and multiplexes the cell information to output them to the STM network. Every part 2 has the capacity of the part 21 to store a prescribed number of basic cells and is standardized. The parts 21 are connected in parallel to each other and have same memory capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM / STM conversion circuit for converting cells input from an ATM (asynchronous transfer mode) network and outputting the converted cells to an STM (synchronous transfer mode) network. ATM that can easily respond to changes in cell delay variation in transmission with a simple configuration
/ STM conversion circuit.

[0002]

2. Description of the Related Art Normally, in a communication system, as shown in FIG. 3, a subscriber transmission line of a communication network connected to data terminals 41 and 46 as subscribers is synchronized with an ST.
M and the data terminal device 41,
The data line terminators 42 and 45 connected to 46 are STM
Included in the net.

[0003] On the other hand, since the ATM system is employed for the relay transmission line portion to effectively use the transmission line, the STM / AT
The STM network and the ATM network are connected via the M converter 43 and the ATM / STM converter 44. Normally, the ATM network includes a cross-connect and multiplexing function, and a change in a path route or a change in accommodating a path in data communication is performed.

[0004] Therefore, after passing through the ATM network, the ATM / S
As shown in FIG. 4, the ATM input signals input to the TM conversion device 44 include cells B, C, D, E,.
The time + t1, -t1, -t2,
A delay fluctuation of + t2, to has occurred. This delay time ± tm
Is usually determined by the amount of traffic in the ATM network or the like. However, when the number of cross-connect passage stages changes due to a change in a path route or the like, the fluctuation range may be large.

[0005] As shown in FIG.
In the TM / STM conversion circuit 200, the data memory unit 20
The write control unit 202 checks the header of the cells received by the ATM 1 as the ATM input signal 11 from the ATM network, and instructs the data memory unit 201 to write and store only valid cells. On the other hand, the cells stored in the data memory unit 201 are read out as the STM output signal 31 at regular intervals in accordance with the read timing 32 received by the read control unit 203 from the STM network.

The data memory section 201 sequentially stores cells A, B,... Of the ATM input signal 11 in a FIFO (first-in first-out) manner with a fixed reference phase T0.
Output as TM output signal 31. However, as described above, in the ATM network, since conditions such as cross-connection and multiplexing operate on a cell basis, a delay variation of + tn to -tn occurs with respect to the reference phase T0.

[0007] With such hardware for converting signals, it is very difficult to determine the required storage amount provided in the data memory unit.

In order to output these input cells in order, in FIG. 4, the maximum amount of cell fluctuation is set to 1.
A state is shown in which the storage capacity of the data memory unit 201 is set to five times and the buffer amount to four cells.

[0009]

SUMMARY OF THE INVENTION The conventional ATM described above.
In the / STM conversion circuit, the delay variation of the input cell is A
Since it greatly changes depending on the configuration in the TM network, many kinds of data memory units having different internal memory amounts are required as hardware in order to cope with this change. As a result, in order to cope with a large change, When the memory capacity is increased, the data can be output without error, but the data delay is large. On the other hand, if the memory capacity of the memory is limited, a memory underflow or overflow occurs,
A value must be set in consideration of a margin that does not cause underflow or overflow of the memory. Therefore, there is a problem that it is very difficult to appropriately set the memory capacity in the ATM / STM conversion circuit.

As shown in FIG. 5, when the memory has a one-sided configuration, when changing the memory capacity, it is necessary to change the parameters of the data memory unit, the write control unit, and the read control unit. There is a problem that hardware cannot be shared.

An object of the present invention is to solve the above-mentioned problems by providing an ATM / STM conversion circuit which can easily cope with a change in the amount of delay variation of cells in data transmission in an ATM network with a simple configuration. .

[0012]

An ATM / S according to the present invention.
The TM conversion circuit is an ATM / STM conversion circuit that converts cells input from the ATM network and outputs the cells to the STM network.
A plurality of data memories in a FIFO format are provided to determine valid cells from input cells. Then, only the valid cells are sequentially stored in the plurality of data memories, and the stored valid cells are sequentially taken out at a predetermined read timing. Output.

[0013] By providing only a plurality of conversion units corresponding to the assumed amount of delay variation of the cells, the conversion units are provided with the storage capacity of the memory by the number of arrangements, while the processing speed is reduced, so that the circuit is downsized. In addition, it is possible to simplify and easily cope with a change in an assumed fluctuation amount.

More specifically, the ATM / STM conversion circuit sequentially distributes only a plurality of conversion units having a FIFO-type data memory for storing a plurality of cells and valid cells input from an ATM network to the conversion units. And a multiplexing unit for sequentially extracting and multiplexing the output of the conversion unit and outputting the multiplexed output to the STM network.

Since the distribution unit determines a valid cell, the configuration of the write control function of the conversion unit is simplified as compared with the prior art.

Further, the data memory has a capacity for storing a predetermined number of basic cells, and the ATM / STM conversion circuit includes the conversion units having data memories of the same memory capacity in parallel. The configuration is further simplified.

[0017]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a functional block diagram showing an embodiment of the present invention. ATM / STM shown in FIG.
The conversion circuit includes a distribution unit 1, four conversion units 2, and a multiplexing unit 3. Each conversion unit 2
As shown in (B), it is assumed that the data memory unit 21, the write control unit 22, and the read control unit 23 are configured.

The difference from the conventional ATM / STM
A plurality of (four in FIG. 1) conversion units having the same circuit configuration as the conversion circuit are provided in parallel for each channel, and the ATM input signal 1
1 is provided with a distribution unit 1 for sequentially distributing 1 to a plurality of conversion units 2 and a multiplexing unit 3 for sequentially taking out from the plurality of conversion units 2 and sending out the STM output signal 31.

First, each component will be described with reference to FIG.

The distribution unit 1 receives cells constituting the ATM input signal 11 as the ATM input signal 11 from the ATM network,
It is assumed that it is determined whether the received cell is valid or invalid, and only the valid cell is sequentially distributed and output as the ATM input signal 24 of the conversion unit 2 from the conversion unit (1) to the conversion unit (4).

The conversion unit 2 receives the valid cells received from the distribution unit 1 as an ATM input signal 24, and sequentially stores the information of the received valid cells in the data memory 21 under the control of the write control unit 22. The cell information stored in the data memory unit 21 is read out as an STM output signal 26 in the order of writing based on the read timing 25 received from the conversion unit 25. The conversion unit (1) to the conversion unit (4) have the same circuit configuration. And are connected in parallel.

The configuration of the conversion unit 2 is the same as that of the conventional ATM / S
The same as the TM conversion circuit, but the memory capacity of the data memory is small, it is not necessary to judge valid cells in the write control, and the read control has a large time interval and can be processed at a low speed. Becomes

The multiplexing unit 3 sequentially distributes the read timing 32 received from the STM network side to each of the conversion units (1) to (4) as the read timing 25 based on the number of the conversion units 2, and reads out the read cell information. As an STM output signal 26, and the logical sum of the STM output signal 26 sequentially received from each of the conversion units (1) to (4) is obtained, and S is output as an STM output signal 31.
It shall be transmitted to the TM network.

Next, referring to FIG. 1 and FIG.
The function of will be described.

First, valid cells (information A, B, C, D,...) Are input as ATM input signals 11 to the distribution unit 1 sequentially in combination with invalid cells. The distribution unit 1 determines a valid cell,
First, the valid cell information A is converted into the input signal 24 of the conversion unit (1), the valid cell information B is converted into the input signal 24 of the conversion unit (2), and the valid cell information D is converted into the input signal 24 of the conversion unit (4). Then, the next valid cell information E to H are sequentially transmitted as input signals 24 of the conversion units (1) to (4) following the previous information.

In the example of FIG. 2, each of the conversion units (1) to (4) first writes the information of the valid cell information A to D received as the input signal 24 to the first address based on the write timing. Next, the received valid cell information E to H is written in the second address, so that the received valid cell information is sequentially written in the input order. At this time, the writing address to the data memory is controlled by the distribution unit 1 by a reset signal or the like so that the conversion unit (1) to (4) have the same address.

The multiplexing unit 3 converts each of the conversion units (1) to (4) based on a cycle four times the read timing 32 received from the STM side.
The read timing 25 is sequentially supplied to (4).
Each of the conversion units (1) to (4) receives the read timing 2
5, the stored cell information is sequentially read out from the oldest one. In the example of FIG. 2, the read timing is a time delayed by a time ΔT from the time of writing to the first address,
The time at which the reading is started from the first address is set. At this time, the read address to the data memory is controlled by the multiplexing unit 3 by a reset signal or the like so that each of the conversion units (1) to (4) has the same address.

Therefore, after each of the cell information A to D is sequentially read from the first address of each of the conversion units (1) to (4), the cell information E to H is sequentially read from the second address. The read and read cell information A to H are ORed in the multiplexing unit 3 and sent to the STM network side as the STM output signal 31 in the order of the cell information A, B, C, D, E,. You.

As described above, since four converters are provided in the conversion unit, the operation processing speed is "1/4". On the other hand, when the number of parallel units is increased, the entire memory is used. The capacity will increase.

Although the number of input / output lines varies depending on the number of conversion units, the distribution unit and the multiplexing unit are relatively simple in function as described above. It is possible.

As for the conversion unit, it is possible to cope with various types of systems only by preparing hardware having basic numerical values (for example, a 10-cell buffer or a 100-cell buffer). For example, if the delay variation width is assumed to be 40 cells, four 10-cell buffers are installed,
Assuming that the number of cells is 500, it can be understood that five cells having a 100-cell buffer need only be installed.

The conversion unit including the buffer memory of the cell and its peripheral circuit has been simplified compared to the conventional one, but since it is plural, a distribution unit and a multiplexing unit are newly required. However, since the distribution unit and the multiplexing unit are relatively simple circuits, and the conversion unit may be of a type having basic numerical values, standardization of hardware such as LSI (Large Scale Integrated Circuit) is required. Is possible.

In the above description, the distribution unit, the conversion unit, and the multiplexing unit are distributed and functioned around the cell buffer and illustrated. However, separation and merging of the functions is free as long as the above functions are satisfied. It does not limit the invention.

[0035]

As described above, according to the present invention, the distribution unit sequentially distributes only valid cells input from the ATM network to a plurality of conversion units having a FIFO type data memory for storing a plurality of cells. On the other hand, the multiplexing section sequentially takes out and multiplexes the storage cell information of the conversion section and outputs it to the STM network.
A TM / STM conversion circuit is obtained, and the data memory has a capacity to store a predetermined number of basic cells.
On the other hand, the converters are provided in parallel, and the data memories of these converters have the same memory capacity.

With this configuration, the ATM / S according to the present invention can be used.
Since the TM conversion circuit has a plurality of conversion units in parallel, the operation processing speed can be reduced and the circuit can be simplified, and the conversion units can be simplified and standardized, so that the equipment can be easily added and changed, and therefore, the environment changes. Has the effect of being able to respond flexibly to

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing an embodiment of the present invention.

FIG. 2 is a waveform diagram showing a timing relationship of a main part in FIG.

FIG. 3 is a schematic connection diagram illustrating an example of a communication system.

FIG. 4 is an explanatory waveform diagram showing an example of “fluctuation” of a cell when passing through an ATM network.

FIG. 5 is a functional block diagram showing an example of the related art.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 distribution unit 2 conversion unit 3 multiplexing unit 21 data memory unit 22 write control unit 23 read control unit

Claims (3)

[Claims] An ATM / STM conversion circuit for converting a cell input from an ATM (asynchronous transfer mode) network and outputting the converted cell to an STM (synchronous transfer mode) network includes a plurality of data memories in a FIFO (first in first out) format. A valid cell is discriminated from input cells, and then only the valid cells are sequentially stored in the plurality of data memories, while the stored valid cells are sequentially extracted and output at a predetermined read timing. STM conversion circuit. 2. Converting a cell input from an ATM network to S
An ATM / STM conversion circuit for outputting to a TM network, a plurality of conversion units having a FIFO type data memory for storing a plurality of cells, and a distribution unit for sequentially distributing only valid cells input from the ATM network to the conversion unit. An ATM / STM conversion circuit comprising: a multiplexing unit for sequentially taking out and multiplexing the output of the conversion unit and outputting the multiplexed data to an STM network. 3. The data memory according to claim 1, wherein the data memory has a capacity for storing a basic number of cells, and the conversion units having the data memory of the same memory capacity are provided in parallel. An ATM / STM conversion circuit characterized by simplifying the configuration.