JPH10150331A - Power amplifier - Google Patents

Abstract

(57) [Problem] To provide a power amplifier that requires an output voltage exceeding a maximum rated voltage of a cascode-connected transistor without saturating the output voltage to a voltage at which a lower transistor is saturated with respect to a power supply voltage. Can be taken out large. A bias circuit for an upper transistor in a cascode connection, a bias circuit for an upper transistor, and a sum of a gate-source voltage of an upper transistor and a collector-emitter saturation voltage of a lower transistor. A zener diode 5 having the above-mentioned zener voltage is provided to prevent the lower transistor 1 from becoming saturated before the upper transistor 2 becomes saturated when the input voltage applied to the lower transistor 1 increases. I do.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a power amplifier used for power amplification of a signal such as a voice signal.

[0002]

2. Description of the Related Art Conventionally, a power amplifier having a power supply voltage exceeding a maximum collector-emitter voltage of a transistor has a configuration shown in FIG. In FIG. 1, the power amplifier has an upper MOS field effect transistor 22 and a lower N type bipolar transistor 21 cascaded to a power supply Vcc, and a bias resistor is provided between the drain and gate of the field effect transistor 22. 24, and the field effect transistor 22
A bias resistor 23 is connected between the gate of the bipolar transistor 21 and the emitter of the bipolar transistor 21. A load 2 is connected between the emitter of the bipolar transistor 21 and the ground.
5 are connected in series, and the base of the bipolar transistor 21 is connected to the input terminal 27.

In this configuration, the power supply voltage is adjusted by a resistor 23,
The difference between the voltage divided at 24 and the output voltage generated at both ends of the load 25 is used as a bias voltage as the field effect transistor 2.
2, the voltage between the drain and the source of the field effect transistor 22 and the voltage between the collector and the emitter of the bipolar transistor 21 are suppressed within the maximum rated voltage.

[0004]

However, in the conventional cascode connection type power amplifier as described above, the sum of the drain-source voltage of the field effect transistor 22 and the collector-emitter saturation voltage of the bipolar transistor 21 is equal to that of the bipolar transistor. 21 is larger than the collector-emitter voltage of the field-effect transistor 2
The bipolar transistor 21 is saturated before the drain-source voltage of No. 2 becomes minimum, so that the power supply voltage cannot be used effectively to the maximum, and the output voltage cannot be taken large.

The present invention has been made in view of the above circumstances, and in a power amplifier that requires an output voltage exceeding the maximum rated voltage of a cascade-connected transistor, the output voltage is made as large as possible with respect to the power supply voltage. It is an object to provide a power amplifier that can be extracted.

[0006]

According to the present invention, there is provided a power amplifier having upper and lower transistors cascode-connected to a power supply. A Zener diode having a Zener voltage not less than the sum of the gate-source voltage or the collector-emitter voltage of the transistor and the collector-emitter or gate-source saturation voltage of the lower transistor is provided.

According to the present invention, the lower transistor is prevented from being saturated before the upper transistor is saturated when the input voltage applied to the lower transistor is increased by the Zener diode. As a result, the output voltage can be taken out to a voltage at which the lower transistor is saturated with respect to the power supply voltage.

[0008]

The invention according to claim 1 of the present invention has upper and lower transistors each comprising one of a field effect transistor and a bipolar transistor cascode-connected to a power supply, and A load is connected in series to an output side of the lower transistor, and a bias voltage of the upper transistor is provided by dividing a power supply voltage and an output voltage generated at both ends of the load by resistance. Between the bias input terminal of the lower transistor and the load connection terminal of the lower transistor, the gate-source voltage or the collector-emitter voltage of the upper transistor and the collector-emitter or gate-source saturation of the lower transistor. A Zener diode with a Zener voltage equal to or greater than the sum of Characterized in that it was.

According to a second aspect of the present invention, the zener diode prevents the lower transistor from being saturated before the upper transistor is saturated when the input voltage applied to the lower transistor is increased. It is characterized by doing.

Therefore, when the input voltage applied to the lower transistor increases, the Zener diode prevents the lower transistor from being saturated before the upper transistor is saturated. The voltage or the voltage between the collector and the emitter is minimized, and the output voltage can be largely extracted without saturating the output voltage up to the voltage at which the lower transistor is saturated with respect to the power supply voltage.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram of a power amplifier according to an embodiment of the present invention. In FIG. 1, the power amplifier has an upper MOS field effect transistor 2 and a lower N type bipolar transistor 1 cascaded to a power supply Vcc, and a bias resistor is provided between the drain and gate of the field effect transistor 2. The bias resistor 3 and the Zener diode 5 are connected in series between the gate of the field effect transistor 2 and the emitter of the bipolar transistor 1. A load 6 is connected in series between the emitter of the bipolar transistor 1 and the ground, and the base of the bipolar transistor 1 is connected to the input terminal 7. The Zener diode 5 has a Zener voltage equal to or higher than the sum of the gate-source voltage of the field effect transistor 2 and the collector-emitter saturation voltage of the bipolar transistor 1.

In this configuration, when an input voltage Vi is applied to the input terminal 7, the bipolar transistor 1 is turned on in accordance with the input voltage Vi, and its emitter current flows through the load 6, so that the output voltage Vo is applied across the load 6. Occurs. Here, a voltage obtained by subtracting the Zener voltage Vz of the Zener diode 5 from the difference between the power supply voltage Vcc and the output voltage Vo is divided by the resistors 3 and 4 and supplied to the gate of the field effect transistor 2 as the bias Vg. As a result, the voltage between the collector and the emitter of the bipolar transistor 1 and the voltage between the drain and the source of the field-effect transistor 2 are each maintained within the maximum rated voltage.

Now, assuming that the output voltage Vo approaches the power supply voltage Vcc, the difference voltage of Vcc-Vo becomes the Zener voltage Vcc.
If z is larger than z, the Zener voltage Vz of the Zener diode 5 is Vz> Vgs + Vcesat.
The bipolar transistor 1 does not saturate. When the output voltage Vo further increases and Vcc−Vo <Vz, the Zener diode 5 turns off, the gate voltage Vg of the field effect transistor 2 becomes Vg = Vcc, and the drain-source voltage Vds of the field effect transistor 2 Is minimized. Here, since the Zener voltage Vz of the Zener diode 5 satisfies Vz> Vgs + Vcesat, the bipolar transistor 1 is saturated after Vg = Vcc, that is, after the drain-source voltage Vds of the field effect transistor 2 becomes minimum. However, the output voltage Vo becomes the maximum voltage with respect to the power supply voltage.

As described above, according to the present embodiment, the Zener diode 5 having a Zener voltage equal to or higher than the sum of the gate-source voltage of the field-effect transistor 2 and the collector-emitter saturation voltage of the bipolar transistor 1 is used. By providing the bias circuit of the transistor 2, it is possible to prevent the collector-emitter of the bipolar transistor 1 from being saturated before the drain-source voltage of the field-effect transistor 2 is minimized. The output voltage can be extracted without saturating the output voltage, the loss can be reduced in a power amplifier that requires an output voltage exceeding the maximum rated voltage of the transistor, and the power supply voltage can be effectively used to the maximum.

In the above description, a field effect transistor is used as the upper transistor 2 and a lower transistor 1 is used as the upper transistor 2.
Although a circuit example using a bipolar transistor has been described above, the present invention is not limited to this, and the present invention can be similarly implemented in a circuit using a bipolar transistor for the upper transistor 2 and a field effect transistor for the lower transistor 1. is there.

[0017]

As described above, according to the present invention, in a power amplifier that requires an output voltage exceeding the maximum rated voltage of a cascode-connected transistor, the power amplifier outputs a voltage up to a voltage at which the lower transistor is saturated with respect to the power supply voltage. There is an effect that the voltage can be largely extracted without saturating the voltage, and the loss of the amplifier can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a power amplifier according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a conventional power amplifier.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Upper-stage transistor 2 Lower-stage transistor 3 Bias resistor 4 Bias resistor 5 Zener diode 6 Load 7 Input terminal

Claims (2)

[Claims] 1. A power supply system comprising upper and lower transistors each comprising one of a field effect transistor and a bipolar transistor cascode-connected to a power supply, and a load connected in series to an output side of the lower transistor. A power amplifier for applying a bias voltage of the upper transistor by dividing a power supply voltage and an output voltage generated between both ends of the load by a resistance, wherein a bias input terminal of the upper transistor and a load connection of the lower transistor are provided. A Zener diode having a Zener diode having a Zener voltage equal to or greater than the sum of the gate-source voltage or the collector-emitter voltage of the upper transistor and the collector-emitter or gate-source saturation voltage of the lower transistor is connected in series between the terminals. A power amplifier, wherein the power amplifier is connected to a power amplifier. 2. The zener diode according to claim 1, wherein when the input voltage applied to the lower transistor increases, the lower transistor does not become saturated before the upper transistor becomes saturated. Power amplifier.