JPH10154098A5 - - Google Patents

Info

Publication number
JPH10154098A5
JPH10154098A5 JP1997309598A JP30959897A JPH10154098A5 JP H10154098 A5 JPH10154098 A5 JP H10154098A5 JP 1997309598 A JP1997309598 A JP 1997309598A JP 30959897 A JP30959897 A JP 30959897A JP H10154098 A5 JPH10154098 A5 JP H10154098A5
Authority
JP
Japan
Prior art keywords
processing unit
instruction
central processing
cache memory
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1997309598A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10154098A (ja
JP4057114B2 (ja
Filing date
Publication date
Priority claimed from US08/748,855 external-priority patent/US5893142A/en
Application filed filed Critical
Publication of JPH10154098A publication Critical patent/JPH10154098A/ja
Publication of JPH10154098A5 publication Critical patent/JPH10154098A5/ja
Application granted granted Critical
Publication of JP4057114B2 publication Critical patent/JP4057114B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP30959897A 1996-11-14 1997-10-24 キャッシュを有するデータ処理システムおよびそのための方法 Expired - Fee Related JP4057114B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US748855 1985-06-26
US08/748,855 US5893142A (en) 1996-11-14 1996-11-14 Data processing system having a cache and method therefor

Publications (3)

Publication Number Publication Date
JPH10154098A JPH10154098A (ja) 1998-06-09
JPH10154098A5 true JPH10154098A5 (2) 2005-06-30
JP4057114B2 JP4057114B2 (ja) 2008-03-05

Family

ID=25011219

Family Applications (1)

Application Number Title Priority Date Filing Date
JP30959897A Expired - Fee Related JP4057114B2 (ja) 1996-11-14 1997-10-24 キャッシュを有するデータ処理システムおよびそのための方法

Country Status (3)

Country Link
US (1) US5893142A (2)
JP (1) JP4057114B2 (2)
KR (1) KR100492041B1 (2)

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US5956746A (en) * 1997-08-13 1999-09-21 Intel Corporation Computer system having tag information in a processor and cache memory
US6055610A (en) * 1997-08-25 2000-04-25 Hewlett-Packard Company Distributed memory multiprocessor computer system with directory based cache coherency with ambiguous mapping of cached data to main-memory locations
US6401196B1 (en) * 1998-06-19 2002-06-04 Motorola, Inc. Data processor system having branch control and method thereof
US6598155B1 (en) * 2000-01-31 2003-07-22 Intel Corporation Method and apparatus for loop buffering digital signal processing instructions
US6519684B1 (en) * 1999-11-23 2003-02-11 Motorola, Inc. Low overhead method for selecting and updating an entry in a cache memory
US6963965B1 (en) 1999-11-30 2005-11-08 Texas Instruments Incorporated Instruction-programmable processor with instruction loop cache
JP2001195302A (ja) * 1999-11-30 2001-07-19 Texas Instr Inc <Ti> 命令ループ・バッファ
US6567895B2 (en) * 2000-05-31 2003-05-20 Texas Instruments Incorporated Loop cache memory and cache controller for pipelined microprocessors
US20040088682A1 (en) * 2002-11-05 2004-05-06 Thompson Ryan C. Method, program product, and apparatus for cache entry tracking, collision detection, and address reasignment in processor testcases
US7249248B2 (en) * 2002-11-25 2007-07-24 Intel Corporation Method, apparatus, and system for variable increment multi-index looping operations
KR20060081413A (ko) * 2003-09-16 2006-07-12 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 스위칭 가능 장치 및 그 작동 방법
AT500858B8 (de) * 2004-08-17 2007-02-15 Martin Schoeberl Instruction cache für echtzeitsysteme
US20060190710A1 (en) * 2005-02-24 2006-08-24 Bohuslav Rychlik Suppressing update of a branch history register by loop-ending branches
US20090055589A1 (en) * 2007-08-24 2009-02-26 Arm Limited Cache memory system for a data processing apparatus
JP5159258B2 (ja) * 2007-11-06 2013-03-06 株式会社東芝 演算処理装置
US9398033B2 (en) 2011-02-25 2016-07-19 Cavium, Inc. Regular expression processing automaton
US9525630B2 (en) 2011-08-02 2016-12-20 Cavium, Inc. Method and apparatus for assigning resources used to manage transport operations between clusters within a processor
US9203805B2 (en) * 2011-11-23 2015-12-01 Cavium, Inc. Reverse NFA generation and processing
US9557999B2 (en) * 2012-06-15 2017-01-31 Apple Inc. Loop buffer learning
US9753733B2 (en) 2012-06-15 2017-09-05 Apple Inc. Methods, apparatus, and processors for packing multiple iterations of loop in a loop buffer
US9426166B2 (en) 2013-08-30 2016-08-23 Cavium, Inc. Method and apparatus for processing finite automata
US9563399B2 (en) 2013-08-30 2017-02-07 Cavium, Inc. Generating a non-deterministic finite automata (NFA) graph for regular expression patterns with advanced features
US9426165B2 (en) 2013-08-30 2016-08-23 Cavium, Inc. Method and apparatus for compilation of finite automata
US9183155B2 (en) * 2013-09-26 2015-11-10 Andes Technology Corporation Microprocessor and method for using an instruction loop cache thereof
US9419943B2 (en) 2013-12-30 2016-08-16 Cavium, Inc. Method and apparatus for processing of finite automata
US9275336B2 (en) 2013-12-31 2016-03-01 Cavium, Inc. Method and system for skipping over group(s) of rules based on skip group rule
US9544402B2 (en) 2013-12-31 2017-01-10 Cavium, Inc. Multi-rule approach to encoding a group of rules
US9667446B2 (en) 2014-01-08 2017-05-30 Cavium, Inc. Condition code approach for comparing rule and packet data that are provided in portions
US9602532B2 (en) 2014-01-31 2017-03-21 Cavium, Inc. Method and apparatus for optimizing finite automata processing
US9904630B2 (en) 2014-01-31 2018-02-27 Cavium, Inc. Finite automata processing based on a top of stack (TOS) memory
US9471322B2 (en) 2014-02-12 2016-10-18 Apple Inc. Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
US10110558B2 (en) 2014-04-14 2018-10-23 Cavium, Inc. Processing of finite automata based on memory hierarchy
US9438561B2 (en) * 2014-04-14 2016-09-06 Cavium, Inc. Processing of finite automata based on a node cache
US10002326B2 (en) 2014-04-14 2018-06-19 Cavium, Inc. Compilation of finite automata based on memory hierarchy

Family Cites Families (11)

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US4763253A (en) * 1986-09-26 1988-08-09 Motorola, Inc. Microcomputer with change of flow
JPH0452741A (ja) * 1990-06-14 1992-02-20 Toshiba Corp キャッシュメモリ装置
JPH06318174A (ja) * 1992-04-29 1994-11-15 Sun Microsyst Inc キャッシュ・メモリ・システム及び主メモリに記憶されているデータのサブセットをキャッシュする方法
US5513335A (en) * 1992-11-02 1996-04-30 Sgs-Thomson Microelectronics, Inc. Cache tag memory having first and second single-port arrays and a dual-port array
JPH06243036A (ja) * 1993-02-12 1994-09-02 Hitachi Ltd キャッシュ制御システム
US5479641A (en) * 1993-03-24 1995-12-26 Intel Corporation Method and apparatus for overlapped timing of cache operations including reading and writing with parity checking
JP2701703B2 (ja) * 1993-09-03 1998-01-21 日本電気株式会社 キャッシュメモリ
US5666505A (en) * 1994-03-11 1997-09-09 Advanced Micro Devices, Inc. Heuristic prefetch mechanism and method for computer system
US5749090A (en) * 1994-08-22 1998-05-05 Motorola, Inc. Cache tag RAM having separate valid bit array with multiple step invalidation and method therefor
US5535360A (en) * 1994-08-31 1996-07-09 Vlsi Technology, Inc. Digital computer system having an improved direct-mapped cache controller (with flag modification) for a CPU with address pipelining and method therefor
US5822755A (en) * 1996-01-25 1998-10-13 International Business Machines Corporation Dual usage memory selectively behaving as a victim cache for L1 cache or as a tag array for L2 cache

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